#--  Synopsys, Inc.
#--  Version J-2015.03M-SP1-2
#--  Project file C:\release\parallel_cam_video_ref_design\synthesis\run_options.txt
#--  Written on Tue Dec 06 10:37:33 2016


#project files
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/APB_WRAPPER.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/AR0330_CAM_TOP/Audio_CCC/AR0330_CAM_TOP_Audio_CCC_FCCC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/AR0330_CAM_TOP/FCCC_0/AR0330_CAM_TOP_FCCC_0_FCCC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/AR0330_CAM_TOP/FCCC_1/AR0330_CAM_TOP_FCCC_1_FCCC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/AR0330_Parallel_IF.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/bus_cdc_synchornizer_hdl.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/vita_data_ddr_write.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/cdcfiforam.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/cdcfifo.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/vita_data_pack.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/AR0330_PRL_IF/AR0330_PRL_IF.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/CLK_GEN.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_Loopbck.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_REG.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/DMA_FSM.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_RX.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_RX_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_TX.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/I2S_TX_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/WS_GEN.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/i2s_clockmux.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/Audio_Controller/Audio_Controller.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/DisplayEnhancements/1.0.1/Obfuscated/cos_mem.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/DisplayEnhancements/1.0.1/Obfuscated/sin_mem.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/DisplayEnhancements/1.0.1/Obfuscated/Display_Enhancements.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/Serializer.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/TX_SYNC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/LVDS_TX_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/TX_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/clock_gen.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/LVDS_TX_7_1/1.0.1/Obfuscated/LVDS_TX_7_1.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/RGB_LVDS_Encoder.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/YCbCr2RGB/1.0.1/Obfuscated/YCbCr2RGB.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/LCD_TOP/LCD_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreConfigP/7.0.105/rtl/vlog/core/coreconfigp.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp_pcie_hotreset.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreResetP/7.0.104/rtl/vlog/core/coreresetp.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb/CCC_0/MSS_TOP_sb_CCC_0_FCCC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_feedthrough.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_16Sto1M.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rd_channel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wresp_channel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_m.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_arbiter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_high.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_rdmatrix_4Mto1S_hgs_low.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_ra_channel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_arbiter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_high.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wrmatrix_4Mto1S_hgs_low.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wa_channel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_wd_channel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_matrix_s.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_interconnect_ntom.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_master_stage.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/COREAXI/3.1.100/rtl/vlog/core/axi_slave_stage.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb/COREAXI_0/rtl/vlog/core/coreaxi.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Actel/SgCore/OSC/2.0.101/osc_comps.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb/FABOSC_0/MSS_TOP_sb_FABOSC_0_OSC.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb_MSS/MSS_TOP_sb_MSS_syn.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb_MSS/MSS_TOP_sb_MSS.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAHBLite/5.2.100/rtl/vlog/core/coreahblite.v"
add_file -verilog -lib COREAPB3_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/release/parallel_cam_video_ref_design/component/Actel/DirectCore/CoreAPB3/4.1.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP_sb/MSS_TOP_sb.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/MSS_TOP/MSS_TOP.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/bus_cdc_synchornizer.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/ddr_read_controller.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/ram2Port.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/async_fifo_display.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/video_timing_generator.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/display_controller/1.0.1/Obfuscated/display_controller.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/downsampler.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/embsync_add.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/AXI_M.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/axi_arbiter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/rd_master_req_latch.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/AXI_displ_master_read.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/axi_buffer.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/ddr_displ_read_contrl .v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/unpack_64_24_displ.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/read_channel1_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/AXI_master_read.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/ddr_read_contrl.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_unpack_64_24.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_unpack_64_32_image.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_unpack_64_8.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/read_channel2_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/read_channel3_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/read_channel4_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/wr_master_req_latch.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/AXI_master_write_c2.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/ddr_write_contrl_ch2.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_packer_24_64.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_packer_32_64.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/data_packer_8_64.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/write_channel1_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/write_channel2_top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ddr_memory_arbiter/1.0.1/Obfuscated/ddr_memory_arbiter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/video_dma/video_dma.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/Bilinear_Interpolation.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/ramDualPort_bayer.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/CFA_RGB_Decoder.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/Median_Filter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/Median.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/FM_Median_Filter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/BayerConversionTop/1.0.1/Obfuscated/Bayer_Conversion_Top.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageEdgeDetection/1.0.1/Obfuscated/ramdualport_edge.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageEdgeDetection/1.0.1/Obfuscated/sobel.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageEdgeDetection/1.0.1/Obfuscated/Image_Edge_Detection.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageSharpenFilter/1.0.1/Obfuscated/ramdualport_sharpen.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageSharpenFilter/1.0.1/Obfuscated/sharpen.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/ImageSharpenFilter/1.0.1/Obfuscated/Image_Sharpen_Filter.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/alpha_blend_control/1.0.1/Obfuscated/Alpha_Blending.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/alpha_blend_control/1.0.1/Obfuscated/ramDualPort_alpha.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/alpha_blend_control/1.0.1/Obfuscated/Alpha_blend_control.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/alpha_object_read.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/Microsemi/SolutionCore/RGB2YCbCr/1.0.1/Obfuscated/RGB2YCbCr.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/Mux2x1.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/ramDualPort.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/hdl/Delay.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/video_isp_pipe/video_isp_pipe.v"
add_file -verilog "C:/release/parallel_cam_video_ref_design/component/work/AR0330_CAM_TOP/AR0330_CAM_TOP.v"
add_file -constraint "C:/release/parallel_cam_video_ref_design/constraint/user_timing_constraints.sdc"



#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std v2001

#device options
set_option -technology SmartFusion2
set_option -part M2S150T
set_option -package FC1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "AR0330_CAM_TOP"

# mapper_options
set_option -frequency 100.0000
set_option -write_verilog 0
set_option -write_vhdl 0
set_option -srs_instrumentation 1

# actel_options
set_option -rw_check_on_ram 0

# Microsemi G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 12
set_option -globalthreshold 1000
set_option -low_power_ram_decomp 0
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 0

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./AR0330_CAM_TOP.edn"
impl -active "synthesis"
