#Build: Synplify Pro (R) S-2021.09M-SP1, Build 150R, Jun 14 2022
#install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
#OS: Windows 10 or later
#Hostname: HYD-LT-I52882B

# Mon Nov 21 15:24:40 2022

#Implementation: synthesis


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 10 or later
Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys HDL Compiler, Version comp202109synp2, Build 152R, Built Jun 14 2022 11:35:28, @

@N: :  | Running in 64-bit mode 
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 10 or later
Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys VHDL Compiler, Version comp202109synp2, Build 152R, Built Jun 14 2022 11:35:28, @

@N: :  | Running in 64-bit mode 
@N: : intensity_average.vhd(23) | Top entity is set to intensity_average.
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\register_config.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\ram2port.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\data_packer_lpddr4.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\synchronizer_circuit.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\read_demux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\read_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\request_scheduler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\write_demux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\write_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\YCbCrtoRGB\4.4.0\Encrypted\YCbCrtoRGB.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\RGBtoYCbCr\4.4.0\Encrypted\RGBtoYCbCr.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\apb3_interface.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\intensity_average.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Display_Controller_C0\Display_Controller_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\HDMI_TX_C0\HDMI_TX_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\YCbCrtoRGB_C0\YCbCrtoRGB_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Bayer_Interpolation_C0\Bayer_Interpolation_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Gamma_Correction_C0\Gamma_Correction_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Image_Enhancement_C0\Image_Enhancement_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\RGBtoYCbCr_C0\RGBtoYCbCr_C0.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 104MB peak: 104MB)


Process completed successfully.
# Mon Nov 21 15:24:41 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 10 or later
Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys Verilog Compiler, Version comp202109synp2, Build 152R, Built Jun 14 2022 11:35:28, @

@N: :  | Running in 64-bit mode 
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\generic\acg5.v" (library work)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v" (library work)
@W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(118) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(168) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(213) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(232) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(281) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(335) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(657) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(761) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(795) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1059) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1369) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1396) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1441) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1474) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1492) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1518) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1559) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1581) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1599) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1616) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1635) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1652) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1681) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1712) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1802) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2026) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2187) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2203) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2219) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2235) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2267) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2648) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3661) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3732) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3861) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3879) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3896) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3911) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3926) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3953) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4065) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4096) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4142) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4252) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4436) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4477) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4503) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4520) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4597) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(5361) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6171) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6318) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(6391) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(7280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(8337) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(9296) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10032) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10747) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10781) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10817) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10864) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10898) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(11764) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12807) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12819) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12830) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected

@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C3\CORERESET_PF_C3_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C3\CORERESET_PF_C3.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C4\CORERESET_PF_C4_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C4\CORERESET_PF_C4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C0\PF_CCC_C0_0\PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C0\PF_CCC_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C1\PF_CCC_C1_0\PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C1\PF_CCC_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0_0\PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_OSC_C0\PF_OSC_C0_0\PF_OSC_C0_PF_OSC_C0_0_PF_OSC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_OSC_C0\PF_OSC_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_TX_PLL_C0\PF_TX_PLL_C0_0\PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_TX_PLL_C0\PF_TX_PLL_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_REF_CLK_C0\PF_XCVR_REF_CLK_C0_0\PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_REF_CLK_C0\PF_XCVR_REF_CLK_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CLOCKS_AND_RESETS\CLOCKS_AND_RESETS.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C0\CORERESET_PF_C0_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C0\CORERESET_PF_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR_Read_LPDDR4\DDR_Read_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR_Write_LPDDR4\DDR_Write_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C1\CORERESET_PF_C1_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C1\CORERESET_PF_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_CLK_DIV_FIFO\PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_CLK_DIV_RXCLK\PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_CLK_TRAINING\PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\PLL_BclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_GENERIC_RX_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CAM_IOD_TIP_TOP\CAM_IOD_TIP_TOP.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C2\CORERESET_PF_C2_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C2\CORERESET_PF_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C2\PF_CCC_C2_0\PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C2\PF_CCC_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\mipicsi2rxdecoderPF_C0\mipicsi2rxdecoderPF_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\IMX334_IF_TOP\IMX334_IF_TOP.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\PF_XCVR_ERM_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_NstagesSync.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_grayToBinConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_async.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_resetSync.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v" (library work)
@W:CG1337 : axi_lbus_corefifo_sync.v(288) | Net almostfulli_deassert is not declared.
@W:CG1337 : axi_lbus_corefifo_sync.v(293) | Net almostemptyi_deassert is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_LSRAM_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\read_top\read_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\write_top\write_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\Video_arbiter_top_LPDDR4\Video_arbiter_top_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\video_processing\video_processing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR4_RD_WR\DDR4_RD_WR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ResetSycnc.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\MasterAddressDecoder.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DependenceChecker.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\BitScan0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\TransactionController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\MasterControl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RoundRobinArb.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\TargetMuxController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\AddressController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Revision.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DERR_Slave.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DualPort_FF_SyncWr_SyncRd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DualPort_Ram_SyncWr_SyncRd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RdFifoDualPort.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ReadDataMux.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RequestQual.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ReadDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\SlaveDataMuxController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RespController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\FifoDualPort.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\WriteDataMux.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\WDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHBL_Ctrl.v" (library work)
@W:CG1337 : AHBL_Ctrl.v(297) | Net axi_read_not_ready is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AXI4_Read_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AXI4_Write_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHB_SM.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrAHBtoAXI4Converter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\Bin2Gray.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_grayCodeCounter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_rdCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_wrCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RAM_BLOCK.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_FIFO.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrClockDomainCrossing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v" (library work)
@W:CG1337 : DWC_UpConv_AChannel.v(457) | Net addr_beat is not declared.
@W:CG1337 : DWC_UpConv_AChannel.v(461) | Net mask is not declared.
@W:CG1337 : DWC_UpConv_AChannel.v(498) | Net FIXED is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_brespCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_CTRL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_BChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChannel_SlvRid_Arb.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChan_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\Hold_Reg_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_preCalcRChan_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_downsizing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChan_Hold_Reg.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChan_ReadDataFifoCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_Wchan_WriteDataFifoCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_upsizing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_preCalcAChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\UpConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_Hold_Reg_Rd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvrd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\byte2bit.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_readWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_Hold_Reg_Wr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DownConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrDataWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrProtocolConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RegSliceFull.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RegisterSlice.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MasterConvertor.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvClockDomainCrossing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvDataWidthConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvRead.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvWrite.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtocolConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvAXI4ID.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvProtocolConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlaveConvertor.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\FIC_BRIDGE\FIC_BRIDGE.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v" (library work)
@W:CG100 : MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v(798) | User defined pragma syn_black_box detected

@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_SEV.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\SEV_PFSoC_OpenVX\SEV_PFSoC_OpenVX.v" (library work)
Verilog syntax check successful!

At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 139MB)


Process completed successfully.
# Mon Nov 21 15:24:42 2022

###########################################################]
###########################################################[
@N:CG1349 :  | Running Verilog Compiler in System Verilog mode 

@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\generic\acg5.v" (library work)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"D:\Microchip\Libero_SoC_v2022.2\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v" (library work)
@W:CG100 : polarfire_syn_comps.v(21) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(61) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(88) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(118) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(168) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(213) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(232) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(281) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(335) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(657) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(761) | User defined pragma syn_black_box detected

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@W:CG100 : polarfire_syn_comps.v(1581) | User defined pragma syn_black_box detected

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@W:CG100 : polarfire_syn_comps.v(1616) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1635) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1652) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1681) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1712) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(1802) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2026) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2187) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2203) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2219) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2235) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2267) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(2648) | User defined pragma syn_black_box detected

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@W:CG100 : polarfire_syn_comps.v(3732) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3861) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3879) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3896) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3911) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3926) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(3953) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4065) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4096) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4142) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(4252) | User defined pragma syn_black_box detected

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@W:CG100 : polarfire_syn_comps.v(6280) | User defined pragma syn_black_box detected

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@W:CG100 : polarfire_syn_comps.v(6391) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(7280) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(8337) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(9296) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10032) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10747) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10781) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10817) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10864) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(10898) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(11764) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12807) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12819) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12830) | User defined pragma syn_black_box detected

@W:CG100 : polarfire_syn_comps.v(12843) | User defined pragma syn_black_box detected

@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C3\CORERESET_PF_C3_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C3\CORERESET_PF_C3.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C4\CORERESET_PF_C4_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C4\CORERESET_PF_C4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C0\PF_CCC_C0_0\PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C0\PF_CCC_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C1\PF_CCC_C1_0\PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C1\PF_CCC_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0_0\PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CLK_DIV_C0\PF_CLK_DIV_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_OSC_C0\PF_OSC_C0_0\PF_OSC_C0_PF_OSC_C0_0_PF_OSC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_OSC_C0\PF_OSC_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_TX_PLL_C0\PF_TX_PLL_C0_0\PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_TX_PLL_C0\PF_TX_PLL_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_REF_CLK_C0\PF_XCVR_REF_CLK_C0_0\PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_REF_CLK_C0\PF_XCVR_REF_CLK_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CLOCKS_AND_RESETS\CLOCKS_AND_RESETS.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C0\CORERESET_PF_C0_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C0\CORERESET_PF_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR_Read_LPDDR4\DDR_Read_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR_Write_LPDDR4\DDR_Write_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C1\CORERESET_PF_C1_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C1\CORERESET_PF_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v" (library CORERXIODBITALIGN_LIB)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign_top.v" (library CORERXIODBITALIGN_LIB)
@N:CG334 : CoreRxIODBitAlign_top.v(115) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(118) | Read directive translate_on.
@N:CG334 : CoreRxIODBitAlign_top.v(130) | Read directive translate_off.
@N:CG333 : CoreRxIODBitAlign_top.v(151) | Read directive translate_on.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_CLK_DIV_FIFO\PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_CLK_DIV_RXCLK\PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_CLK_TRAINING\PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\PLL_BclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_GENERIC_RX_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CAM_IOD_TIP_TOP\CAM_IOD_TIP_TOP.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C2\CORERESET_PF_C2_0\core\corereset_pf.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERESET_PF_C2\CORERESET_PF_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C2\PF_CCC_C2_0\PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C2\PF_CCC_C2.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\mipicsi2rxdecoderPF_C0\mipicsi2rxdecoderPF_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\IMX334_IF_TOP\IMX334_IF_TOP.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\PF_XCVR_ERM_C0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_NstagesSync.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_grayToBinConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_async.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_resetSync.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v" (library work)
@W:CG1337 : axi_lbus_corefifo_sync.v(288) | Net almostfulli_deassert is not declared.
@W:CG1337 : axi_lbus_corefifo_sync.v(293) | Net almostemptyi_deassert is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_LSRAM_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\read_top\read_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\write_top\write_top.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\Video_arbiter_top_LPDDR4\Video_arbiter_top_LPDDR4.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\video_processing\video_processing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DDR4_RD_WR\DDR4_RD_WR.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ResetSycnc.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\MasterAddressDecoder.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DependenceChecker.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\BitScan0.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\TransactionController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\MasterControl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RoundRobinArb.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\TargetMuxController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\AddressController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Revision.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DERR_Slave.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DualPort_FF_SyncWr_SyncRd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\DualPort_Ram_SyncWr_SyncRd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RdFifoDualPort.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ReadDataMux.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RequestQual.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\ReadDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\SlaveDataMuxController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\RespController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\FifoDualPort.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\WriteDataMux.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\WDataController.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHBL_Ctrl.v" (library work)
@W:CG1337 : AHBL_Ctrl.v(297) | Net axi_read_not_ready is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AXI4_Read_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AXI4_Write_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHB_SM.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrAHBtoAXI4Converter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\Bin2Gray.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_grayCodeCounter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_rdCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_wrCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RAM_BLOCK.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\CDC_FIFO.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrClockDomainCrossing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v" (library work)
@W:CG1337 : DWC_UpConv_AChannel.v(457) | Net addr_beat is not declared.
@W:CG1337 : DWC_UpConv_AChannel.v(461) | Net mask is not declared.
@W:CG1337 : DWC_UpConv_AChannel.v(498) | Net FIXED is not declared.
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_brespCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_CTRL.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_BChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChannel_SlvRid_Arb.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChan_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\Hold_Reg_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_preCalcRChan_Ctrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_downsizing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_RChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChan_Hold_Reg.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChan_ReadDataFifoCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_Wchan_WriteDataFifoCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\FIFO_upsizing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_WChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_preCalcAChannel.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\UpConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_Hold_Reg_Rd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvrd.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\byte2bit.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_readWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_Hold_Reg_Wr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DownConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrDataWidthConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MstrProtocolConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RegSliceFull.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\RegisterSlice.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\MasterConvertor.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvClockDomainCrossing.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvDataWidthConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvRead.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvWrite.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtocolConv.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvAxi4ProtConvAXI4ID.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlvProtocolConverter.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\SlaveConvertor.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\FIC_BRIDGE\FIC_BRIDGE.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v" (library work)
@W:CG100 : MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v(798) | User defined pragma syn_black_box detected

@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_SEV.v" (library work)
@I::"D:\Delme\SEV_PFSoC_OpenVX\component\work\SEV_PFSoC_OpenVX\SEV_PFSoC_OpenVX.v" (library work)
Verilog syntax check successful!
@N:CG364 : acg5.v(121) | Synthesizing module AND2 in library work.
Running optimization stage 1 on AND2 .......
Finished optimization stage 1 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 141MB)
@N:CG364 : acg5.v(333) | Synthesizing module BIBUF in library work.
Running optimization stage 1 on BIBUF .......
Finished optimization stage 1 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 142MB)
@N:CG364 : acg5.v(151) | Synthesizing module AND3 in library work.
Running optimization stage 1 on AND3 .......
Finished optimization stage 1 on AND3 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 142MB)
@N:CG364 : corereset_pf.v(21) | Synthesizing module CORERESET_PF_C3_CORERESET_PF_C3_0_CORERESET_PF in library work.
Running optimization stage 1 on CORERESET_PF_C3_CORERESET_PF_C3_0_CORERESET_PF .......
Finished optimization stage 1 on CORERESET_PF_C3_CORERESET_PF_C3_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : CORERESET_PF_C3.v(21) | Synthesizing module CORERESET_PF_C3 in library work.
Running optimization stage 1 on CORERESET_PF_C3 .......
Finished optimization stage 1 on CORERESET_PF_C3 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : corereset_pf.v(21) | Synthesizing module CORERESET_PF_C4_CORERESET_PF_C4_0_CORERESET_PF in library work.
Running optimization stage 1 on CORERESET_PF_C4_CORERESET_PF_C4_0_CORERESET_PF .......
Finished optimization stage 1 on CORERESET_PF_C4_CORERESET_PF_C4_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : CORERESET_PF_C4.v(21) | Synthesizing module CORERESET_PF_C4 in library work.
Running optimization stage 1 on CORERESET_PF_C4 .......
Finished optimization stage 1 on CORERESET_PF_C4 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(44) | Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(44) | Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(44) | Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(44) | Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(44) | Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : polarfire_syn_comps.v(1702) | Synthesizing module INIT in library work.
Running optimization stage 1 on INIT .......
Finished optimization stage 1 on INIT (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(55) | Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_GPIO_7 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : polarfire_syn_comps.v(107) | Synthesizing module BANKCTRL_GPIO in library work.
Running optimization stage 1 on BANKCTRL_GPIO .......
Finished optimization stage 1 on BANKCTRL_GPIO (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : acg5.v(504) | Synthesizing module VCC in library work.
Running optimization stage 1 on VCC .......
Finished optimization stage 1 on VCC (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(63) | Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_HSIO_8 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : polarfire_syn_comps.v(156) | Synthesizing module BANKCTRL_HSIO in library work.
Running optimization stage 1 on BANKCTRL_HSIO .......
Finished optimization stage 1 on BANKCTRL_HSIO (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : acg5.v(500) | Synthesizing module GND in library work.
Running optimization stage 1 on GND .......
Finished optimization stage 1 on GND (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(71) | Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_GPIO_9 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v(5) | Synthesizing module INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR in library work.
Running optimization stage 1 on INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR .......
Finished optimization stage 1 on INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : INIT_MONITOR.v(67) | Synthesizing module INIT_MONITOR in library work.
Running optimization stage 1 on INIT_MONITOR .......
Finished optimization stage 1 on INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
Finished optimization stage 1 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v(37) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : polarfire_syn_comps.v(3694) | Synthesizing module PLL in library work.
Running optimization stage 1 on PLL .......
Finished optimization stage 1 on PLL (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v(5) | Synthesizing module PF_CCC_C0_PF_CCC_C0_0_PF_CCC in library work.
Running optimization stage 1 on PF_CCC_C0_PF_CCC_C0_0_PF_CCC .......
Finished optimization stage 1 on PF_CCC_C0_PF_CCC_C0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_CCC_C0.v(264) | Synthesizing module PF_CCC_C0 in library work.
Running optimization stage 1 on PF_CCC_C0 .......
Finished optimization stage 1 on PF_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@W:CG168 : PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v(37) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v(5) | Synthesizing module PF_CCC_C1_PF_CCC_C1_0_PF_CCC in library work.
Running optimization stage 1 on PF_CCC_C1_PF_CCC_C1_0_PF_CCC .......
Finished optimization stage 1 on PF_CCC_C1_PF_CCC_C1_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_CCC_C1.v(264) | Synthesizing module PF_CCC_C1 in library work.
Running optimization stage 1 on PF_CCC_C1 .......
Finished optimization stage 1 on PF_CCC_C1 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : polarfire_syn_comps.v(1553) | Synthesizing module ICB_CLKDIV in library work.
Running optimization stage 1 on ICB_CLKDIV .......
Finished optimization stage 1 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v(5) | Synthesizing module PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV in library work.
Running optimization stage 1 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV .......
Finished optimization stage 1 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_CLK_DIV_C0.v(24) | Synthesizing module PF_CLK_DIV_C0 in library work.
Running optimization stage 1 on PF_CLK_DIV_C0 .......
Finished optimization stage 1 on PF_CLK_DIV_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : polarfire_syn_comps.v(2231) | Synthesizing module OSC_RC2MHZ in library work.
Running optimization stage 1 on OSC_RC2MHZ .......
Finished optimization stage 1 on OSC_RC2MHZ (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_OSC_C0_PF_OSC_C0_0_PF_OSC.v(5) | Synthesizing module PF_OSC_C0_PF_OSC_C0_0_PF_OSC in library work.
Running optimization stage 1 on PF_OSC_C0_PF_OSC_C0_0_PF_OSC .......
Finished optimization stage 1 on PF_OSC_C0_PF_OSC_C0_0_PF_OSC (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_OSC_C0.v(27) | Synthesizing module PF_OSC_C0 in library work.
Running optimization stage 1 on PF_OSC_C0 .......
Finished optimization stage 1 on PF_OSC_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : polarfire_syn_comps.v(4119) | Synthesizing module TX_PLL in library work.
Running optimization stage 1 on TX_PLL .......
Finished optimization stage 1 on TX_PLL (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL.v(5) | Synthesizing module PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL in library work.
Running optimization stage 1 on PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL .......
Finished optimization stage 1 on PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_TX_PLL_C0.v(50) | Synthesizing module PF_TX_PLL_C0 in library work.
Running optimization stage 1 on PF_TX_PLL_C0 .......
Finished optimization stage 1 on PF_TX_PLL_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : polarfire_syn_comps.v(10810) | Synthesizing module XCVR_REF_CLK in library work.
Running optimization stage 1 on XCVR_REF_CLK .......
Finished optimization stage 1 on XCVR_REF_CLK (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK.v(5) | Synthesizing module PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK in library work.
Running optimization stage 1 on PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK .......
Finished optimization stage 1 on PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : PF_XCVR_REF_CLK_C0.v(27) | Synthesizing module PF_XCVR_REF_CLK_C0 in library work.
Running optimization stage 1 on PF_XCVR_REF_CLK_C0 .......
Finished optimization stage 1 on PF_XCVR_REF_CLK_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 142MB)
@N:CG364 : CLOCKS_AND_RESETS.v(9) | Synthesizing module CLOCKS_AND_RESETS in library work.
Running optimization stage 1 on CLOCKS_AND_RESETS .......
Finished optimization stage 1 on CLOCKS_AND_RESETS (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 143MB)
@N:CG364 : corereset_pf.v(21) | Synthesizing module CORERESET_PF_C0_CORERESET_PF_C0_0_CORERESET_PF in library work.
Running optimization stage 1 on CORERESET_PF_C0_CORERESET_PF_C0_0_CORERESET_PF .......
Finished optimization stage 1 on CORERESET_PF_C0_CORERESET_PF_C0_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 143MB)
@N:CG364 : CORERESET_PF_C0.v(21) | Synthesizing module CORERESET_PF_C0 in library work.
Running optimization stage 1 on CORERESET_PF_C0 .......
Finished optimization stage 1 on CORERESET_PF_C0 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 143MB)
@N:CG364 : DDR_Read_LPDDR4.v(9) | Synthesizing module DDR_Read_LPDDR4 in library work.
@N:CG794 : DDR_Read_LPDDR4.v(136) | Using module data_unpacker_FHD_RX from library work
@N:CG794 : DDR_Read_LPDDR4.v(152) | Using module DDR_read_controller_FHD_HDMI_RX from library work
@N:CG794 : DDR_Read_LPDDR4.v(172) | Using module Register_Config from library work
@N:CG794 : DDR_Read_LPDDR4.v(186) | Using module video_fifo from library work
Running optimization stage 1 on DDR_Read_LPDDR4 .......
Finished optimization stage 1 on DDR_Read_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 143MB)
@N:CG364 : DDR_Write_LPDDR4.v(9) | Synthesizing module DDR_Write_LPDDR4 in library work.
@N:CG794 : DDR_Write_LPDDR4.v(120) | Using module data_packer_lpddr4 from library work
@N:CG794 : DDR_Write_LPDDR4.v(136) | Using module DDR_write_controller_lpddr4 from library work
@N:CG794 : DDR_Write_LPDDR4.v(158) | Using module synchronizer_circuit from library work
@N:CG794 : DDR_Write_LPDDR4.v(184) | Using module video_fifo from library work
Running optimization stage 1 on DDR_Write_LPDDR4 .......
Finished optimization stage 1 on DDR_Write_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 142MB peak: 143MB)
@N:CG364 : corereset_pf.v(21) | Synthesizing module CORERESET_PF_C1_CORERESET_PF_C1_0_CORERESET_PF in library work.
Running optimization stage 1 on CORERESET_PF_C1_CORERESET_PF_C1_0_CORERESET_PF .......
Finished optimization stage 1 on CORERESET_PF_C1_CORERESET_PF_C1_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
@N:CG364 : CORERESET_PF_C1.v(21) | Synthesizing module CORERESET_PF_C1 in library work.
Running optimization stage 1 on CORERESET_PF_C1 .......
Finished optimization stage 1 on CORERESET_PF_C1 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
@N:CG364 : corereset_pf.v(21) | Synthesizing module CORERESET_PF_C2_CORERESET_PF_C2_0_CORERESET_PF in library work.
Running optimization stage 1 on CORERESET_PF_C2_CORERESET_PF_C2_0_CORERESET_PF .......
Finished optimization stage 1 on CORERESET_PF_C2_CORERESET_PF_C2_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
@N:CG364 : CORERESET_PF_C2.v(21) | Synthesizing module CORERESET_PF_C2 in library work.
Running optimization stage 1 on CORERESET_PF_C2 .......
Finished optimization stage 1 on CORERESET_PF_C2 (CPU Time 0h:00m:00s, Memory Used current: 143MB peak: 143MB)
@N:CG364 : mipicsi2rxdecoderPF.v(1) | Synthesizing module mipicsi2rxdecoderPF in library work.

	g_DATAWIDTH=32'b00000000000000000000000000001010
	g_LANE_WIDTH=32'b00000000000000000000000000000100
	g_NUM_OF_PIXELS=32'b00000000000000000000000000000001
	g_INPUT_DATA_INVERT=32'b00000000000000000000000000000000
	g_FIFO_SIZE=32'b00000000000000000000000000001100
	g_FORMAT=32'b00000000000000000000000000000000
   Generated name = mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s
@N:CG364 : mipicsi2rxdecoderPF.v(1677) | Synthesizing module embsync_detect in library work.

	g_LANE_WIDTH=32'b00000000000000000000000000000100
	ST_IDLE=3'b000
	ST_WAIT=3'b001
	ST_WCNT0=3'b010
	ST_WCNT1=3'b011
	ST_ACTIVE=3'b100
	ST_IDLE0=2'b00
	ST_WAIT0=2'b01
	ST_RUN0=2'b10
	ST_IDLE1=2'b00
	ST_WAIT1=2'b01
	ST_RUN1=2'b10
	ST_IDLE2=2'b00
	ST_WAIT2=2'b01
	ST_RUN2=2'b10
	ST_IDLE3=2'b00
	ST_WAIT3=2'b01
	ST_RUN3=2'b10
	ST_IDLE4=2'b00
	ST_WAIT4=2'b01
	ST_RUN4=2'b10
	ST_IDLE5=2'b00
	ST_WAIT5=2'b01
	ST_RUN5=2'b10
	ST_IDLE6=2'b00
	ST_WAIT6=2'b01
	ST_RUN6=2'b10
	ST_IDLE7=2'b00
	ST_WAIT7=2'b01
	ST_RUN7=2'b10
   Generated name = embsync_detect_Z1_layer0
@N:CG179 : mipicsi2rxdecoderPF.v(2220) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2221) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2222) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2228) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2229) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2230) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2238) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2239) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2251) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2257) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2259) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2419) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2480) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2541) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2602) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2663) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2724) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2785) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2846) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2930) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2931) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2936) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(2937) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3091) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3092) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3097) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3098) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3254) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3255) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3260) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3261) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3420) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3421) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3426) | Removing redundant assignment.
@N:CG179 : mipicsi2rxdecoderPF.v(3427) | Removing redundant assignment.
@N:CG364 : mipicsi2rxdecoderPF.v(6616) | Synthesizing module mipi_csi2_rx_cdcfiforam in library work.

	ADDR_WIDTH=4'b1000
	DATA_WIDTH=8'b00001000
   Generated name = mipi_csi2_rx_cdcfiforam_8_8
Running optimization stage 1 on mipi_csi2_rx_cdcfiforam_8_8 .......
@N:CL134 : mipicsi2rxdecoderPF.v(6641) | Found RAM ram_block, depth=256, width=8
Finished optimization stage 1 on mipi_csi2_rx_cdcfiforam_8_8 (CPU Time 0h:00m:00s, Memory Used current: 145MB peak: 145MB)
@N:CG364 : mipicsi2rxdecoderPF.v(6352) | Synthesizing module mipi_csi2_rx_cdcfifo in library work.

	ADDR_WIDTH=4'b1000
	DATA_WIDTH=8'b00001000
	GRAY_P1=32'b00000000000000000000000000000001
	GRAY_P2=32'b00000000000000000000000000000011
   Generated name = mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3
Running optimization stage 1 on mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3 .......
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register overflow. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register overflow1. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register rdaddr_r_bin[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register wraddr_sync_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register wraddr_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register rdaddr_sync_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3 (CPU Time 0h:00m:00s, Memory Used current: 146MB peak: 147MB)
@W:CG360 : mipicsi2rxdecoderPF.v(1706) | Removing wire L4_DATA_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1707) | Removing wire L5_DATA_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1708) | Removing wire L6_DATA_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1709) | Removing wire L7_DATA_O, as there is no assignment to it.
@W:CG133 : mipicsi2rxdecoderPF.v(1786) | Object L4_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1787) | Object L5_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1788) | Object L6_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1789) | Object L7_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1794) | Object L4_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1795) | Object L5_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1796) | Object L6_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1797) | Object L7_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1802) | Object L4_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1803) | Object L5_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1804) | Object L6_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1805) | Object L7_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1810) | Object L4_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1811) | Object L5_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1812) | Object L6_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1813) | Object L7_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1818) | Object L4_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1819) | Object L5_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1820) | Object L6_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1821) | Object L7_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1826) | Object L4_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1827) | Object L5_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1828) | Object L6_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1829) | Object L7_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1834) | Object L4_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1835) | Object L5_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1836) | Object L6_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1837) | Object L7_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1842) | Object L4_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1843) | Object L5_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1844) | Object L6_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1845) | Object L7_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1850) | Object L4_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1851) | Object L5_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1852) | Object L6_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1853) | Object L7_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : mipicsi2rxdecoderPF.v(1858) | Removing wire L4_data_out_r, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1859) | Removing wire L5_data_out_r, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1860) | Removing wire L6_data_out_r, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(1861) | Removing wire L7_data_out_r, as there is no assignment to it.
@W:CG133 : mipicsi2rxdecoderPF.v(1866) | Object L4_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1867) | Object L5_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1868) | Object L6_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1869) | Object L7_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1874) | Object q_in4_7 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1875) | Object q_in5_7 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1876) | Object q_in6_7 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1877) | Object q_in7_7 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1879) | Object sync4 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1879) | Object sync5 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1879) | Object sync6 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1879) | Object sync7 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1881) | Object sync4_reg is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1881) | Object sync5_reg is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1881) | Object sync6_reg is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(1881) | Object sync7_reg is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on embsync_detect_Z1_layer0 .......
@W:CL318 : mipicsi2rxdecoderPF.v(1706) | *Output L4_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(1707) | *Output L5_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(1708) | *Output L6_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(1709) | *Output L7_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL169 : mipicsi2rxdecoderPF.v(4231) | Pruning unused register genblk12.q_in3_4[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4231) | Pruning unused register genblk12.q_in3_5[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4231) | Pruning unused register genblk12.q_in3_6[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4231) | Pruning unused register genblk12.q_in3_7[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4201) | Pruning unused register genblk11.q_in2_4[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4201) | Pruning unused register genblk11.q_in2_5[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4201) | Pruning unused register genblk11.q_in2_6[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4201) | Pruning unused register genblk11.q_in2_7[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4171) | Pruning unused register genblk10.q_in1_4[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4171) | Pruning unused register genblk10.q_in1_5[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4171) | Pruning unused register genblk10.q_in1_6[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4171) | Pruning unused register genblk10.q_in1_7[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4141) | Pruning unused register genblk9.q_in0_4[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4141) | Pruning unused register genblk9.q_in0_5[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4141) | Pruning unused register genblk9.q_in0_6[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4141) | Pruning unused register genblk9.q_in0_7[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2801) | Pruning unused register genblk1.state_7[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2801) | Pruning unused register genblk1.sync_start7. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2740) | Pruning unused register genblk1.state_6[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2740) | Pruning unused register genblk1.sync_start6. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2679) | Pruning unused register genblk1.state_5[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2679) | Pruning unused register genblk1.sync_start5. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2618) | Pruning unused register genblk1.state_4[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(2618) | Pruning unused register genblk1.sync_start4. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1914) | Pruning unused register L4_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1914) | Pruning unused register L5_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1914) | Pruning unused register L6_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1914) | Pruning unused register L7_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W:CL271 : mipicsi2rxdecoderPF.v(4445) | Pruning unused bits 10 to 5 of q_sync_detect_all_lanes[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : mipicsi2rxdecoderPF.v(1914) | Pruning unused bits 15 to 8 of L0_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : mipicsi2rxdecoderPF.v(1914) | Pruning unused bits 15 to 8 of L1_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : mipicsi2rxdecoderPF.v(1914) | Pruning unused bits 15 to 8 of L2_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : mipicsi2rxdecoderPF.v(1914) | Pruning unused bits 15 to 8 of L3_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 1 on embsync_detect_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 148MB peak: 148MB)
@N:CG364 : mipicsi2rxdecoderPF.v(6616) | Synthesizing module mipi_csi2_rx_cdcfiforam in library work.

	ADDR_WIDTH=4'b1100
	DATA_WIDTH=8'b00101000
   Generated name = mipi_csi2_rx_cdcfiforam_12_40
Running optimization stage 1 on mipi_csi2_rx_cdcfiforam_12_40 .......
@N:CL134 : mipicsi2rxdecoderPF.v(6641) | Found RAM ram_block, depth=4096, width=40
Finished optimization stage 1 on mipi_csi2_rx_cdcfiforam_12_40 (CPU Time 0h:00m:00s, Memory Used current: 153MB peak: 153MB)
@N:CG364 : mipicsi2rxdecoderPF.v(6352) | Synthesizing module mipi_csi2_rx_cdcfifo in library work.

	ADDR_WIDTH=4'b1100
	DATA_WIDTH=8'b00101000
	GRAY_P1=32'b00000000000000000000000000000001
	GRAY_P2=32'b00000000000000000000000000000011
   Generated name = mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3
Running optimization stage 1 on mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3 .......
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register overflow. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register overflow1. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register rdaddr_r_bin[11:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6543) | Pruning unused register wraddr_sync_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register wraddr_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6450) | Pruning unused register rdaddr_sync_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3 (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 154MB)
@N:CG364 : mipicsi2rxdecoderPF.v(4672) | Synthesizing module byte2pixel_conversion in library work.

	g_DATAWIDTH=32'b00000000000000000000000000001010
	g_LANE_WIDTH=32'b00000000000000000000000000000100
	g_NUM_OF_PIXELS=32'b00000000000000000000000000000001
	g_FIFO_SIZE=32'b00000000000000000000000000001100
	S0=3'b000
	S1=3'b001
	S2=3'b010
	S3=3'b011
	S4=3'b100
	S5=3'b101
	S6=3'b110
	S7=3'b111
	state1=3'b001
	state2=3'b010
	state3=3'b011
	state4=3'b100
	state5=3'b101
	state6=3'b110
	state7=3'b111
	FIFO_DATA_WIDTH=32'b00000000000000000000000000101000
   Generated name = byte2pixel_conversion_Z2_layer0
@N:CG179 : mipicsi2rxdecoderPF.v(5900) | Removing redundant assignment.
@W:CG133 : mipicsi2rxdecoderPF.v(4729) | Object reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(4730) | Object reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(4737) | Object rd_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(4742) | Object pix_distribute_2lane is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(4743) | Object pix_cnt_2lane is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : mipicsi2rxdecoderPF.v(4746) | Object pix_distribute_8lane is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on byte2pixel_conversion_Z2_layer0 .......
@W:CL169 : mipicsi2rxdecoderPF.v(6066) | Pruning unused register byte_data_arranged_2[39:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6066) | Pruning unused register byte_data_arranged_3[39:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6066) | Pruning unused register byte_data_arranged_4[39:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(6066) | Pruning unused register byte_data_arranged_5[39:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4825) | Pruning unused register genblk2.reg1[31:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4752) | Pruning unused register byte_en1. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4752) | Pruning unused register byte_en2. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(4752) | Pruning unused register b2p_fv_reg. Make sure that there are no unused intermediate registers.
@W:CL271 : mipicsi2rxdecoderPF.v(6033) | Pruning unused bits 8 to 3 of read_en_reg[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@A:CL282 : mipicsi2rxdecoderPF.v(4825) | Feedback mux created for signal genblk2.reg0[31:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
Finished optimization stage 1 on byte2pixel_conversion_Z2_layer0 (CPU Time 0h:00m:00s, Memory Used current: 154MB peak: 155MB)
@N:CG364 : mipicsi2rxdecoderPF.v(380) | Synthesizing module mipi_csi2_rxdecoder in library work.

	g_DATAWIDTH=32'b00000000000000000000000000001010
	g_INPUT_DATA_INVERT=32'b00000000000000000000000000000000
	g_LANE_WIDTH=32'b00000000000000000000000000000100
	g_NUM_OF_PIXELS=32'b00000000000000000000000000000001
	g_FIFO_SIZE=32'b00000000000000000000000000001100
	SHIFT_REG_WIDTH=32'b00000000000000000000000000010000
	g_FSH=16'b1011100000000000
	g_FEH=16'b1011100000000001
	g_LSH=16'b1011100000101011
	IDLE_FS=32'b00000000000000000000000000000000
	FS1=32'b00000000000000000000000000000001
	FS2=32'b00000000000000000000000000000010
	FS3=32'b00000000000000000000000000000011
	SYNC_LANE0=32'b00000000000000000000000000000100
	WC_0=32'b00000000000000000000000000000101
	WC_1=32'b00000000000000000000000000000110
	LENGTH=32'b00000000000000000000000000000111
	PAYLOAD=32'b00000000000000000000000000001000
	LINE_END=32'b00000000000000000000000000001001
	LE1=32'b00000000000000000000000000001010
	LE2=32'b00000000000000000000000000001011
	FRAME_END=32'b00000000000000000000000000001100
	FE1=32'b00000000000000000000000000001101
	FE2=32'b00000000000000000000000000001110
	FE3=32'b00000000000000000000000000001111
	L1_SYNC_FRAME=32'b00000000000000000000000000000000
	L1_FS=32'b00000000000000000000000000000001
	L1_FS1=32'b00000000000000000000000000000010
	L1_SYNC_LINE=32'b00000000000000000000000000000011
	L1_WC_0=32'b00000000000000000000000000000100
	L1_WC_1=32'b00000000000000000000000000000101
	L1_PAYLOAD=32'b00000000000000000000000000000110
	L1_LE_CRC=32'b00000000000000000000000000000111
	L4_SYNC_FRAME=32'b00000000000000000000000000000000
	L4_FS=32'b00000000000000000000000000000001
	L4_SYNC_LINE=32'b00000000000000000000000000000010
	L4_WC=32'b00000000000000000000000000000011
	L4_PAYLOAD=32'b00000000000000000000000000000100
	L4_LE_CRC=32'b00000000000000000000000000000101
	L8_SYNC_FRAME=32'b00000000000000000000000000000000
	L8_FS=32'b00000000000000000000000000000001
	L8_SYNC_LINE=32'b00000000000000000000000000000010
	L8_WC=32'b00000000000000000000000000000011
	L8_PAYLOAD=32'b00000000000000000000000000000100
	L8_LE_CRC=32'b00000000000000000000000000000101
   Generated name = mipi_csi2_rxdecoder_Z3_layer0
@N:CG179 : mipicsi2rxdecoderPF.v(1541) | Removing redundant assignment.
@W:CG133 : mipicsi2rxdecoderPF.v(465) | Object serial_data_reg is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on mipi_csi2_rxdecoder_Z3_layer0 .......
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.frame_start_out. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.frame_end_out. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.line_start_out. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.fn_1[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.fn_0[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.fn_end_1[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.fn_end_0[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.wc1[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.wc2[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(1125) | Pruning unused register genblk2.line_end_out. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(720) | Pruning unused register shift_reg[15:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(651) | Pruning unused register data_in_reverse_L7[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(634) | Pruning unused register data_in_reverse_L6[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(617) | Pruning unused register data_in_reverse_L5[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : mipicsi2rxdecoderPF.v(600) | Pruning unused register data_in_reverse_L4[7:0]. Make sure that there are no unused intermediate registers.
@W:CL208 : mipicsi2rxdecoderPF.v(1514) | All reachable assignments to bit 6 of data_type_o[7:0] assign 0, register removed by optimization.
@W:CL208 : mipicsi2rxdecoderPF.v(1514) | All reachable assignments to bit 7 of data_type_o[7:0] assign 0, register removed by optimization.
Finished optimization stage 1 on mipi_csi2_rxdecoder_Z3_layer0 (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CG364 : mipicsi2rxdecoderPF.v(208) | Synthesizing module mipicsi2rxdecoderPF_native in library work.

	g_DATAWIDTH=32'b00000000000000000000000000001010
	g_LANE_WIDTH=32'b00000000000000000000000000000100
	g_NUM_OF_PIXELS=32'b00000000000000000000000000000001
	g_INPUT_DATA_INVERT=32'b00000000000000000000000000000000
	g_FIFO_SIZE=32'b00000000000000000000000000001100
   Generated name = mipicsi2rxdecoderPF_native_10s_4s_1s_0s_12s
Running optimization stage 1 on mipicsi2rxdecoderPF_native_10s_4s_1s_0s_12s .......
Finished optimization stage 1 on mipicsi2rxdecoderPF_native_10s_4s_1s_0s_12s (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L0_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L1_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L2_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L3_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L4_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L5_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L6_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : mipicsi2rxdecoderPF.v(76) | Input L7_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG360 : mipicsi2rxdecoderPF.v(51) | Removing wire TDATA_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(52) | Removing wire TSTRB_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(53) | Removing wire TKEEP_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(54) | Removing wire TVALID_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(55) | Removing wire TLAST_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(56) | Removing wire TUSER_O, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(62) | Removing wire axi_data, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(63) | Removing wire sof_axi, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(64) | Removing wire frame_valid_axi, as there is no assignment to it.
@W:CG360 : mipicsi2rxdecoderPF.v(65) | Removing wire line_valid_axi, as there is no assignment to it.
Running optimization stage 1 on mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s .......
@W:CL318 : mipicsi2rxdecoderPF.v(51) | *Output TDATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(52) | *Output TSTRB_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(53) | *Output TKEEP_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(54) | *Output TVALID_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(55) | *Output TLAST_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : mipicsi2rxdecoderPF.v(56) | *Output TUSER_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CG364 : mipicsi2rxdecoderPF_C0.v(27) | Synthesizing module mipicsi2rxdecoderPF_C0 in library work.
Running optimization stage 1 on mipicsi2rxdecoderPF_C0 .......
Finished optimization stage 1 on mipicsi2rxdecoderPF_C0 (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@W:CG168 : PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v(37) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v(5) | Synthesizing module PF_CCC_C2_PF_CCC_C2_0_PF_CCC in library work.
Running optimization stage 1 on PF_CCC_C2_PF_CCC_C2_0_PF_CCC .......
Finished optimization stage 1 on PF_CCC_C2_PF_CCC_C2_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CG364 : PF_CCC_C2.v(264) | Synthesizing module PF_CCC_C2 in library work.
Running optimization stage 1 on PF_CCC_C2 .......
Finished optimization stage 1 on PF_CCC_C2 (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CG364 : acg5.v(187) | Synthesizing module AND4 in library work.
Running optimization stage 1 on AND4 .......
Finished optimization stage 1 on AND4 (CPU Time 0h:00m:00s, Memory Used current: 155MB peak: 155MB)
@N:CG775 : CoreRxIODBitAlign_top.v(2) | Component CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN not found in library "work" or "__hyper__lib__", but found in library CORERXIODBITALIGN_LIB
@N:CG364 : CoreRxIODBitAlign.v(2) | Synthesizing module CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	LP_PULSE_WD=32'b00000000000000000000000000010000
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
	LP_P_WD=32'b00000000000000000000000000001001
	BITALIGN_IDLE_ST=5'b00000
	BITALIGN_LOAD_ST=5'b00001
	BITALIGN_CLRFLAGS_ST=5'b00010
	BITALIGN_EM_ST=5'b00011
	BITALIGN_TAPSTORE_ST=5'b00100
	BITALIGN_TAPCALC_ST=5'b00101
	BITALIGN_TAPCALC_STRT_DLY_ST=5'b00110
	BITALIGN_TAPCALC_STRT_DLY1_ST=5'b00111
	BITALIGN_TAPCALC_STRT_DLY2_ST=5'b01000
	BITALIGN_TAPCALC_STRT_ST=5'b01001
	BITALIGN_ELY_DLY_ST=5'b01010
	BITALIGN_ELY_DLY1_ST=5'b01011
	BITALIGN_ELY_DLY2_ST=5'b01100
	BITALIGN_ELY_ST=5'b01101
	BITALIGN_LTE_DLY_ST=5'b01110
	BITALIGN_LTE_DLY1_ST=5'b01111
	BITALIGN_LTE_DLY2_ST=5'b10000
	BITALIGN_LTE_ST=5'b10001
	BITALIGN_NOELY_NOLTE_DLY_ST=5'b10010
	BITALIGN_NOELY_NOLTE_DLY1_ST=5'b10011
	BITALIGN_NOELY_NOLTE_DLY2_ST=5'b10100
	BITALIGN_NOELY_NOLTE_ST=5'b10101
	BITALIGN_VALID_TAP_CHK_DLY_ST=5'b10110
	BITALIGN_VALID_TAP_CHK_ST=5'b10111
	BITALIGN_TAPCMP_ST=5'b11000
	BITALIGN_TAPCMP2_ST=5'b11001
	BITALIGN_VALID_TAP_WAIT_ST1=5'b11010
	BITALIGN_VALID_TAP_WAIT_ST2=5'b11011
	BITALIGN_DONE_ST=5'b11100
	BITALIGN_HOLD_ST=5'b11101
	BITALIGN_LP_WAIT_ST=5'b11110
   Generated name = CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0
@N:CG179 : CoreRxIODBitAlign.v(631) | Removing redundant assignment.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG360 : CoreRxIODBitAlign.v(177) | Removing wire re_train, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0 .......
@W:CL271 : CoreRxIODBitAlign.v(982) | Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL208 : CoreRxIODBitAlign.v(1031) | All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W:CL113 : CoreRxIODBitAlign.v(982) | Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL250 : CoreRxIODBitAlign.v(982) | All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(1107) | Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : CoreRxIODBitAlign.v(269) | Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreRxIODBitAlign.v(1107) | Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0 (CPU Time 0h:00m:00s, Memory Used current: 182MB peak: 189MB)
@N:CG364 : CoreRxIODBitAlign_top.v(2) | Synthesizing module CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000011010
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TRNG_MODE=32'b00000000000000000000000000000001
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
   Generated name = CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8
@W:CG360 : CoreRxIODBitAlign_top.v(68) | Removing wire HS_RESETN, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 182MB peak: 189MB)
@N:CG364 : CORERXIODBITALIGN_C0.v(25) | Synthesizing module CORERXIODBITALIGN_C0 in library work.
Running optimization stage 1 on CORERXIODBITALIGN_C0 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C0 (CPU Time 0h:00m:00s, Memory Used current: 182MB peak: 189MB)
@N:CG775 : CoreRxIODBitAlign_top.v(2) | Component CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN not found in library "work" or "__hyper__lib__", but found in library CORERXIODBITALIGN_LIB
@N:CG364 : CoreRxIODBitAlign.v(2) | Synthesizing module CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	LP_PULSE_WD=32'b00000000000000000000000000010000
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
	LP_P_WD=32'b00000000000000000000000000001001
	BITALIGN_IDLE_ST=5'b00000
	BITALIGN_LOAD_ST=5'b00001
	BITALIGN_CLRFLAGS_ST=5'b00010
	BITALIGN_EM_ST=5'b00011
	BITALIGN_TAPSTORE_ST=5'b00100
	BITALIGN_TAPCALC_ST=5'b00101
	BITALIGN_TAPCALC_STRT_DLY_ST=5'b00110
	BITALIGN_TAPCALC_STRT_DLY1_ST=5'b00111
	BITALIGN_TAPCALC_STRT_DLY2_ST=5'b01000
	BITALIGN_TAPCALC_STRT_ST=5'b01001
	BITALIGN_ELY_DLY_ST=5'b01010
	BITALIGN_ELY_DLY1_ST=5'b01011
	BITALIGN_ELY_DLY2_ST=5'b01100
	BITALIGN_ELY_ST=5'b01101
	BITALIGN_LTE_DLY_ST=5'b01110
	BITALIGN_LTE_DLY1_ST=5'b01111
	BITALIGN_LTE_DLY2_ST=5'b10000
	BITALIGN_LTE_ST=5'b10001
	BITALIGN_NOELY_NOLTE_DLY_ST=5'b10010
	BITALIGN_NOELY_NOLTE_DLY1_ST=5'b10011
	BITALIGN_NOELY_NOLTE_DLY2_ST=5'b10100
	BITALIGN_NOELY_NOLTE_ST=5'b10101
	BITALIGN_VALID_TAP_CHK_DLY_ST=5'b10110
	BITALIGN_VALID_TAP_CHK_ST=5'b10111
	BITALIGN_TAPCMP_ST=5'b11000
	BITALIGN_TAPCMP2_ST=5'b11001
	BITALIGN_VALID_TAP_WAIT_ST1=5'b11010
	BITALIGN_VALID_TAP_WAIT_ST2=5'b11011
	BITALIGN_DONE_ST=5'b11100
	BITALIGN_HOLD_ST=5'b11101
	BITALIGN_LP_WAIT_ST=5'b11110
   Generated name = CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0
@N:CG179 : CoreRxIODBitAlign.v(631) | Removing redundant assignment.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG360 : CoreRxIODBitAlign.v(177) | Removing wire re_train, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0 .......
@W:CL271 : CoreRxIODBitAlign.v(982) | Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL208 : CoreRxIODBitAlign.v(1031) | All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W:CL113 : CoreRxIODBitAlign.v(982) | Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL250 : CoreRxIODBitAlign.v(982) | All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(1107) | Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : CoreRxIODBitAlign.v(269) | Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreRxIODBitAlign.v(1107) | Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0 (CPU Time 0h:00m:00s, Memory Used current: 183MB peak: 203MB)
@N:CG364 : CoreRxIODBitAlign_top.v(2) | Synthesizing module CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000011010
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TRNG_MODE=32'b00000000000000000000000000000001
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
   Generated name = CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8
@W:CG360 : CoreRxIODBitAlign_top.v(68) | Removing wire HS_RESETN, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 160MB peak: 203MB)
@N:CG364 : CORERXIODBITALIGN_C1.v(25) | Synthesizing module CORERXIODBITALIGN_C1 in library work.
Running optimization stage 1 on CORERXIODBITALIGN_C1 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C1 (CPU Time 0h:00m:00s, Memory Used current: 160MB peak: 203MB)
@N:CG775 : CoreRxIODBitAlign_top.v(2) | Component CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN not found in library "work" or "__hyper__lib__", but found in library CORERXIODBITALIGN_LIB
@N:CG364 : CoreRxIODBitAlign.v(2) | Synthesizing module CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	LP_PULSE_WD=32'b00000000000000000000000000010000
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
	LP_P_WD=32'b00000000000000000000000000001001
	BITALIGN_IDLE_ST=5'b00000
	BITALIGN_LOAD_ST=5'b00001
	BITALIGN_CLRFLAGS_ST=5'b00010
	BITALIGN_EM_ST=5'b00011
	BITALIGN_TAPSTORE_ST=5'b00100
	BITALIGN_TAPCALC_ST=5'b00101
	BITALIGN_TAPCALC_STRT_DLY_ST=5'b00110
	BITALIGN_TAPCALC_STRT_DLY1_ST=5'b00111
	BITALIGN_TAPCALC_STRT_DLY2_ST=5'b01000
	BITALIGN_TAPCALC_STRT_ST=5'b01001
	BITALIGN_ELY_DLY_ST=5'b01010
	BITALIGN_ELY_DLY1_ST=5'b01011
	BITALIGN_ELY_DLY2_ST=5'b01100
	BITALIGN_ELY_ST=5'b01101
	BITALIGN_LTE_DLY_ST=5'b01110
	BITALIGN_LTE_DLY1_ST=5'b01111
	BITALIGN_LTE_DLY2_ST=5'b10000
	BITALIGN_LTE_ST=5'b10001
	BITALIGN_NOELY_NOLTE_DLY_ST=5'b10010
	BITALIGN_NOELY_NOLTE_DLY1_ST=5'b10011
	BITALIGN_NOELY_NOLTE_DLY2_ST=5'b10100
	BITALIGN_NOELY_NOLTE_ST=5'b10101
	BITALIGN_VALID_TAP_CHK_DLY_ST=5'b10110
	BITALIGN_VALID_TAP_CHK_ST=5'b10111
	BITALIGN_TAPCMP_ST=5'b11000
	BITALIGN_TAPCMP2_ST=5'b11001
	BITALIGN_VALID_TAP_WAIT_ST1=5'b11010
	BITALIGN_VALID_TAP_WAIT_ST2=5'b11011
	BITALIGN_DONE_ST=5'b11100
	BITALIGN_HOLD_ST=5'b11101
	BITALIGN_LP_WAIT_ST=5'b11110
   Generated name = CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0
@N:CG179 : CoreRxIODBitAlign.v(631) | Removing redundant assignment.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG360 : CoreRxIODBitAlign.v(177) | Removing wire re_train, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0 .......
@W:CL271 : CoreRxIODBitAlign.v(982) | Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL208 : CoreRxIODBitAlign.v(1031) | All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W:CL113 : CoreRxIODBitAlign.v(982) | Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL250 : CoreRxIODBitAlign.v(982) | All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(1107) | Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : CoreRxIODBitAlign.v(269) | Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreRxIODBitAlign.v(1107) | Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0 (CPU Time 0h:00m:00s, Memory Used current: 183MB peak: 203MB)
@N:CG364 : CoreRxIODBitAlign_top.v(2) | Synthesizing module CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000011010
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TRNG_MODE=32'b00000000000000000000000000000001
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
   Generated name = CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8
@W:CG360 : CoreRxIODBitAlign_top.v(68) | Removing wire HS_RESETN, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 183MB peak: 203MB)
@N:CG364 : CORERXIODBITALIGN_C2.v(25) | Synthesizing module CORERXIODBITALIGN_C2 in library work.
Running optimization stage 1 on CORERXIODBITALIGN_C2 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C2 (CPU Time 0h:00m:00s, Memory Used current: 183MB peak: 203MB)
@N:CG775 : CoreRxIODBitAlign_top.v(2) | Component CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN not found in library "work" or "__hyper__lib__", but found in library CORERXIODBITALIGN_LIB
@N:CG364 : CoreRxIODBitAlign.v(2) | Synthesizing module CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	LP_PULSE_WD=32'b00000000000000000000000000010000
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
	LP_P_WD=32'b00000000000000000000000000001001
	BITALIGN_IDLE_ST=5'b00000
	BITALIGN_LOAD_ST=5'b00001
	BITALIGN_CLRFLAGS_ST=5'b00010
	BITALIGN_EM_ST=5'b00011
	BITALIGN_TAPSTORE_ST=5'b00100
	BITALIGN_TAPCALC_ST=5'b00101
	BITALIGN_TAPCALC_STRT_DLY_ST=5'b00110
	BITALIGN_TAPCALC_STRT_DLY1_ST=5'b00111
	BITALIGN_TAPCALC_STRT_DLY2_ST=5'b01000
	BITALIGN_TAPCALC_STRT_ST=5'b01001
	BITALIGN_ELY_DLY_ST=5'b01010
	BITALIGN_ELY_DLY1_ST=5'b01011
	BITALIGN_ELY_DLY2_ST=5'b01100
	BITALIGN_ELY_ST=5'b01101
	BITALIGN_LTE_DLY_ST=5'b01110
	BITALIGN_LTE_DLY1_ST=5'b01111
	BITALIGN_LTE_DLY2_ST=5'b10000
	BITALIGN_LTE_ST=5'b10001
	BITALIGN_NOELY_NOLTE_DLY_ST=5'b10010
	BITALIGN_NOELY_NOLTE_DLY1_ST=5'b10011
	BITALIGN_NOELY_NOLTE_DLY2_ST=5'b10100
	BITALIGN_NOELY_NOLTE_ST=5'b10101
	BITALIGN_VALID_TAP_CHK_DLY_ST=5'b10110
	BITALIGN_VALID_TAP_CHK_ST=5'b10111
	BITALIGN_TAPCMP_ST=5'b11000
	BITALIGN_TAPCMP2_ST=5'b11001
	BITALIGN_VALID_TAP_WAIT_ST1=5'b11010
	BITALIGN_VALID_TAP_WAIT_ST2=5'b11011
	BITALIGN_DONE_ST=5'b11100
	BITALIGN_HOLD_ST=5'b11101
	BITALIGN_LP_WAIT_ST=5'b11110
   Generated name = CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0
@N:CG179 : CoreRxIODBitAlign.v(631) | Removing redundant assignment.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : CoreRxIODBitAlign.v(245) | Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG360 : CoreRxIODBitAlign.v(177) | Removing wire re_train, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0 .......
@W:CL271 : CoreRxIODBitAlign.v(982) | Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : CoreRxIODBitAlign.v(269) | Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL208 : CoreRxIODBitAlign.v(1031) | All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W:CL113 : CoreRxIODBitAlign.v(982) | Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL250 : CoreRxIODBitAlign.v(982) | All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(269) | Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : CoreRxIODBitAlign.v(1107) | Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : CoreRxIODBitAlign.v(269) | Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreRxIODBitAlign.v(1107) | Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0 (CPU Time 0h:00m:00s, Memory Used current: 185MB peak: 204MB)
@N:CG364 : CoreRxIODBitAlign_top.v(2) | Synthesizing module CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN in library CORERXIODBITALIGN_LIB.

	MIPI_TRNG=32'b00000000000000000000000000000001
	SKIP_TRNG=32'b00000000000000000000000000000000
	HOLD_TRNG=32'b00000000000000000000000000000000
	FAMILY=32'b00000000000000000000000000011010
	DEM_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	DEM_TRNG_MODE=32'b00000000000000000000000000000001
	MIN_WINDOW_VALUE=32'b00000000000000000000000000001010
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	DEM_TAP_CNT=32'b00000000000000000000000100000000
	DEM_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
   Generated name = CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8
@W:CG360 : CoreRxIODBitAlign_top.v(68) | Removing wire HS_RESETN, as there is no assignment to it.
Running optimization stage 1 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 164MB peak: 204MB)
@N:CG364 : CORERXIODBITALIGN_C3.v(25) | Synthesizing module CORERXIODBITALIGN_C3 in library work.
Running optimization stage 1 on CORERXIODBITALIGN_C3 .......
Finished optimization stage 1 on CORERXIODBITALIGN_C3 (CPU Time 0h:00m:00s, Memory Used current: 164MB peak: 204MB)
@N:CG364 : acg5.v(357) | Synthesizing module INBUF_DIFF in library work.
Running optimization stage 1 on INBUF_DIFF .......
Finished optimization stage 1 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 164MB peak: 204MB)
@N:CG364 : CoreBclkSclkAlign.v(17) | Synthesizing module PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN in library work.

	IOG_FABRIC_RATIO=32'b00000000000000000000000000000100
	BCLKSCLK_TRN_MODE=32'b00000000000000000000000000000001
	FAMILY=32'b00000000000000000000000000011011
	CLK_ALGN_SKIP_TRNG=32'b00000000000000000000000000000001
	CLK_ALGN_HOLD_TRNG=32'b00000000000000000000000000000001
	BCLKSCLK_ICB_MODE=32'b00000000000000000000000000000001
	BCLKSCLK_ICB_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	ICB_CLK_ALGN_SKIP_TRNG=32'b00000000000000000000000000000001
	ICB_CLK_ALGN_HOLD_TRNG=32'b00000000000000000000000000000001
	PLL_CLK_ALGN_SKIP_TRNG=32'b00000000000000000000000000000000
	PLL_CLK_ALGN_HOLD_TRNG=32'b00000000000000000000000000000000
	BCLKSCLK_ICB_TAP_CNT=32'b00000000000000000000000100000000
	BCLKSCLK_ICB_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
   Generated name = PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0
@N:CG364 : ICB_BclkSclkAlign.v(2) | Synthesizing module ICB_BCLKSCLKALIGN in library work.

	BCLKSCLK_TRN_MODE=32'b00000000000000000000000000000001
	ICB_CLK_ALGN_SKIP_TRNG=32'b00000000000000000000000000000001
	ICB_CLK_ALGN_HOLD_TRNG=32'b00000000000000000000000000000001
	BCLKSCLK_ICB_TAP_WAIT_CNT_WIDTH=32'b00000000000000000000000000000011
	BCLKSCLK_ICB_TAP_CNT=32'b00000000000000000000000100000000
	BCLKSCLK_ICB_TAP_CNT_WIDTH=32'b00000000000000000000000000001000
	RST_CNT_WIDTH=32'b00000000000000000000000000001010
	CLKALIGN_HOLD_ST=6'b000000
	CLKALIGN_INIT_ST=6'b000001
	CLKALIGN_RESE_ST=6'b000010
	CLKALIGN_RESW_ST=6'b000011
	CLKALIGN_START_ST=6'b000100
	CLKALIGN_LOAD_ST=6'b000101
	CLKALIGN_CLRFLAGS_ST=6'b000110
	CLKALIGN_EM_ST=6'b000111
	CLKALIGN_TAPSTORE_ST=6'b001000
	CLKALIGN_TAPCALC_ST=6'b001001
	CLKALIGN_TAPCALC_STRT_DLY_ST=6'b001010
	CLKALIGN_TAPCALC_STRT_DLY1_ST=6'b001011
	CLKALIGN_TAPCALC_STRT_DLY2_ST=6'b001100
	CLKALIGN_TAPCALC_STRT_ST=6'b001101
	CLKALIGN_INIT_ELY_LTE_DLY_ST=6'b001110
	CLKALIGN_INIT_ELY_LTE_DLY1_ST=6'b001111
	CLKALIGN_INIT_ELY_LTE_DLY2_ST=6'b010000
	CLKALIGN_INIT_ELY_LTE_ST=6'b010001
	CLKALIGN_INIT_NO_ELY_LTE_DLY_ST=6'b010010
	CLKALIGN_INIT_NO_ELY_LTE_DLY1_ST=6'b010011
	CLKALIGN_INIT_NO_ELY_LTE_DLY2_ST=6'b010100
	CLKALIGN_INIT_NO_ELY_LTE_ST=6'b010101
	CLKALIGN_NXT_ELY_LTE_DLY_ST=6'b010110
	CLKALIGN_NXT_ELY_LTE_DLY1_ST=6'b010111
	CLKALIGN_NXT_ELY_LTE_DLY2_ST=6'b011000
	CLKALIGN_NXT_ELY_LTE_ST=6'b011001
	CLKALIGN_VALID_TAP_CHK_DLY_ST=6'b011010
	CLKALIGN_VALID_TAP_CHK_ST=6'b011011
	CLKALIGN_TAPCMP_ST=6'b011100
	CLKALIGN_TAPCMP2_ST=6'b011101
	CLKALIGN_VALID_TAP_WAIT_ST1=6'b011110
	CLKALIGN_VALID_TAP_WAIT_ST2=6'b011111
	CLKALIGN_DONE_ST=6'b100000
	CLKALIGN_TAPCMP_OFFSET_ST=6'b100001
	CLKALIGN_TAPCMP2_OFFSET_ST=6'b100010
	CLKALIGN_VALID_TAP_WAIT_OFFSET_ST1=6'b100011
	CLKALIGN_VALID_TAP_WAIT_OFFSET_ST2=6'b100100
	CLKALIGN_PAUSE_ST=6'b100101
	CLKALIGN_RESE1_ST=6'b100110
	CLKALIGN_DONE1_ST=6'b100111
   Generated name = ICB_BCLKSCLKALIGN_Z9_layer0
@W:CG1340 : ICB_BclkSclkAlign.v(180) | Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : ICB_BclkSclkAlign.v(180) | Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : ICB_BclkSclkAlign.v(180) | Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W:CG1340 : ICB_BclkSclkAlign.v(180) | Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
Running optimization stage 1 on ICB_BCLKSCLKALIGN_Z9_layer0 .......
@W:CL265 : ICB_BclkSclkAlign.v(959) | Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ICB_BclkSclkAlign.v(761) | Removing unused bit 8 of sig_tapcnt_final_2[8:0]. Either assign all bits or reduce the width of the signal.
@W:CL265 : ICB_BclkSclkAlign.v(737) | Removing unused bit 8 of sig_tapcnt_final_1[8:0]. Either assign all bits or reduce the width of the signal.
Finished optimization stage 1 on ICB_BCLKSCLKALIGN_Z9_layer0 (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@W:CG360 : CoreBclkSclkAlign.v(82) | Removing wire PLL_VCOPHSEL_SCLK_SEL, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(83) | Removing wire PLL_VCOPHSEL_BCLK_SEL, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(84) | Removing wire PLL_VCOPHSEL_BCLK90_SEL, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(85) | Removing wire PLL_VCOPHSEL_MCLK_SEL, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(86) | Removing wire PLL_LOADPHS, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(87) | Removing wire PLL_PHS_ROTATE, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(88) | Removing wire PLL_PHS_DIRECTION, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(99) | Removing wire BCLKSCLK_BCLK_VCOPHSEL, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(124) | Removing wire PLL_BCLKSCLK_TRAIN_DONE, as there is no assignment to it.
@W:CG360 : CoreBclkSclkAlign.v(150) | Removing wire PLL_CLK_ALGN_PAUSE, as there is no assignment to it.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0 .......
@W:CL318 : CoreBclkSclkAlign.v(82) | *Output PLL_VCOPHSEL_SCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(83) | *Output PLL_VCOPHSEL_BCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(84) | *Output PLL_VCOPHSEL_BCLK90_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(85) | *Output PLL_VCOPHSEL_MCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(86) | *Output PLL_LOADPHS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(87) | *Output PLL_PHS_ROTATE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(88) | *Output PLL_PHS_DIRECTION has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreBclkSclkAlign.v(99) | *Output BCLKSCLK_BCLK_VCOPHSEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0 (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_TR.v(27) | Synthesizing module PF_IOD_GENERIC_RX_C0_TR in library work.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_TR .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_TR (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : polarfire_syn_comps.v(1470) | Synthesizing module HS_IO_CLK in library work.
Running optimization stage 1 on HS_IO_CLK .......
Finished optimization stage 1 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : acg5.v(181) | Synthesizing module MX2 in library work.
Running optimization stage 1 on MX2 .......
Finished optimization stage 1 on MX2 (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : polarfire_syn_comps.v(1505) | Synthesizing module ICB_CLKDIVDELAY in library work.
Running optimization stage 1 on ICB_CLKDIVDELAY .......
Finished optimization stage 1 on ICB_CLKDIVDELAY (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY.v(5) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY in library work.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY.v(5) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY in library work.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : polarfire_syn_comps.v(1738) | Synthesizing module IOD in library work.
Running optimization stage 1 on IOD .......
Finished optimization stage 1 on IOD (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v(5) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD in library work.
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v(60) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v(60) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : acg5.v(1781) | Synthesizing module INBUF_DIFF_MIPI in library work.
Running optimization stage 1 on INBUF_DIFF_MIPI .......
Finished optimization stage 1 on INBUF_DIFF_MIPI (CPU Time 0h:00m:00s, Memory Used current: 166MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v(5) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD in library work.
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v(152) | Input RX_N on instance I_IOD_2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v(196) | Input RX_N on instance I_IOD_3 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v(240) | Input RX_N on instance I_IOD_1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W:CG781 : PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v(295) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : polarfire_syn_comps.v(1979) | Synthesizing module LANECTRL in library work.
Running optimization stage 1 on LANECTRL .......
Finished optimization stage 1 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : PF_LANECTRL_PAUSE_SYNC.v(13) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC in library work.

	ENABLE_PAUSE_EXTENSION=3'b011
   Generated name = PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_3
@N:CG364 : acg5.v(4) | Synthesizing module SLE in library work.
Running optimization stage 1 on SLE .......
Finished optimization stage 1 on SLE (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@W:CG133 : PF_LANECTRL_PAUSE_SYNC.v(20) | Object pause_reg_0 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : PF_LANECTRL_PAUSE_SYNC.v(20) | Object pause_reg_1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : PF_LANECTRL_PAUSE_SYNC.v(20) | Object pause is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_3 .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_3 (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL.v(5) | Synthesizing module PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL in library work.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : PF_IOD_GENERIC_RX_C0.v(59) | Synthesizing module PF_IOD_GENERIC_RX_C0 in library work.
Running optimization stage 1 on PF_IOD_GENERIC_RX_C0 .......
Finished optimization stage 1 on PF_IOD_GENERIC_RX_C0 (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : CAM_IOD_TIP_TOP.v(9) | Synthesizing module CAM_IOD_TIP_TOP in library work.
Running optimization stage 1 on CAM_IOD_TIP_TOP .......
Finished optimization stage 1 on CAM_IOD_TIP_TOP (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : IMX334_IF_TOP.v(9) | Synthesizing module IMX334_IF_TOP in library work.
Running optimization stage 1 on IMX334_IF_TOP .......
Finished optimization stage 1 on IMX334_IF_TOP (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@N:CG364 : acg5.v(484) | Synthesizing module RCLKINT in library work.
Running optimization stage 1 on RCLKINT .......
Finished optimization stage 1 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 167MB peak: 204MB)
@W:CG168 : PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v(318) | Type of parameter INTERFACE_LEVEL on the instance LANE3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : polarfire_syn_comps.v(9980) | Synthesizing module XCVR_PMA in library work.
Running optimization stage 1 on XCVR_PMA .......
Finished optimization stage 1 on XCVR_PMA (CPU Time 0h:00m:00s, Memory Used current: 168MB peak: 204MB)
@W:CG168 : PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v(611) | Type of parameter INTERFACE_LEVEL on the instance LANE2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v(905) | Type of parameter INTERFACE_LEVEL on the instance LANE1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v(1201) | Type of parameter INTERFACE_LEVEL on the instance LANE0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v(5) | Synthesizing module PF_XCVR_ERM_C0_I_XCVR_PF_XCVR in library work.
Running optimization stage 1 on PF_XCVR_ERM_C0_I_XCVR_PF_XCVR .......
Finished optimization stage 1 on PF_XCVR_ERM_C0_I_XCVR_PF_XCVR (CPU Time 0h:00m:00s, Memory Used current: 168MB peak: 204MB)
@N:CG364 : PF_XCVR_ERM_C0.v(70) | Synthesizing module PF_XCVR_ERM_C0 in library work.
Running optimization stage 1 on PF_XCVR_ERM_C0 .......
Finished optimization stage 1 on PF_XCVR_ERM_C0 (CPU Time 0h:00m:00s, Memory Used current: 168MB peak: 204MB)
@N:CG364 : video_axi_fifo.v(15) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo in library work.

	FAMILY=32'b00000000000000000000000000011010
	SYNC=32'b00000000000000000000000000000001
	RCLK_EDGE=32'b00000000000000000000000000000001
	WCLK_EDGE=32'b00000000000000000000000000000001
	RE_POLARITY=32'b00000000000000000000000000000000
	WE_POLARITY=32'b00000000000000000000000000000000
	RWIDTH=32'b00000000000000000000001000000000
	WWIDTH=32'b00000000000000000000001000000000
	RDEPTH=32'b00000000000000000000000100000000
	WDEPTH=32'b00000000000000000000000100000000
	READ_DVALID=32'b00000000000000000000000000000001
	WRITE_ACK=32'b00000000000000000000000000000000
	CTRL_TYPE=32'b00000000000000000000000000000010
	ESTOP=32'b00000000000000000000000000000001
	FSTOP=32'b00000000000000000000000000000001
	AE_STATIC_EN=32'b00000000000000000000000000000001
	AF_STATIC_EN=32'b00000000000000000000000000000001
	AEVAL=32'b00000000000000000000000000000010
	AFVAL=32'b00000000000000000000000011110000
	PIPE=32'b00000000000000000000000000000001
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	ECC=32'b00000000000000000000000000000000
	RESET_POLARITY=32'b00000000000000000000000000000000
	OVERFLOW_EN=32'b00000000000000000000000000000000
	UNDERFLOW_EN=32'b00000000000000000000000000000000
	WRCNT_EN=32'b00000000000000000000000000000000
	RDCNT_EN=32'b00000000000000000000000000000001
	NUM_STAGES=32'b00000000000000000000000000000010
	WMSB_DEPTH=32'b00000000000000000000000000001000
	RMSB_DEPTH=32'b00000000000000000000000000001000
	WDEPTH_CAL=32'b00000000000000000000000000000111
	RDEPTH_CAL=32'b00000000000000000000000000000111
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0
@W:CG168 : video_axi_fifo.v(461) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : axi_lbus_corefifo_sync_scntr.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr in library work.

	WRITE_WIDTH=32'b00000000000000000000001000000000
	WRITE_DEPTH=32'b00000000000000000000000000001000
	FULL_WRITE_DEPTH=32'b00000000000000000000000100000000
	READ_WIDTH=32'b00000000000000000000001000000000
	READ_DEPTH=32'b00000000000000000000000000001000
	FULL_READ_DEPTH=32'b00000000000000000000000100000000
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	WCLK_HIGH=32'b00000000000000000000000000000001
	RESET_LOW=32'b00000000000000000000000000000000
	WRITE_LOW=32'b00000000000000000000000000000000
	READ_LOW=32'b00000000000000000000000000000000
	AF_FLAG_STATIC=32'b00000000000000000000000000000001
	AE_FLAG_STATIC=32'b00000000000000000000000000000001
	AFULL_VAL=32'b00000000000000000000000011110000
	AEMPTY_VAL=32'b00000000000000000000000000000010
	ESTOP=32'b00000000000000000000000000000001
	FSTOP=32'b00000000000000000000000000000001
	PIPE=32'b00000000000000000000000000000001
	REGISTER_RADDR=32'b00000000000000000000000000000001
	READ_DVALID=32'b00000000000000000000000000000001
	WRITE_ACK=32'b00000000000000000000000000000000
	OVERFLOW_EN=32'b00000000000000000000000000000000
	UNDERFLOW_EN=32'b00000000000000000000000000000000
	WRCNT_EN=32'b00000000000000000000000000000000
	RDCNT_EN=32'b00000000000000000000000000000001
	ECC=32'b00000000000000000000000000000000
	WDEPTH_CAL=32'b00000000000000000000000000000111
	RDEPTH_CAL=32'b00000000000000000000000000000111
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z11_layer0
@W:CG360 : axi_lbus_corefifo_sync_scntr.v(158) | Removing wire neg_reset, as there is no assignment to it.
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z11_layer0 .......
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(365) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(349) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(349) | Pruning unused register full_reg. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(349) | Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(453) | All reachable assignments to genblk7.wack_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(453) | All reachable assignments to genblk7.overflow_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(365) | All reachable assignments to underflow_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(203) | All reachable assignments to wrcnt[8:0] assign 0, register removed by optimization.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z11_layer0 (CPU Time 0h:00m:00s, Memory Used current: 169MB peak: 204MB)
@N:CG364 : axi_lbus_corefifo_fwft.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft in library work.

	RDEPTH=32'b00000000000000000000000000001000
	WWIDTH=32'b00000000000000000000001000000000
	RWIDTH=32'b00000000000000000000001000000000
	WCLK_HIGH=32'b00000000000000000000000000000001
	RCLK_HIGH=32'b00000000000000000000000000000001
	RESET_LOW=32'b00000000000000000000000000000000
	WRITE_LOW=32'b00000000000000000000000000000000
	READ_LOW=32'b00000000000000000000000000000000
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	SYNC=32'b00000000000000000000000000000001
	RDEPTH_CAL=32'b00000000000000000000000000000111
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z12_layer0
@N:CG179 : axi_lbus_corefifo_fwft.v(180) | Removing redundant assignment.
@W:CG133 : axi_lbus_corefifo_fwft.v(87) | Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : axi_lbus_corefifo_fwft.v(93) | Removing wire aresetn, as there is no assignment to it.
@W:CG360 : axi_lbus_corefifo_fwft.v(99) | Removing wire empty1, as there is no assignment to it.
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z12_layer0 .......
@W:CL169 : axi_lbus_corefifo_fwft.v(260) | Pruning unused register we_p_r. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_fwft.v(170) | Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_fwft.v(162) | Pruning unused register re_p_d. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_fwft.v(147) | Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_fwft.v(147) | Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z12_layer0 (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 204MB)
@N:CG364 : axi_lbus_LSRAM_top.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top in library work.

	RWIDTH=32'b00000000000000000000001000000000
	WWIDTH=32'b00000000000000000000001000000000
	RDEPTH=32'b00000000000000000000000000001000
	WDEPTH=32'b00000000000000000000000000001000
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_512s_512s_8_8
@N:CG364 : acg5.v(578) | Synthesizing module RAM1K20 in library work.
Running optimization stage 1 on RAM1K20 .......
Finished optimization stage 1 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 204MB)
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_512s_512s_8_8 .......
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_512s_512s_8_8 (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 204MB)
@N:CG364 : axi_lbus_ram_wrapper.v(17) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper in library work.

	RWIDTH=32'b00000000000000000000001000000000
	WWIDTH=32'b00000000000000000000001000000000
	RDEPTH=32'b00000000000000000000000000001000
	WDEPTH=32'b00000000000000000000000000001000
	SYNC=32'b00000000000000000000000000000001
	PIPE=32'b00000000000000000000000000000001
	CTRL_TYPE=32'b00000000000000000000000000000010
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s .......
@W:CL318 : axi_lbus_ram_wrapper.v(57) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(58) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(59) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(60) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s (CPU Time 0h:00m:00s, Memory Used current: 171MB peak: 204MB)
@W:CG360 : video_axi_fifo.v(150) | Removing wire SB_CORRECT, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(151) | Removing wire DB_DETECT, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(188) | Removing wire pf_MEMRADDR, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(194) | Removing wire pf_Q, as there is no assignment to it.
@W:CG184 : video_axi_fifo.v(212) | Removing wire DVLD_async, as it has the load but no drivers.
@W:CG184 : video_axi_fifo.v(214) | Removing wire DVLD_sync, as it has the load but no drivers.
@W:CG360 : video_axi_fifo.v(217) | Removing wire pf_dvld, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(222) | Removing wire A_SB_CORRECT, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(223) | Removing wire A_DB_DETECT, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(224) | Removing wire B_SB_CORRECT, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(225) | Removing wire B_DB_DETECT, as there is no assignment to it.
@W:CG133 : video_axi_fifo.v(226) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : video_axi_fifo.v(240) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
@W:CG360 : video_axi_fifo.v(255) | Removing wire reset_sync_r, as there is no assignment to it.
@W:CG360 : video_axi_fifo.v(256) | Removing wire reset_sync_w, as there is no assignment to it.
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0 .......
@W:CL318 : video_axi_fifo.v(150) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : video_axi_fifo.v(151) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL169 : video_axi_fifo.v(965) | Pruning unused register RDATA_ext_r1[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(955) | Pruning unused register RDATA_ext_r[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register REN_d2. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register REN_d3. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register RE_d2. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register RE_d3. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(893) | Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(881) | Pruning unused register RDATA_r2[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(871) | Pruning unused register RDATA_r1[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(861) | Pruning unused register RDATA_r_pre[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(851) | Pruning unused register fwft_Q_r[511:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(379) | Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(379) | Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(379) | Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(367) | Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers.
@W:CL169 : video_axi_fifo.v(367) | Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG364 : video_axi_fifo.v(15) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo in library work.

	FAMILY=32'b00000000000000000000000000011010
	SYNC=32'b00000000000000000000000000000001
	RCLK_EDGE=32'b00000000000000000000000000000001
	WCLK_EDGE=32'b00000000000000000000000000000001
	RE_POLARITY=32'b00000000000000000000000000000000
	WE_POLARITY=32'b00000000000000000000000000000000
	RWIDTH=32'b00000000000000000000000000010000
	WWIDTH=32'b00000000000000000000000000010000
	RDEPTH=32'b00000000000000000000000000000101
	WDEPTH=32'b00000000000000000000000000000101
	READ_DVALID=32'b00000000000000000000000000000000
	WRITE_ACK=32'b00000000000000000000000000000000
	CTRL_TYPE=32'b00000000000000000000000000000010
	ESTOP=32'b00000000000000000000000000000001
	FSTOP=32'b00000000000000000000000000000001
	AE_STATIC_EN=32'b00000000000000000000000000000001
	AF_STATIC_EN=32'b00000000000000000000000000000001
	AEVAL=32'b00000000000000000000000000000010
	AFVAL=32'b00000000000000000000000000000100
	PIPE=32'b00000000000000000000000000000001
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	ECC=32'b00000000000000000000000000000000
	RESET_POLARITY=32'b00000000000000000000000000000000
	OVERFLOW_EN=32'b00000000000000000000000000000000
	UNDERFLOW_EN=32'b00000000000000000000000000000000
	WRCNT_EN=32'b00000000000000000000000000000000
	RDCNT_EN=32'b00000000000000000000000000000001
	NUM_STAGES=32'b00000000000000000000000000000010
	WMSB_DEPTH=32'b00000000000000000000000000000011
	RMSB_DEPTH=32'b00000000000000000000000000000011
	WDEPTH_CAL=32'b00000000000000000000000000000010
	RDEPTH_CAL=32'b00000000000000000000000000000010
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z13_layer0
@W:CG168 : video_axi_fifo.v(461) | Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@N:CG364 : axi_lbus_corefifo_sync_scntr.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr in library work.

	WRITE_WIDTH=32'b00000000000000000000000000010000
	WRITE_DEPTH=32'b00000000000000000000000000000011
	FULL_WRITE_DEPTH=32'b00000000000000000000000000000101
	READ_WIDTH=32'b00000000000000000000000000010000
	READ_DEPTH=32'b00000000000000000000000000000011
	FULL_READ_DEPTH=32'b00000000000000000000000000000101
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	WCLK_HIGH=32'b00000000000000000000000000000001
	RESET_LOW=32'b00000000000000000000000000000000
	WRITE_LOW=32'b00000000000000000000000000000000
	READ_LOW=32'b00000000000000000000000000000000
	AF_FLAG_STATIC=32'b00000000000000000000000000000001
	AE_FLAG_STATIC=32'b00000000000000000000000000000001
	AFULL_VAL=32'b00000000000000000000000000000100
	AEMPTY_VAL=32'b00000000000000000000000000000010
	ESTOP=32'b00000000000000000000000000000001
	FSTOP=32'b00000000000000000000000000000001
	PIPE=32'b00000000000000000000000000000001
	REGISTER_RADDR=32'b00000000000000000000000000000001
	READ_DVALID=32'b00000000000000000000000000000000
	WRITE_ACK=32'b00000000000000000000000000000000
	OVERFLOW_EN=32'b00000000000000000000000000000000
	UNDERFLOW_EN=32'b00000000000000000000000000000000
	WRCNT_EN=32'b00000000000000000000000000000000
	RDCNT_EN=32'b00000000000000000000000000000001
	ECC=32'b00000000000000000000000000000000
	WDEPTH_CAL=32'b00000000000000000000000000000010
	RDEPTH_CAL=32'b00000000000000000000000000000010
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z14_layer0
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z14_layer0 .......
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(365) | Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
@W:CL169 : axi_lbus_corefifo_sync_scntr.v(349) | Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.

Only the first 100 messages of id 'CL169' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CL169' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL169} -count unlimited' in the Tcl shell.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(453) | All reachable assignments to genblk7.wack_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(453) | All reachable assignments to genblk7.overflow_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(365) | All reachable assignments to underflow_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(365) | All reachable assignments to dvld_r assign 0, register removed by optimization.
@W:CL207 : axi_lbus_corefifo_sync_scntr.v(203) | All reachable assignments to wrcnt[3:0] assign 0, register removed by optimization.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z14_layer0 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG364 : axi_lbus_corefifo_fwft.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft in library work.

	RDEPTH=32'b00000000000000000000000000000011
	WWIDTH=32'b00000000000000000000000000010000
	RWIDTH=32'b00000000000000000000000000010000
	WCLK_HIGH=32'b00000000000000000000000000000001
	RCLK_HIGH=32'b00000000000000000000000000000001
	RESET_LOW=32'b00000000000000000000000000000000
	WRITE_LOW=32'b00000000000000000000000000000000
	READ_LOW=32'b00000000000000000000000000000000
	PREFETCH=32'b00000000000000000000000000000000
	FWFT=32'b00000000000000000000000000000001
	SYNC=32'b00000000000000000000000000000001
	RDEPTH_CAL=32'b00000000000000000000000000000010
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z15_layer0
@W:CG133 : axi_lbus_corefifo_fwft.v(87) | Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z15_layer0 .......
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z15_layer0 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG364 : axi_lbus_LSRAM_top.v(16) | Synthesizing module ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top in library work.

	RWIDTH=32'b00000000000000000000000000010000
	WWIDTH=32'b00000000000000000000000000010000
	RDEPTH=32'b00000000000000000000000000000011
	WDEPTH=32'b00000000000000000000000000000011
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_16s_16s_3_3
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_16s_16s_3_3 .......
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_16s_16s_3_3 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)

Only the first 100 messages of id 'CG364' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CG364' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG364} -count unlimited' in the Tcl shell.

	RWIDTH=32'b00000000000000000000000000010000
	WWIDTH=32'b00000000000000000000000000010000
	RDEPTH=32'b00000000000000000000000000000011
	WDEPTH=32'b00000000000000000000000000000011
	SYNC=32'b00000000000000000000000000000001
	PIPE=32'b00000000000000000000000000000001
	CTRL_TYPE=32'b00000000000000000000000000000010
   Generated name = ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s .......
@W:CL318 : axi_lbus_ram_wrapper.v(57) | *Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(58) | *Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(59) | *Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : axi_lbus_ram_wrapper.v(60) | *Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@W:CG133 : video_axi_fifo.v(226) | Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : video_axi_fifo.v(240) | Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z13_layer0 .......
@W:CL318 : video_axi_fifo.v(150) | *Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : video_axi_fifo.v(151) | *Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
Finished optimization stage 1 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z13_layer0 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)

	AXI_ID_WIDTH=32'b00000000000000000000000000000100
	AXI_ADDR_WIDTH=32'b00000000000000000000000000100000
	AXI_DATA_WIDTH=32'b00000000000000000000001000000000
	AXI_LEN_WIDTH=32'b00000000000000000000000000010000
	VIDEO_BUS_ASIZE=32'b00000000000000000000000000100100
	VIDEO_BUS_DSIZE=32'b00000000000000000000001000000000
	ALL_ADDRESS_ZEROS=32'b00000000000000000000000000000000
	ALL_DATA_ZEROS=512'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
	ALL_DATA_ONES=512'b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
	ALL_SIZE_VAL=3'b110
	STRB_WIDTH=32'b00000000000000000000000001000000
	RDEPTH=32'b00000000000000000000000100000000
	RDEPTH2=32'b00000000000000000000000100000000
	RDEPTH3=32'b00000000000000000000000011110000
	IDLE=32'b00000000000000000000000000000000
	ADDRESS_CHK=32'b00000000000000000000000000000001
	WR_ADDRESS=32'b00000000000000000000000000000010
	WR_DATA=32'b00000000000000000000000000000011
	WR_DATA_LAST=32'b00000000000000000000000000000100
	READ_ADDRESS=32'b00000000000000000000000000000101
	WAIT_ST=32'b00000000000000000000000000000110
	WREADY_CHK=32'b00000000000000000000000000000001
	WLAST_CHK=32'b00000000000000000000000000000010
	WLAST_CHK0SIZE=32'b00000000000000000000000000000011
	RLAST_CHK=1'b1
   Generated name = ddr_rw_arbiter_lpddr4_Z16_layer0
Running optimization stage 1 on ddr_rw_arbiter_lpddr4_Z16_layer0 .......
@A:CL282 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal v_wr_len_fifo_wrdata[15:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element bready and merging rready. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awsize[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awprot[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awlock[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awid[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awcache[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element awcache and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal awburst[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arsize[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arsize and merging awsize. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arprot[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arprot and merging awprot. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arlock[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arlock and merging awlock. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arid[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arid and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arcache[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arcache and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL113 : ddr_rw_arbiter_lpddr4.v(400) | Feedback mux created for signal arburst[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arburst and merging awburst. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL177 : ddr_rw_arbiter_lpddr4.v(400) | Sharing sequential element arburst and merging awburst. Add a syn_preserve attribute to the element to prevent sharing.
@W:CL251 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to arsize[2:1] assign 1, register removed by optimization
@W:CL250 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awburst[1] assign 0, register removed by optimization
@W:CL251 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awburst[0] assign 1, register removed by optimization
@W:CL250 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awid[3:0] assign 0, register removed by optimization
@W:CL250 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awlock[1:0] assign 0, register removed by optimization
@W:CL250 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awprot[2:0] assign 0, register removed by optimization
@W:CL251 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awsize[2:1] assign 1, register removed by optimization
@W:CL250 : ddr_rw_arbiter_lpddr4.v(400) | All reachable assignments to awsize[0] assign 0, register removed by optimization
Finished optimization stage 1 on ddr_rw_arbiter_lpddr4_Z16_layer0 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
Running optimization stage 1 on DFN1 .......
Finished optimization stage 1 on DFN1 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG794 : read_top.v(172) | Using module read_demux from library work
@N:CG794 : read_top.v(195) | Using module read_mux from library work
@N:CG794 : read_top.v(212) | Using module request_scheduler from library work
Running optimization stage 1 on read_top .......
Finished optimization stage 1 on read_top (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG794 : write_top.v(197) | Using module write_demux from library work
@N:CG794 : write_top.v(215) | Using module write_mux from library work
Running optimization stage 1 on write_top .......
Finished optimization stage 1 on write_top (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
Running optimization stage 1 on Video_arbiter_top_LPDDR4 .......
Finished optimization stage 1 on Video_arbiter_top_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG794 : video_processing.v(156) | Using module apb3_interface from library work
@N:CG794 : video_processing.v(180) | Using module Bayer_Interpolation_C0 from library work
@N:CG794 : video_processing.v(197) | Using module Gamma_Correction_C0 from library work
@N:CG794 : video_processing.v(213) | Using module Image_Enhancement_C0 from library work
@N:CG794 : video_processing.v(230) | Using module intensity_average from library work
@N:CG794 : video_processing.v(244) | Using module RGBtoYCbCr_C0 from library work
Running optimization stage 1 on video_processing .......
Finished optimization stage 1 on video_processing (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@N:CG794 : DDR4_RD_WR.v(532) | Using module Display_Controller_C0 from library work
@N:CG794 : DDR4_RD_WR.v(550) | Using module HDMI_TX_C0 from library work
@N:CG794 : DDR4_RD_WR.v(764) | Using module YCbCrtoRGB_C0 from library work
Running optimization stage 1 on DDR4_RD_WR .......
Finished optimization stage 1 on DDR4_RD_WR (CPU Time 0h:00m:00s, Memory Used current: 172MB peak: 204MB)
@W:CG1283 : DMA_MASTER.v(4559) | Ignoring localparam ADDR_WIDTH_INT on the instance and using locally defined value
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE0_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE1_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE2_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE3_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE4_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE5_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE6_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE7_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE8_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE9_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE10_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE11_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE12_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE13_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE14_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE15_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE16_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE17_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE18_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE19_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE20_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE21_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE22_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE23_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE24_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE25_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE26_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE27_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE28_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE29_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE30_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE31_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE0_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE1_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE2_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE3_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE4_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE5_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE6_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE7_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE8_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE9_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE10_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE11_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE12_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE13_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE14_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE15_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE16_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE17_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE18_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE19_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE20_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE21_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE22_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE23_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE24_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE25_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE26_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE27_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE28_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE29_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE30_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE31_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE0_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE1_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE2_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE3_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE4_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE5_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE6_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE7_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE8_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE9_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE10_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE11_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE12_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE13_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE14_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE15_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE16_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE17_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W:CG168 : DMA_MASTER.v(4559) | Type of parameter SLAVE18_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 

Only the first 100 messages of id 'CG168' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CG168' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG168} -count unlimited' in the Tcl shell.
Running optimization stage 1 on caxi4interconnect_ResetSycnc .......
Finished optimization stage 1 on caxi4interconnect_ResetSycnc (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 204MB)

	FAMILY=32'b00000000000000000000000000010011
	NUM_MASTERS=32'b00000000000000000000000000000001
	NUM_SLAVES=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	NUM_THREADS=32'b00000000000000000000000000000100
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	OPEN_WRTRANS_MAX=32'b00000000000000000000000000000101
	OPEN_RDTRANS_MAX=32'b00000000000000000000000000000101
	UPPER_COMPARE_BIT=32'b00000000000000000000000000100000
	LOWER_COMPARE_BIT=32'b00000000000000000000000000000000
	SLOT_BASE_VEC=2'b00
	SLOT_MIN_VEC=32'b10000000000000000000000000000000
	SLOT_MAX_VEC=32'b10101111111111111111111111111111
	SUPPORT_USER_SIGNALS=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	CROSSBAR_MODE=32'b00000000000000000000000000000000
	MASTER_WRITE_CONNECTIVITY=1'b1
	MASTER_READ_CONNECTIVITY=1'b1
	NUM_MASTERS_WIDTH=32'b00000000000000000000000000000001
	HI_FREQ=32'b00000000000000000000000000000001
	RD_ARB_EN=32'b00000000000000000000000000000000
	READ_INTERLEAVE=1'b0
	NUM_SLAVES_INT=32'b00000000000000000000000000000010
	NUM_SLAVES_WIDTH=32'b00000000000000000000000000000001
	ADDR_WIDTH_BITS=32'b00000000000000000000000000000101
	NUM_THREADS_WIDTH=32'b00000000000000000000000000000010
	OPEN_TRANS_WIDTH=32'b00000000000000000000000000000100
	MASTERID_WIDTH=32'b00000000000000000000000000000101
	MASTER_READ_CONNECTIVITY_INT=2'b11
	MASTER_WRITE_CONNECTIVITY_INT=2'b11
   Generated name = caxi4interconnect_Axi4CrossBar_Z17_layer0
@W:CG360 : Axi4CrossBar.v(229) | Removing wire currRDataTransID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(230) | Removing wire openRTransDec, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(232) | Removing wire currWDataTransID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(233) | Removing wire openWTransDec, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(235) | Removing wire sysReset, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(237) | Removing wire dataFifoWr, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(238) | Removing wire srcPort, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(239) | Removing wire destPort, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(240) | Removing wire wrFifoFull, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(242) | Removing wire rdDataFifoWr, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(243) | Removing wire rdSrcPort, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(244) | Removing wire rdDestPort, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(245) | Removing wire rdFifoFull, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(250) | Removing wire DERR_ARID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(251) | Removing wire DERR_ARLEN, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(252) | Removing wire DERR_ARVALID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(253) | Removing wire DERR_ARREADY, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(255) | Removing wire DERR_RID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(256) | Removing wire DERR_RDATA, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(257) | Removing wire DERR_RRESP, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(258) | Removing wire DERR_RLAST, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(259) | Removing wire DERR_RUSER, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(260) | Removing wire DERR_RVALID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(261) | Removing wire DERR_RREADY, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(263) | Removing wire DERR_AWID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(264) | Removing wire DERR_AWLEN, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(265) | Removing wire DERR_AWVALID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(266) | Removing wire DERR_AWREADY, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(268) | Removing wire DERR_WID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(269) | Removing wire DERR_WDATA, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(270) | Removing wire DERR_WSTRB, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(271) | Removing wire DERR_WLAST, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(272) | Removing wire DERR_WUSER, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(273) | Removing wire DERR_WVALID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(274) | Removing wire DERR_WREADY, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(276) | Removing wire DERR_BID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(277) | Removing wire DERR_BRESP, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(278) | Removing wire DERR_BUSER, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(279) | Removing wire DERR_BVALID, as there is no assignment to it.
@W:CG360 : Axi4CrossBar.v(280) | Removing wire DERR_BREADY, as there is no assignment to it.
@W:CG133 : Axi4CrossBar.v(318) | Object i is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on caxi4interconnect_Axi4CrossBar_Z17_layer0 .......
Finished optimization stage 1 on caxi4interconnect_Axi4CrossBar_Z17_layer0 (CPU Time 0h:00m:00s, Memory Used current: 175MB peak: 204MB)

	FAMILY=32'b00000000000000000000000000011011
	NUM_MASTERS=32'b00000000000000000000000000000001
	NUM_SLAVES=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	ADDR_WIDTH=32'b00000000000000000000000000100000
	OPTIMIZATION=32'b00000000000000000000000000000001
	DATA_WIDTH=32'b00000000000000000000000001000000
	NUM_THREADS=32'b00000000000000000000000000000100
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	ADDR_WIDTH_INT=32'b00000000000000000000000000100000
	SLAVE0_START_ADDR=32'b10000000000000000000000000000000
	SLAVE1_START_ADDR=32'b01100001000000000000000000000000
	SLAVE2_START_ADDR=32'b01100000000000100000000000000000
	SLAVE3_START_ADDR=32'b00011000000000000000000000000000
	SLAVE4_START_ADDR=32'b00100000000000000000000000000000
	SLAVE5_START_ADDR=32'b00101000000000000000000000000000
	SLAVE6_START_ADDR=32'b00110000000000000000000000000000
	SLAVE7_START_ADDR=32'b00111000000000000000000000000000
	SLAVE8_START_ADDR=32'b01000000000000000000000000000000
	SLAVE9_START_ADDR=32'b01001000000000000000000000000000
	SLAVE10_START_ADDR=32'b01010000000000000000000000000000
	SLAVE11_START_ADDR=32'b01011000000000000000000000000000
	SLAVE12_START_ADDR=32'b10010000000000000000000000000000
	SLAVE13_START_ADDR=32'b10010000001100000000000000000000
	SLAVE14_START_ADDR=32'b10010000011000000000000000000000
	SLAVE15_START_ADDR=32'b10010000100100000000000000000000
	SLAVE16_START_ADDR=32'b10010000110000000000000000000000
	SLAVE17_START_ADDR=32'b10010000111100000000000000000000
	SLAVE18_START_ADDR=32'b10010001001000000000000000000000
	SLAVE19_START_ADDR=32'b10010001010100000000000000000000
	SLAVE20_START_ADDR=32'b10010001100000000000000000000000
	SLAVE21_START_ADDR=32'b10010001101100000000000000000000
	SLAVE22_START_ADDR=32'b10010001111000000000000000000000
	SLAVE23_START_ADDR=32'b10010010000100000000000000000000
	SLAVE24_START_ADDR=32'b10010010010000000000000000000000
	SLAVE25_START_ADDR=32'b10010010011100000000000000000000
	SLAVE26_START_ADDR=32'b10010010101000000000000000000000
	SLAVE27_START_ADDR=32'b10010010110100000000000000000000
	SLAVE28_START_ADDR=32'b10010011000000000000000000000000
	SLAVE29_START_ADDR=32'b10010011001100000000000000000000
	SLAVE30_START_ADDR=32'b10010011011000000000000000000000
	SLAVE31_START_ADDR=32'b10010011100100000000000000000000
	SLAVE0_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE1_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE2_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE3_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE4_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE5_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE6_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE7_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE8_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE9_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE10_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE11_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE12_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE13_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE14_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE15_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE16_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE17_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE18_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE19_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE20_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE21_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE22_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE23_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE24_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE25_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE26_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE27_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE28_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE29_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE30_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE31_START_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE0_END_ADDR=32'b10101111111111111111111111111111
	SLAVE1_END_ADDR=32'b01101111111111111111111111111111
	SLAVE2_END_ADDR=32'b01100000000000101111111111111111
	SLAVE3_END_ADDR=32'b00011111111111111111111111111111
	SLAVE4_END_ADDR=32'b00100111111111111111111111111111
	SLAVE5_END_ADDR=32'b00101111111111111111111111111111
	SLAVE6_END_ADDR=32'b00110111111111111111111111111111
	SLAVE7_END_ADDR=32'b00111111111111111111111111111111
	SLAVE8_END_ADDR=32'b01000111111111111111111111111111
	SLAVE9_END_ADDR=32'b01001111111111111111111111111111
	SLAVE10_END_ADDR=32'b01010111111111111111111111111111
	SLAVE11_END_ADDR=32'b01011111111111111111111111111111
	SLAVE12_END_ADDR=32'b10010000001011111111111111111111
	SLAVE13_END_ADDR=32'b10010000010111111111111111111111
	SLAVE14_END_ADDR=32'b10010000100011111111111111111111
	SLAVE15_END_ADDR=32'b10010000101111111111111111111111
	SLAVE16_END_ADDR=32'b10010000111011111111111111111111
	SLAVE17_END_ADDR=32'b10010001000111111111111111111111
	SLAVE18_END_ADDR=32'b10010001010011111111111111111111
	SLAVE19_END_ADDR=32'b10010001011111111111111111111111
	SLAVE20_END_ADDR=32'b10010001101011111111111111111111
	SLAVE21_END_ADDR=32'b10010001110111111111111111111111
	SLAVE22_END_ADDR=32'b10010010000011111111111111111111
	SLAVE23_END_ADDR=32'b10010010001111111111111111111111
	SLAVE24_END_ADDR=32'b10010010011011111111111111111111
	SLAVE25_END_ADDR=32'b10010010100111111111111111111111
	SLAVE26_END_ADDR=32'b10010010110011111111111111111111
	SLAVE27_END_ADDR=32'b10010010111111111111111111111111
	SLAVE28_END_ADDR=32'b10010011001011111111111111111111
	SLAVE29_END_ADDR=32'b10010011010111111111111111111111
	SLAVE30_END_ADDR=32'b10010011100011111111111111111111
	SLAVE31_END_ADDR=32'b10010011101111111111111111111111
	SLAVE0_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE1_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE2_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE3_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE4_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE5_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE6_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE7_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE8_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE9_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE10_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE11_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE12_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE13_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE14_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE15_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE16_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE17_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE18_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE19_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE20_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE21_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE22_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE23_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE24_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE25_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE26_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE27_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE28_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE29_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE30_END_ADDR_UPPER=32'b00000000000000000000000000000000
	SLAVE31_END_ADDR_UPPER=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	CROSSBAR_MODE=32'b00000000000000000000000000000000
	MASTER0_WRITE_SLAVE0=1'b1
	MASTER0_WRITE_SLAVE1=1'b1
	MASTER0_WRITE_SLAVE2=1'b1
	MASTER0_WRITE_SLAVE3=1'b1
	MASTER0_WRITE_SLAVE4=1'b1
	MASTER0_WRITE_SLAVE5=1'b1
	MASTER0_WRITE_SLAVE6=1'b1
	MASTER0_WRITE_SLAVE7=1'b1
	MASTER0_WRITE_SLAVE8=1'b1
	MASTER0_WRITE_SLAVE9=1'b1
	MASTER0_WRITE_SLAVE10=1'b1
	MASTER0_WRITE_SLAVE11=1'b1
	MASTER0_WRITE_SLAVE12=1'b1
	MASTER0_WRITE_SLAVE13=1'b1
	MASTER0_WRITE_SLAVE14=1'b1
	MASTER0_WRITE_SLAVE15=1'b1
	MASTER0_WRITE_SLAVE16=1'b1
	MASTER0_WRITE_SLAVE17=1'b1
	MASTER0_WRITE_SLAVE18=1'b1
	MASTER0_WRITE_SLAVE19=1'b1
	MASTER0_WRITE_SLAVE20=1'b1
	MASTER0_WRITE_SLAVE21=1'b1
	MASTER0_WRITE_SLAVE22=1'b1
	MASTER0_WRITE_SLAVE23=1'b1
	MASTER0_WRITE_SLAVE24=1'b1
	MASTER0_WRITE_SLAVE25=1'b1
	MASTER0_WRITE_SLAVE26=1'b1
	MASTER0_WRITE_SLAVE27=1'b1
	MASTER0_WRITE_SLAVE28=1'b1
	MASTER0_WRITE_SLAVE29=1'b1
	MASTER0_WRITE_SLAVE30=1'b1
	MASTER0_WRITE_SLAVE31=1'b1
	MASTER1_WRITE_SLAVE0=1'b1
	MASTER1_WRITE_SLAVE1=1'b1
	MASTER1_WRITE_SLAVE2=1'b1
	MASTER1_WRITE_SLAVE3=1'b1
	MASTER1_WRITE_SLAVE4=1'b1
	MASTER1_WRITE_SLAVE5=1'b1
	MASTER1_WRITE_SLAVE6=1'b1
	MASTER1_WRITE_SLAVE7=1'b1
	MASTER1_WRITE_SLAVE8=1'b1
	MASTER1_WRITE_SLAVE9=1'b1
	MASTER1_WRITE_SLAVE10=1'b1
	MASTER1_WRITE_SLAVE11=1'b1
	MASTER1_WRITE_SLAVE12=1'b1
	MASTER1_WRITE_SLAVE13=1'b1
	MASTER1_WRITE_SLAVE14=1'b1
	MASTER1_WRITE_SLAVE15=1'b1
	MASTER1_WRITE_SLAVE16=1'b1
	MASTER1_WRITE_SLAVE17=1'b1
	MASTER1_WRITE_SLAVE18=1'b1
	MASTER1_WRITE_SLAVE19=1'b1
	MASTER1_WRITE_SLAVE20=1'b1
	MASTER1_WRITE_SLAVE21=1'b1
	MASTER1_WRITE_SLAVE22=1'b1
	MASTER1_WRITE_SLAVE23=1'b1
	MASTER1_WRITE_SLAVE24=1'b1
	MASTER1_WRITE_SLAVE25=1'b1
	MASTER1_WRITE_SLAVE26=1'b1
	MASTER1_WRITE_SLAVE27=1'b1
	MASTER1_WRITE_SLAVE28=1'b1
	MASTER1_WRITE_SLAVE29=1'b1
	MASTER1_WRITE_SLAVE30=1'b1
	MASTER1_WRITE_SLAVE31=1'b1
	MASTER2_WRITE_SLAVE0=1'b1
	MASTER2_WRITE_SLAVE1=1'b1
	MASTER2_WRITE_SLAVE2=1'b1
	MASTER2_WRITE_SLAVE3=1'b1
	MASTER2_WRITE_SLAVE4=1'b1
	MASTER2_WRITE_SLAVE5=1'b1
	MASTER2_WRITE_SLAVE6=1'b1
	MASTER2_WRITE_SLAVE7=1'b1
	MASTER2_WRITE_SLAVE8=1'b1
	MASTER2_WRITE_SLAVE9=1'b1
	MASTER2_WRITE_SLAVE10=1'b1
	MASTER2_WRITE_SLAVE11=1'b1
	MASTER2_WRITE_SLAVE12=1'b1
	MASTER2_WRITE_SLAVE13=1'b1
	MASTER2_WRITE_SLAVE14=1'b1
	MASTER2_WRITE_SLAVE15=1'b1
	MASTER2_WRITE_SLAVE16=1'b1
	MASTER2_WRITE_SLAVE17=1'b1
	MASTER2_WRITE_SLAVE18=1'b1
	MASTER2_WRITE_SLAVE19=1'b1
	MASTER2_WRITE_SLAVE20=1'b1
	MASTER2_WRITE_SLAVE21=1'b1
	MASTER2_WRITE_SLAVE22=1'b1
	MASTER2_WRITE_SLAVE23=1'b1
	MASTER2_WRITE_SLAVE24=1'b1
	MASTER2_WRITE_SLAVE25=1'b1
	MASTER2_WRITE_SLAVE26=1'b1
	MASTER2_WRITE_SLAVE27=1'b1
	MASTER2_WRITE_SLAVE28=1'b1
	MASTER2_WRITE_SLAVE29=1'b1
	MASTER2_WRITE_SLAVE30=1'b1
	MASTER2_WRITE_SLAVE31=1'b1
	MASTER3_WRITE_SLAVE0=1'b1
	MASTER3_WRITE_SLAVE1=1'b1
	MASTER3_WRITE_SLAVE2=1'b1
	MASTER3_WRITE_SLAVE3=1'b1
	MASTER3_WRITE_SLAVE4=1'b1
	MASTER3_WRITE_SLAVE5=1'b1
	MASTER3_WRITE_SLAVE6=1'b1
	MASTER3_WRITE_SLAVE7=1'b1
	MASTER3_WRITE_SLAVE8=1'b1
	MASTER3_WRITE_SLAVE9=1'b1
	MASTER3_WRITE_SLAVE10=1'b1
	MASTER3_WRITE_SLAVE11=1'b1
	MASTER3_WRITE_SLAVE12=1'b1
	MASTER3_WRITE_SLAVE13=1'b1
	MASTER3_WRITE_SLAVE14=1'b1
	MASTER3_WRITE_SLAVE15=1'b1
	MASTER3_WRITE_SLAVE16=1'b1
	MASTER3_WRITE_SLAVE17=1'b1
	MASTER3_WRITE_SLAVE18=1'b1
	MASTER3_WRITE_SLAVE19=1'b1
	MASTER3_WRITE_SLAVE20=1'b1
	MASTER3_WRITE_SLAVE21=1'b1
	MASTER3_WRITE_SLAVE22=1'b1
	MASTER3_WRITE_SLAVE23=1'b1
	MASTER3_WRITE_SLAVE24=1'b1
	MASTER3_WRITE_SLAVE25=1'b1
	MASTER3_WRITE_SLAVE26=1'b1
	MASTER3_WRITE_SLAVE27=1'b1
	MASTER3_WRITE_SLAVE28=1'b1
	MASTER3_WRITE_SLAVE29=1'b1
	MASTER3_WRITE_SLAVE30=1'b1
	MASTER3_WRITE_SLAVE31=1'b1
	MASTER4_WRITE_SLAVE0=1'b1
	MASTER4_WRITE_SLAVE1=1'b1
	MASTER4_WRITE_SLAVE2=1'b1
	MASTER4_WRITE_SLAVE3=1'b1
	MASTER4_WRITE_SLAVE4=1'b1
	MASTER4_WRITE_SLAVE5=1'b1
	MASTER4_WRITE_SLAVE6=1'b1
	MASTER4_WRITE_SLAVE7=1'b1
	MASTER4_WRITE_SLAVE8=1'b1
	MASTER4_WRITE_SLAVE9=1'b1
	MASTER4_WRITE_SLAVE10=1'b1
	MASTER4_WRITE_SLAVE11=1'b1
	MASTER4_WRITE_SLAVE12=1'b1
	MASTER4_WRITE_SLAVE13=1'b1
	MASTER4_WRITE_SLAVE14=1'b1
	MASTER4_WRITE_SLAVE15=1'b1
	MASTER4_WRITE_SLAVE16=1'b1
	MASTER4_WRITE_SLAVE17=1'b1
	MASTER4_WRITE_SLAVE18=1'b1
	MASTER4_WRITE_SLAVE19=1'b1
	MASTER4_WRITE_SLAVE20=1'b1
	MASTER4_WRITE_SLAVE21=1'b1
	MASTER4_WRITE_SLAVE22=1'b1
	MASTER4_WRITE_SLAVE23=1'b1
	MASTER4_WRITE_SLAVE24=1'b1
	MASTER4_WRITE_SLAVE25=1'b1
	MASTER4_WRITE_SLAVE26=1'b1
	MASTER4_WRITE_SLAVE27=1'b1
	MASTER4_WRITE_SLAVE28=1'b1
	MASTER4_WRITE_SLAVE29=1'b1
	MASTER4_WRITE_SLAVE30=1'b1
	MASTER4_WRITE_SLAVE31=1'b1
	MASTER5_WRITE_SLAVE0=1'b1
	MASTER5_WRITE_SLAVE1=1'b1
	MASTER5_WRITE_SLAVE2=1'b1
	MASTER5_WRITE_SLAVE3=1'b1
	MASTER5_WRITE_SLAVE4=1'b1
	MASTER5_WRITE_SLAVE5=1'b1
	MASTER5_WRITE_SLAVE6=1'b1
	MASTER5_WRITE_SLAVE7=1'b1
	MASTER5_WRITE_SLAVE8=1'b1
	MASTER5_WRITE_SLAVE9=1'b1
	MASTER5_WRITE_SLAVE10=1'b1
	MASTER5_WRITE_SLAVE11=1'b1
	MASTER5_WRITE_SLAVE12=1'b1
	MASTER5_WRITE_SLAVE13=1'b1
	MASTER5_WRITE_SLAVE14=1'b1
	MASTER5_WRITE_SLAVE15=1'b1
	MASTER5_WRITE_SLAVE16=1'b1
	MASTER5_WRITE_SLAVE17=1'b1
	MASTER5_WRITE_SLAVE18=1'b1
	MASTER5_WRITE_SLAVE19=1'b1
	MASTER5_WRITE_SLAVE20=1'b1
	MASTER5_WRITE_SLAVE21=1'b1
	MASTER5_WRITE_SLAVE22=1'b1
	MASTER5_WRITE_SLAVE23=1'b1
	MASTER5_WRITE_SLAVE24=1'b1
	MASTER5_WRITE_SLAVE25=1'b1
	MASTER5_WRITE_SLAVE26=1'b1
	MASTER5_WRITE_SLAVE27=1'b1
	MASTER5_WRITE_SLAVE28=1'b1
	MASTER5_WRITE_SLAVE29=1'b1
	MASTER5_WRITE_SLAVE30=1'b1
	MASTER5_WRITE_SLAVE31=1'b1
	MASTER6_WRITE_SLAVE0=1'b1
	MASTER6_WRITE_SLAVE1=1'b1
	MASTER6_WRITE_SLAVE2=1'b1
	MASTER6_WRITE_SLAVE3=1'b1
	MASTER6_WRITE_SLAVE4=1'b1
	MASTER6_WRITE_SLAVE5=1'b1
	MASTER6_WRITE_SLAVE6=1'b1
	MASTER6_WRITE_SLAVE7=1'b1
	MASTER6_WRITE_SLAVE8=1'b1
	MASTER6_WRITE_SLAVE9=1'b1
	MASTER6_WRITE_SLAVE10=1'b1
	MASTER6_WRITE_SLAVE11=1'b1
	MASTER6_WRITE_SLAVE12=1'b1
	MASTER6_WRITE_SLAVE13=1'b1
	MASTER6_WRITE_SLAVE14=1'b1
	MASTER6_WRITE_SLAVE15=1'b1
	MASTER6_WRITE_SLAVE16=1'b1
	MASTER6_WRITE_SLAVE17=1'b1
	MASTER6_WRITE_SLAVE18=1'b1
	MASTER6_WRITE_SLAVE19=1'b1
	MASTER6_WRITE_SLAVE20=1'b1
	MASTER6_WRITE_SLAVE21=1'b1
	MASTER6_WRITE_SLAVE22=1'b1
	MASTER6_WRITE_SLAVE23=1'b1
	MASTER6_WRITE_SLAVE24=1'b1
	MASTER6_WRITE_SLAVE25=1'b1
	MASTER6_WRITE_SLAVE26=1'b1
	MASTER6_WRITE_SLAVE27=1'b1
	MASTER6_WRITE_SLAVE28=1'b1
	MASTER6_WRITE_SLAVE29=1'b1
	MASTER6_WRITE_SLAVE30=1'b1
	MASTER6_WRITE_SLAVE31=1'b1
	MASTER7_WRITE_SLAVE0=1'b1
	MASTER7_WRITE_SLAVE1=1'b1
	MASTER7_WRITE_SLAVE2=1'b1
	MASTER7_WRITE_SLAVE3=1'b1
	MASTER7_WRITE_SLAVE4=1'b1
	MASTER7_WRITE_SLAVE5=1'b1
	MASTER7_WRITE_SLAVE6=1'b1
	MASTER7_WRITE_SLAVE7=1'b1
	MASTER7_WRITE_SLAVE8=1'b1
	MASTER7_WRITE_SLAVE9=1'b1
	MASTER7_WRITE_SLAVE10=1'b1
	MASTER7_WRITE_SLAVE11=1'b1
	MASTER7_WRITE_SLAVE12=1'b1
	MASTER7_WRITE_SLAVE13=1'b1
	MASTER7_WRITE_SLAVE14=1'b1
	MASTER7_WRITE_SLAVE15=1'b1
	MASTER7_WRITE_SLAVE16=1'b1
	MASTER7_WRITE_SLAVE17=1'b1
	MASTER7_WRITE_SLAVE18=1'b1
	MASTER7_WRITE_SLAVE19=1'b1
	MASTER7_WRITE_SLAVE20=1'b1
	MASTER7_WRITE_SLAVE21=1'b1
	MASTER7_WRITE_SLAVE22=1'b1
	MASTER7_WRITE_SLAVE23=1'b1
	MASTER7_WRITE_SLAVE24=1'b1
	MASTER7_WRITE_SLAVE25=1'b1
	MASTER7_WRITE_SLAVE26=1'b1
	MASTER7_WRITE_SLAVE27=1'b1
	MASTER7_WRITE_SLAVE28=1'b1
	MASTER7_WRITE_SLAVE29=1'b1
	MASTER7_WRITE_SLAVE30=1'b1
	MASTER7_WRITE_SLAVE31=1'b1
	MASTER8_WRITE_SLAVE0=1'b1
	MASTER8_WRITE_SLAVE1=1'b1
	MASTER8_WRITE_SLAVE2=1'b1
	MASTER8_WRITE_SLAVE3=1'b1
	MASTER8_WRITE_SLAVE4=1'b1
	MASTER8_WRITE_SLAVE5=1'b1
	MASTER8_WRITE_SLAVE6=1'b1
	MASTER8_WRITE_SLAVE7=1'b1
	MASTER8_WRITE_SLAVE8=1'b1
	MASTER8_WRITE_SLAVE9=1'b1
	MASTER8_WRITE_SLAVE10=1'b1
	MASTER8_WRITE_SLAVE11=1'b1
	MASTER8_WRITE_SLAVE12=1'b1
	MASTER8_WRITE_SLAVE13=1'b1
	MASTER8_WRITE_SLAVE14=1'b1
	MASTER8_WRITE_SLAVE15=1'b1
	MASTER8_WRITE_SLAVE16=1'b1
	MASTER8_WRITE_SLAVE17=1'b1
	MASTER8_WRITE_SLAVE18=1'b1
	MASTER8_WRITE_SLAVE19=1'b1
	MASTER8_WRITE_SLAVE20=1'b1
	MASTER8_WRITE_SLAVE21=1'b1
	MASTER8_WRITE_SLAVE22=1'b1
	MASTER8_WRITE_SLAVE23=1'b1
	MASTER8_WRITE_SLAVE24=1'b1
	MASTER8_WRITE_SLAVE25=1'b1
	MASTER8_WRITE_SLAVE26=1'b1
	MASTER8_WRITE_SLAVE27=1'b1
	MASTER8_WRITE_SLAVE28=1'b1
	MASTER8_WRITE_SLAVE29=1'b1
	MASTER8_WRITE_SLAVE30=1'b1
	MASTER8_WRITE_SLAVE31=1'b1
	MASTER9_WRITE_SLAVE0=1'b1
	MASTER9_WRITE_SLAVE1=1'b1
	MASTER9_WRITE_SLAVE2=1'b1
	MASTER9_WRITE_SLAVE3=1'b1
	MASTER9_WRITE_SLAVE4=1'b1
	MASTER9_WRITE_SLAVE5=1'b1
	MASTER9_WRITE_SLAVE6=1'b1
	MASTER9_WRITE_SLAVE7=1'b1
	MASTER9_WRITE_SLAVE8=1'b1
	MASTER9_WRITE_SLAVE9=1'b1
	MASTER9_WRITE_SLAVE10=1'b1
	MASTER9_WRITE_SLAVE11=1'b1
	MASTER9_WRITE_SLAVE12=1'b1
	MASTER9_WRITE_SLAVE13=1'b1
	MASTER9_WRITE_SLAVE14=1'b1
	MASTER9_WRITE_SLAVE15=1'b1
	MASTER9_WRITE_SLAVE16=1'b1
	MASTER9_WRITE_SLAVE17=1'b1
	MASTER9_WRITE_SLAVE18=1'b1
	MASTER9_WRITE_SLAVE19=1'b1
	MASTER9_WRITE_SLAVE20=1'b1
	MASTER9_WRITE_SLAVE21=1'b1
	MASTER9_WRITE_SLAVE22=1'b1
	MASTER9_WRITE_SLAVE23=1'b1
	MASTER9_WRITE_SLAVE24=1'b1
	MASTER9_WRITE_SLAVE25=1'b1
	MASTER9_WRITE_SLAVE26=1'b1
	MASTER9_WRITE_SLAVE27=1'b1
	MASTER9_WRITE_SLAVE28=1'b1
	MASTER9_WRITE_SLAVE29=1'b1
	MASTER9_WRITE_SLAVE30=1'b1
	MASTER9_WRITE_SLAVE31=1'b1
	MASTER10_WRITE_SLAVE0=1'b1
	MASTER10_WRITE_SLAVE1=1'b1
	MASTER10_WRITE_SLAVE2=1'b1
	MASTER10_WRITE_SLAVE3=1'b1
	MASTER10_WRITE_SLAVE4=1'b1
	MASTER10_WRITE_SLAVE5=1'b1
	MASTER10_WRITE_SLAVE6=1'b1
	MASTER10_WRITE_SLAVE7=1'b1
	MASTER10_WRITE_SLAVE8=1'b1
	MASTER10_WRITE_SLAVE9=1'b1
	MASTER10_WRITE_SLAVE10=1'b1
	MASTER10_WRITE_SLAVE11=1'b1
	MASTER10_WRITE_SLAVE12=1'b1
	MASTER10_WRITE_SLAVE13=1'b1
	MASTER10_WRITE_SLAVE14=1'b1
	MASTER10_WRITE_SLAVE15=1'b1
	MASTER10_WRITE_SLAVE16=1'b1
	MASTER10_WRITE_SLAVE17=1'b1
	MASTER10_WRITE_SLAVE18=1'b1
	MASTER10_WRITE_SLAVE19=1'b1
	MASTER10_WRITE_SLAVE20=1'b1
	MASTER10_WRITE_SLAVE21=1'b1
	MASTER10_WRITE_SLAVE22=1'b1
	MASTER10_WRITE_SLAVE23=1'b1
	MASTER10_WRITE_SLAVE24=1'b1
	MASTER10_WRITE_SLAVE25=1'b1
	MASTER10_WRITE_SLAVE26=1'b1
	MASTER10_WRITE_SLAVE27=1'b1
	MASTER10_WRITE_SLAVE28=1'b1
	MASTER10_WRITE_SLAVE29=1'b1
	MASTER10_WRITE_SLAVE30=1'b1
	MASTER10_WRITE_SLAVE31=1'b1
	MASTER11_WRITE_SLAVE0=1'b1
	MASTER11_WRITE_SLAVE1=1'b1
	MASTER11_WRITE_SLAVE2=1'b1
	MASTER11_WRITE_SLAVE3=1'b1
	MASTER11_WRITE_SLAVE4=1'b1
	MASTER11_WRITE_SLAVE5=1'b1
	MASTER11_WRITE_SLAVE6=1'b1
	MASTER11_WRITE_SLAVE7=1'b1
	MASTER11_WRITE_SLAVE8=1'b1
	MASTER11_WRITE_SLAVE9=1'b1
	MASTER11_WRITE_SLAVE10=1'b1
	MASTER11_WRITE_SLAVE11=1'b1
	MASTER11_WRITE_SLAVE12=1'b1
	MASTER11_WRITE_SLAVE13=1'b1
	MASTER11_WRITE_SLAVE14=1'b1
	MASTER11_WRITE_SLAVE15=1'b1
	MASTER11_WRITE_SLAVE16=1'b1
	MASTER11_WRITE_SLAVE17=1'b1
	MASTER11_WRITE_SLAVE18=1'b1
	MASTER11_WRITE_SLAVE19=1'b1
	MASTER11_WRITE_SLAVE20=1'b1
	MASTER11_WRITE_SLAVE21=1'b1
	MASTER11_WRITE_SLAVE22=1'b1
	MASTER11_WRITE_SLAVE23=1'b1
	MASTER11_WRITE_SLAVE24=1'b1
	MASTER11_WRITE_SLAVE25=1'b1
	MASTER11_WRITE_SLAVE26=1'b1
	MASTER11_WRITE_SLAVE27=1'b1
	MASTER11_WRITE_SLAVE28=1'b1
	MASTER11_WRITE_SLAVE29=1'b1
	MASTER11_WRITE_SLAVE30=1'b1
	MASTER11_WRITE_SLAVE31=1'b1
	MASTER12_WRITE_SLAVE0=1'b1
	MASTER12_WRITE_SLAVE1=1'b1
	MASTER12_WRITE_SLAVE2=1'b1
	MASTER12_WRITE_SLAVE3=1'b1
	MASTER12_WRITE_SLAVE4=1'b1
	MASTER12_WRITE_SLAVE5=1'b1
	MASTER12_WRITE_SLAVE6=1'b1
	MASTER12_WRITE_SLAVE7=1'b1
	MASTER12_WRITE_SLAVE8=1'b1
	MASTER12_WRITE_SLAVE9=1'b1
	MASTER12_WRITE_SLAVE10=1'b1
	MASTER12_WRITE_SLAVE11=1'b1
	MASTER12_WRITE_SLAVE12=1'b1
	MASTER12_WRITE_SLAVE13=1'b1
	MASTER12_WRITE_SLAVE14=1'b1
	MASTER12_WRITE_SLAVE15=1'b1
	MASTER12_WRITE_SLAVE16=1'b1
	MASTER12_WRITE_SLAVE17=1'b1
	MASTER12_WRITE_SLAVE18=1'b1
	MASTER12_WRITE_SLAVE19=1'b1
	MASTER12_WRITE_SLAVE20=1'b1
	MASTER12_WRITE_SLAVE21=1'b1
	MASTER12_WRITE_SLAVE22=1'b1
	MASTER12_WRITE_SLAVE23=1'b1
	MASTER12_WRITE_SLAVE24=1'b1
	MASTER12_WRITE_SLAVE25=1'b1
	MASTER12_WRITE_SLAVE26=1'b1
	MASTER12_WRITE_SLAVE27=1'b1
	MASTER12_WRITE_SLAVE28=1'b1
	MASTER12_WRITE_SLAVE29=1'b1
	MASTER12_WRITE_SLAVE30=1'b1
	MASTER12_WRITE_SLAVE31=1'b1
	MASTER13_WRITE_SLAVE0=1'b1
	MASTER13_WRITE_SLAVE1=1'b1
	MASTER13_WRITE_SLAVE2=1'b1
	MASTER13_WRITE_SLAVE3=1'b1
	MASTER13_WRITE_SLAVE4=1'b1
	MASTER13_WRITE_SLAVE5=1'b1
	MASTER13_WRITE_SLAVE6=1'b1
	MASTER13_WRITE_SLAVE7=1'b1
	MASTER13_WRITE_SLAVE8=1'b1
	MASTER13_WRITE_SLAVE9=1'b1
	MASTER13_WRITE_SLAVE10=1'b1
	MASTER13_WRITE_SLAVE11=1'b1
	MASTER13_WRITE_SLAVE12=1'b1
	MASTER13_WRITE_SLAVE13=1'b1
	MASTER13_WRITE_SLAVE14=1'b1
	MASTER13_WRITE_SLAVE15=1'b1
	MASTER13_WRITE_SLAVE16=1'b1
	MASTER13_WRITE_SLAVE17=1'b1
	MASTER13_WRITE_SLAVE18=1'b1
	MASTER13_WRITE_SLAVE19=1'b1
	MASTER13_WRITE_SLAVE20=1'b1
	MASTER13_WRITE_SLAVE21=1'b1
	MASTER13_WRITE_SLAVE22=1'b1
	MASTER13_WRITE_SLAVE23=1'b1
	MASTER13_WRITE_SLAVE24=1'b1
	MASTER13_WRITE_SLAVE25=1'b1
	MASTER13_WRITE_SLAVE26=1'b1
	MASTER13_WRITE_SLAVE27=1'b1
	MASTER13_WRITE_SLAVE28=1'b1
	MASTER13_WRITE_SLAVE29=1'b1
	MASTER13_WRITE_SLAVE30=1'b1
	MASTER13_WRITE_SLAVE31=1'b1
	MASTER14_WRITE_SLAVE0=1'b1
	MASTER14_WRITE_SLAVE1=1'b1
	MASTER14_WRITE_SLAVE2=1'b1
	MASTER14_WRITE_SLAVE3=1'b1
	MASTER14_WRITE_SLAVE4=1'b1
	MASTER14_WRITE_SLAVE5=1'b1
	MASTER14_WRITE_SLAVE6=1'b1
	MASTER14_WRITE_SLAVE7=1'b1
	MASTER14_WRITE_SLAVE8=1'b1
	MASTER14_WRITE_SLAVE9=1'b1
	MASTER14_WRITE_SLAVE10=1'b1
	MASTER14_WRITE_SLAVE11=1'b1
	MASTER14_WRITE_SLAVE12=1'b1
	MASTER14_WRITE_SLAVE13=1'b1
	MASTER14_WRITE_SLAVE14=1'b1
	MASTER14_WRITE_SLAVE15=1'b1
	MASTER14_WRITE_SLAVE16=1'b1
	MASTER14_WRITE_SLAVE17=1'b1
	MASTER14_WRITE_SLAVE18=1'b1
	MASTER14_WRITE_SLAVE19=1'b1
	MASTER14_WRITE_SLAVE20=1'b1
	MASTER14_WRITE_SLAVE21=1'b1
	MASTER14_WRITE_SLAVE22=1'b1
	MASTER14_WRITE_SLAVE23=1'b1
	MASTER14_WRITE_SLAVE24=1'b1
	MASTER14_WRITE_SLAVE25=1'b1
	MASTER14_WRITE_SLAVE26=1'b1
	MASTER14_WRITE_SLAVE27=1'b1
	MASTER14_WRITE_SLAVE28=1'b1
	MASTER14_WRITE_SLAVE29=1'b1
	MASTER14_WRITE_SLAVE30=1'b1
	MASTER14_WRITE_SLAVE31=1'b1
	MASTER15_WRITE_SLAVE0=1'b1
	MASTER15_WRITE_SLAVE1=1'b1
	MASTER15_WRITE_SLAVE2=1'b1
	MASTER15_WRITE_SLAVE3=1'b1
	MASTER15_WRITE_SLAVE4=1'b1
	MASTER15_WRITE_SLAVE5=1'b1
	MASTER15_WRITE_SLAVE6=1'b1
	MASTER15_WRITE_SLAVE7=1'b1
	MASTER15_WRITE_SLAVE8=1'b1
	MASTER15_WRITE_SLAVE9=1'b1
	MASTER15_WRITE_SLAVE10=1'b1
	MASTER15_WRITE_SLAVE11=1'b1
	MASTER15_WRITE_SLAVE12=1'b1
	MASTER15_WRITE_SLAVE13=1'b1
	MASTER15_WRITE_SLAVE14=1'b1
	MASTER15_WRITE_SLAVE15=1'b1
	MASTER15_WRITE_SLAVE16=1'b1
	MASTER15_WRITE_SLAVE17=1'b1
	MASTER15_WRITE_SLAVE18=1'b1
	MASTER15_WRITE_SLAVE19=1'b1
	MASTER15_WRITE_SLAVE20=1'b1
	MASTER15_WRITE_SLAVE21=1'b1
	MASTER15_WRITE_SLAVE22=1'b1
	MASTER15_WRITE_SLAVE23=1'b1
	MASTER15_WRITE_SLAVE24=1'b1
	MASTER15_WRITE_SLAVE25=1'b1
	MASTER15_WRITE_SLAVE26=1'b1
	MASTER15_WRITE_SLAVE27=1'b1
	MASTER15_WRITE_SLAVE28=1'b1
	MASTER15_WRITE_SLAVE29=1'b1
	MASTER15_WRITE_SLAVE30=1'b1
	MASTER15_WRITE_SLAVE31=1'b1
	MASTER0_READ_SLAVE0=1'b1
	MASTER0_READ_SLAVE1=1'b1
	MASTER0_READ_SLAVE2=1'b1
	MASTER0_READ_SLAVE3=1'b1
	MASTER0_READ_SLAVE4=1'b1
	MASTER0_READ_SLAVE5=1'b1
	MASTER0_READ_SLAVE6=1'b1
	MASTER0_READ_SLAVE7=1'b1
	MASTER0_READ_SLAVE8=1'b1
	MASTER0_READ_SLAVE9=1'b1
	MASTER0_READ_SLAVE10=1'b1
	MASTER0_READ_SLAVE11=1'b1
	MASTER0_READ_SLAVE12=1'b1
	MASTER0_READ_SLAVE13=1'b1
	MASTER0_READ_SLAVE14=1'b1
	MASTER0_READ_SLAVE15=1'b1
	MASTER0_READ_SLAVE16=1'b1
	MASTER0_READ_SLAVE17=1'b1
	MASTER0_READ_SLAVE18=1'b1
	MASTER0_READ_SLAVE19=1'b1
	MASTER0_READ_SLAVE20=1'b1
	MASTER0_READ_SLAVE21=1'b1
	MASTER0_READ_SLAVE22=1'b1
	MASTER0_READ_SLAVE23=1'b1
	MASTER0_READ_SLAVE24=1'b1
	MASTER0_READ_SLAVE25=1'b1
	MASTER0_READ_SLAVE26=1'b1
	MASTER0_READ_SLAVE27=1'b1
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	MASTER15_READ_SLAVE3=1'b1
	MASTER15_READ_SLAVE4=1'b1
	MASTER15_READ_SLAVE5=1'b1
	MASTER15_READ_SLAVE6=1'b1
	MASTER15_READ_SLAVE7=1'b1
	MASTER15_READ_SLAVE8=1'b1
	MASTER15_READ_SLAVE9=1'b1
	MASTER15_READ_SLAVE10=1'b1
	MASTER15_READ_SLAVE11=1'b1
	MASTER15_READ_SLAVE12=1'b1
	MASTER15_READ_SLAVE13=1'b1
	MASTER15_READ_SLAVE14=1'b1
	MASTER15_READ_SLAVE15=1'b1
	MASTER15_READ_SLAVE16=1'b1
	MASTER15_READ_SLAVE17=1'b1
	MASTER15_READ_SLAVE18=1'b1
	MASTER15_READ_SLAVE19=1'b1
	MASTER15_READ_SLAVE20=1'b1
	MASTER15_READ_SLAVE21=1'b1
	MASTER15_READ_SLAVE22=1'b1
	MASTER15_READ_SLAVE23=1'b1
	MASTER15_READ_SLAVE24=1'b1
	MASTER15_READ_SLAVE25=1'b1
	MASTER15_READ_SLAVE26=1'b1
	MASTER15_READ_SLAVE27=1'b1
	MASTER15_READ_SLAVE28=1'b1
	MASTER15_READ_SLAVE29=1'b1
	MASTER15_READ_SLAVE30=1'b1
	MASTER15_READ_SLAVE31=1'b1
	RD_ARB_EN=32'b00000000000000000000000000000000
	MASTER0_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER1_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER2_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER3_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER4_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER5_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER6_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER7_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER8_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER9_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER10_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER11_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER12_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER13_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER14_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER15_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE0_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE1_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE2_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE3_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE4_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE5_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE6_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE7_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE8_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE9_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE10_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE11_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE12_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE13_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE14_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE15_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE16_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE17_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE18_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE19_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE20_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE21_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE22_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE23_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE24_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE25_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE26_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE27_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE28_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE29_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE30_CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE31_CLOCK_DOMAIN_CROSSING=1'b0
	MASTER0_TYPE=2'b00
	MASTER1_TYPE=2'b00
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	MASTER14_TYPE=2'b00
	MASTER15_TYPE=2'b00
	SLAVE0_TYPE=2'b00
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	SLAVE20_TYPE=2'b00
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	SLAVE24_TYPE=2'b00
	SLAVE25_TYPE=2'b00
	SLAVE26_TYPE=2'b00
	SLAVE27_TYPE=2'b00
	SLAVE28_TYPE=2'b00
	SLAVE29_TYPE=2'b00
	SLAVE30_TYPE=2'b00
	SLAVE31_TYPE=2'b00
	MASTER0_DATA_WIDTH=32'b00000000000000000000001000000000
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	MASTER0_CHAN_RS=1'b1
	MASTER1_CHAN_RS=1'b1
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	MASTER3_CHAN_RS=1'b1
	MASTER4_CHAN_RS=1'b1
	MASTER5_CHAN_RS=1'b1
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	MASTER10_CHAN_RS=1'b1
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	MASTER14_CHAN_RS=1'b1
	MASTER15_CHAN_RS=1'b1
	SLAVE0_CHAN_RS=1'b1
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	SLAVE2_CHAN_RS=1'b1
	SLAVE3_CHAN_RS=1'b1
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	SLAVE5_CHAN_RS=1'b1
	SLAVE6_CHAN_RS=1'b1
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	SLAVE10_CHAN_RS=1'b1
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	SLAVE17_CHAN_RS=1'b1
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	SLAVE19_CHAN_RS=1'b1
	SLAVE20_CHAN_RS=1'b1
	SLAVE21_CHAN_RS=1'b1
	SLAVE22_CHAN_RS=1'b1
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	SLAVE24_CHAN_RS=1'b1
	SLAVE25_CHAN_RS=1'b1
	SLAVE26_CHAN_RS=1'b1
	SLAVE27_CHAN_RS=1'b1
	SLAVE28_CHAN_RS=1'b1
	SLAVE29_CHAN_RS=1'b1
	SLAVE30_CHAN_RS=1'b1
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	SLAVE0_DWC_DATA_FIFO_DEPTH=14'b00000000010000
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	MASTER0_DWC_DATA_FIFO_DEPTH=14'b00000000010000
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	DWC_ADDR_FIFO_DEPTH_CEILING=32'b00000000000000000000000001000000
	MASTER0_READ_INTERLEAVE=1'b0
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	MASTER10_READ_INTERLEAVE=1'b0
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	SLAVE0_READ_INTERLEAVE=1'b0
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	SLAVE5_READ_INTERLEAVE=1'b0
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	SLAVE8_READ_INTERLEAVE=1'b0
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	SLAVE20_READ_INTERLEAVE=1'b0
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	SLAVE22_READ_INTERLEAVE=1'b0
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	SLAVE25_READ_INTERLEAVE=1'b0
	SLAVE26_READ_INTERLEAVE=1'b0
	SLAVE27_READ_INTERLEAVE=1'b0
	SLAVE28_READ_INTERLEAVE=1'b0
	SLAVE29_READ_INTERLEAVE=1'b0
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	NUM_MASTERS_WIDTH=32'b00000000000000000000000000000001
	TGIGEN_DISPLAY_SYMBOL=32'b00000000000000000000000000000001
	UPPER_COMPARE_BIT=32'b00000000000000000000000000100000
	LOWER_COMPARE_BIT=32'b00000000000000000000000000000000
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	SLAVE0_READ_ZERO_SLAVE_ID=1'b1
	SLAVE1_READ_ZERO_SLAVE_ID=1'b1
	SLAVE2_READ_ZERO_SLAVE_ID=1'b1
	SLAVE3_READ_ZERO_SLAVE_ID=1'b1
	SLAVE4_READ_ZERO_SLAVE_ID=1'b1
	SLAVE5_READ_ZERO_SLAVE_ID=1'b1
	SLAVE6_READ_ZERO_SLAVE_ID=1'b1
	SLAVE7_READ_ZERO_SLAVE_ID=1'b1
	SLAVE8_READ_ZERO_SLAVE_ID=1'b1
	SLAVE9_READ_ZERO_SLAVE_ID=1'b1
	SLAVE10_READ_ZERO_SLAVE_ID=1'b1
	SLAVE11_READ_ZERO_SLAVE_ID=1'b1
	SLAVE12_READ_ZERO_SLAVE_ID=1'b1
	SLAVE13_READ_ZERO_SLAVE_ID=1'b1
	SLAVE14_READ_ZERO_SLAVE_ID=1'b1
	SLAVE15_READ_ZERO_SLAVE_ID=1'b1
	SLAVE16_READ_ZERO_SLAVE_ID=1'b1
	SLAVE17_READ_ZERO_SLAVE_ID=1'b1
	SLAVE18_READ_ZERO_SLAVE_ID=1'b1
	SLAVE19_READ_ZERO_SLAVE_ID=1'b1
	SLAVE20_READ_ZERO_SLAVE_ID=1'b1
	SLAVE21_READ_ZERO_SLAVE_ID=1'b1
	SLAVE22_READ_ZERO_SLAVE_ID=1'b1
	SLAVE23_READ_ZERO_SLAVE_ID=1'b1
	SLAVE24_READ_ZERO_SLAVE_ID=1'b1
	SLAVE25_READ_ZERO_SLAVE_ID=1'b1
	SLAVE26_READ_ZERO_SLAVE_ID=1'b1
	SLAVE27_READ_ZERO_SLAVE_ID=1'b1
	SLAVE28_READ_ZERO_SLAVE_ID=1'b1
	SLAVE29_READ_ZERO_SLAVE_ID=1'b1
	SLAVE30_READ_ZERO_SLAVE_ID=1'b1
	SLAVE31_READ_ZERO_SLAVE_ID=1'b1
	SLAVE0_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE1_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE2_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE3_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE4_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE5_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE6_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE7_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE8_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE9_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE10_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE11_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE12_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE13_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE14_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE15_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE16_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE17_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE18_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE19_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE20_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE21_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE22_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE23_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE24_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE25_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE26_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE27_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE28_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE29_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE30_WRITE_ZERO_SLAVE_ID=1'b1
	SLAVE31_WRITE_ZERO_SLAVE_ID=1'b1
	MASTER0_AWCHAN_RS=1'b1
	MASTER1_AWCHAN_RS=1'b1
	MASTER2_AWCHAN_RS=1'b1
	MASTER3_AWCHAN_RS=1'b1
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	SLAVE0_AWCHAN_RS=1'b1
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	SLAVE0_RCHAN_RS=1'b1
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	SLAVE24_RCHAN_RS=1'b1
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	SLAVE30_RCHAN_RS=1'b1
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	SLAVE0_BCHAN_RS=1'b1
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	SLAVE3_BCHAN_RS=1'b1
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	SLAVE5_BCHAN_RS=1'b1
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	SLAVE7_BCHAN_RS=1'b1
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	SLAVE28_BCHAN_RS=1'b1
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	SLAVE30_BCHAN_RS=1'b1
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	MASTER0_DEF_BURST_LEN=8'b00000000
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	AHB_MASTER0_BRESP_CHECK_MODE=2'b00
	AHB_MASTER1_BRESP_CHECK_MODE=2'b00
	AHB_MASTER2_BRESP_CHECK_MODE=2'b00
	AHB_MASTER3_BRESP_CHECK_MODE=2'b00
	AHB_MASTER4_BRESP_CHECK_MODE=2'b00
	AHB_MASTER5_BRESP_CHECK_MODE=2'b00
	AHB_MASTER6_BRESP_CHECK_MODE=2'b00
	AHB_MASTER7_BRESP_CHECK_MODE=2'b00
	AHB_MASTER8_BRESP_CHECK_MODE=2'b00
	AHB_MASTER9_BRESP_CHECK_MODE=2'b00
	AHB_MASTER10_BRESP_CHECK_MODE=2'b00
	AHB_MASTER11_BRESP_CHECK_MODE=2'b00
	AHB_MASTER12_BRESP_CHECK_MODE=2'b00
	AHB_MASTER13_BRESP_CHECK_MODE=2'b00
	AHB_MASTER14_BRESP_CHECK_MODE=2'b00
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	AHB_MASTER0_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER1_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER2_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER3_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER4_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER5_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER6_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER7_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER8_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER9_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER10_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER11_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER12_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER13_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER14_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_MASTER15_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	HI_FREQ=32'b00000000000000000000000000000001
	NUM_SLAVES_WIDTH=32'b00000000000000000000000000000001
	ADDR_WIDTH_BITS=32'b00000000000000000000000000000101
	NUM_THREADS_WIDTH=32'b00000000000000000000000000000010
	OPEN_TRANS_WIDTH=32'b00000000000000000000000000000011
	MASTERID_WIDTH=32'b00000000000000000000000000000101
	BASE_WIDTH=32'b00000000000000000000000000100000
	SLOT_BASE_VEC=32'b00000000000000000000000000000000
	CMPR_WIDTH=32'b00000000000000000000000000100000
	SLOT_MIN_VEC=32'b10000000000000000000000000000000
	SLOT_MAX_VEC=32'b10101111111111111111111111111111
	MASTER_TYPE=2'b00
	SLAVE_TYPE=2'b00
	SLAVE_READ_ZERO_SLAVE_ID=1'b1
	SLAVE_WRITE_ZERO_SLAVE_ID=1'b1
	MASTER_AWCHAN_RS=1'b1
	MASTER_ARCHAN_RS=1'b1
	MASTER_WCHAN_RS=1'b1
	MASTER_RCHAN_RS=1'b1
	MASTER_BCHAN_RS=1'b1
	SLAVE_AWCHAN_RS=1'b1
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	SLAVE_WCHAN_RS=1'b1
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	AHB_MASTER_PORTS_BRESP_CHECK_MODE=2'b00
	AHB_MASTER_PORTS_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	MASTER_PORTS_DATA_WIDTH=32'b00000000000000000000001000000000
	SLAVE_PORTS_DATA_WIDTH=32'b00000000000000000000000001000000
	MASTER_DATA_WIDTH_PORT=32'b00000000000000000000010111000000
	MDW0_UPPER=13'b0001000000000
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	SLAVE_DATA_WIDTH_PORT=32'b00000000000000000000011111100000
	SDW0_UPPER=13'b0000001000000
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	SDW30_UPPER=13'b0011110100000
	SDW31_UPPER=13'b0011111100000
	MDW_UPPER_VEC=13'b0001000000000
	MDW_LOWER_VEC=13'b0000000000000
	SDW_UPPER_VEC=13'b0000001000000
	SDW_LOWER_VEC=13'b0000000000000
	MASTER_STRB_WIDTH_PORT=32'b00000000000000000000000010111000
	SLAVE_STRB_WIDTH_PORT=32'b00000000000000000000000011111100
	MASTER0_WRITE_CONNECTIVITY=1'b1
	MASTER1_WRITE_CONNECTIVITY=1'b1
	MASTER2_WRITE_CONNECTIVITY=1'b1
	MASTER3_WRITE_CONNECTIVITY=1'b1
	MASTER4_WRITE_CONNECTIVITY=1'b1
	MASTER5_WRITE_CONNECTIVITY=1'b1
	MASTER6_WRITE_CONNECTIVITY=1'b1
	MASTER7_WRITE_CONNECTIVITY=1'b1
	MASTER8_WRITE_CONNECTIVITY=1'b1
	MASTER9_WRITE_CONNECTIVITY=1'b1
	MASTER10_WRITE_CONNECTIVITY=1'b1
	MASTER11_WRITE_CONNECTIVITY=1'b1
	MASTER12_WRITE_CONNECTIVITY=1'b1
	MASTER13_WRITE_CONNECTIVITY=1'b1
	MASTER14_WRITE_CONNECTIVITY=1'b1
	MASTER15_WRITE_CONNECTIVITY=1'b1
	MASTER0_READ_CONNECTIVITY=1'b1
	MASTER1_READ_CONNECTIVITY=1'b1
	MASTER2_READ_CONNECTIVITY=1'b1
	MASTER3_READ_CONNECTIVITY=1'b1
	MASTER4_READ_CONNECTIVITY=1'b1
	MASTER5_READ_CONNECTIVITY=1'b1
	MASTER6_READ_CONNECTIVITY=1'b1
	MASTER7_READ_CONNECTIVITY=1'b1
	MASTER8_READ_CONNECTIVITY=1'b1
	MASTER9_READ_CONNECTIVITY=1'b1
	MASTER10_READ_CONNECTIVITY=1'b1
	MASTER11_READ_CONNECTIVITY=1'b1
	MASTER12_READ_CONNECTIVITY=1'b1
	MASTER13_READ_CONNECTIVITY=1'b1
	MASTER14_READ_CONNECTIVITY=1'b1
	MASTER15_READ_CONNECTIVITY=1'b1
	MASTER_WRITE_CONNECTIVITY=1'b1
	MASTER_READ_CONNECTIVITY=1'b1
	MASTER_DEF_BURST_LEN=8'b00000000
	SLAVE_DWC_DATA_FIFO_DEPTH=14'b00000000010000
	MASTER_DWC_DATA_FIFO_DEPTH=14'b00000000010000
	S_CDC=1'b0
	M_CDC=1'b0
	MASTER_READ_INTERLEAVE=1'b0
	SLAVE_READ_INTERLEAVE=1'b0
	CROSSBAR_INTERLEAVE=1'b0
   Generated name = COREAXI4INTERCONNECT_Z18_layer0

	AWCHAN=1'b1
	ARCHAN=1'b1
	RCHAN=1'b1
	WCHAN=1'b1
	BCHAN=1'b1
	ID_WIDTH=32'b00000000000000000000000000000100
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	SUPPORT_USER_SIGNALS=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
   Generated name = caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s

	CHAN_WIDTH=32'b00000000000000000000000001000011
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_67s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_67s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_67s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000001001000
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_72s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_72s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_72s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000001001110
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_78s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_78s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_78s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000000000111
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_7s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_7s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_7s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s .......
Finished optimization stage 1 on caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	MASTER_TYPE=2'b00
	MASTER_NUMBER=32'b00000000000000000000000000000000
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	ID_WIDTH=32'b00000000000000000000000000000100
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	MASTER_DATA_WIDTH=32'b00000000000000000000001000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	DWC_ADDR_FIFO_DEPTH_CEILING=32'b00000000000000000000000001000000
	DATA_FIFO_DEPTH=14'b00000000010000
	READ_INTERLEAVE=1'b0
	NUM_THREADS=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_MstrDataWidthConv_Z19_layer0

	FIFO_SIZE=32'b00000000000000000000000001000000
	NEARLY_FULL=32'b00000000000000000000000000111111
	NEARLY_EMPTY=32'b00000000000000000000000010000000
	ADDRESS_WIDTH=32'b00000000000000000000000000000110
	fmax=32'b00000000000000000000000001000000
	fdiff=32'b00000000000000000000000000000000
   Generated name = caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s
Running optimization stage 1 on caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s .......
Finished optimization stage 1 on caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	MEM_DEPTH=32'b00000000000000000000000001000000
	DATA_WIDTH_IN=32'b00000000000000000000000000101001
	DATA_WIDTH_OUT=32'b00000000000000000000000000101001
	NEARLY_FULL_THRESH=32'b00000000000000000000000000111111
	NEARLY_EMPTY_THRESH=32'b00000000000000000000000010000000
	FIFO_SIZE=32'b00000000000000000000000001000000
	FIFO_ADDR_WIDTH=32'b00000000000000000000000000000110
	NEARLY_EMPTY=32'b00000000000000000000000010000000
	NEARLY_FULL=32'b00000000000000000000000000111111
   Generated name = caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s

	MEM_DEPTH=32'b00000000000000000000000001000000
	ADDR_WIDTH=32'b00000000000000000000000000000110
	DATA_WIDTH=32'b00000000000000000000000000101001
	MASTER_BCHAN=32'b00000000000000000000000000000000
   Generated name = caxi4interconnect_RAM_BLOCK_64s_6s_41s_0s
Running optimization stage 1 on caxi4interconnect_RAM_BLOCK_64s_6s_41s_0s .......
@N:CL134 : RAM_BLOCK.v(65) | Found RAM mem, depth=64, width=41
Finished optimization stage 1 on caxi4interconnect_RAM_BLOCK_64s_6s_41s_0s (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s .......
Finished optimization stage 1 on caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_Hold_Reg_Ctrl .......
Finished optimization stage 1 on caxi4interconnect_Hold_Reg_Ctrl (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	ID_WIDTH=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_DWC_DownConv_Hold_Reg_Wr_41s_4s
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_Hold_Reg_Wr_41s_4s .......
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_Hold_Reg_Wr_41s_4s (CPU Time 0h:00m:00s, Memory Used current: 178MB peak: 204MB)

	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	USER_WIDTH=32'b00000000000000000000000000000001
	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	STRB_WIDTH_IN=32'b00000000000000000000000001000000
	STRB_WIDTH_OUT=32'b00000000000000000000000000001000
	ID_WIDTH=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s
@W:CG133 : DWC_DownConv_widthConvwr.v(142) | Object WVLID_FIXED_BURST_CTRL is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s .......
@W:CL207 : DWC_DownConv_widthConvwr.v(396) | All reachable assignments to cnt_plus_1_eq_0 assign 0, register removed by optimization.
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)

	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	USER_WIDTH=32'b00000000000000000000000000000001
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	READ_INTERLEAVE=1'b0
	TOTAL_IDS=32'b00000000000000000000000000010000
	SEND_TRANS=1'b0
	WAIT_AVALID=1'b1
   Generated name = caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_16s_0_1
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_16s_0_1 .......
@W:CL207 : DWC_DownConv_CmdFifoWriteCtrl.v(627) | All reachable assignments to SLAVE_AID[3:0] assign 0, register removed by optimization.
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_16s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)

	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	WRITE_ENABLE=1'b1
	MASTER_MAX_SIZE=32'b00000000000000000000000000000110
	MASTER_SIZE_MAX_MASK=32'b00000000000000000000000000111111
	MAX_SIZE=32'b00000000000000000000000000000111
   Generated name = caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_1_6s_63s_7s
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_1_6s_63s_7s .......
@A:CL282 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Feedback mux created for signal unaligned_fixed_len_iter_pre[6:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Feedback mux created for signal fixed_burst_pre. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Optimizing register bit ASIZE_pre[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Pruning register bit 2 of ASIZE_pre[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_1_6s_63s_7s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)

	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	ADDR_FIFO_DEPTH=32'b00000000000000000000000001000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	USER_WIDTH=32'b00000000000000000000000000000001
	STRB_WIDTH_IN=32'b00000000000000000000000001000000
	STRB_WIDTH_OUT=32'b00000000000000000000000000001000
	READ_INTERLEAVE=1'b0
	TOTAL_IDS=32'b00000000000000000000000000000001
   Generated name = caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0

	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_DWC_brespCtrl_1s_4s
Running optimization stage 1 on caxi4interconnect_DWC_brespCtrl_1s_4s .......
Finished optimization stage 1 on caxi4interconnect_DWC_brespCtrl_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)

	MEM_DEPTH=32'b00000000000000000000000001000000
	DATA_WIDTH_IN=32'b00000000000000000000000000000101
	DATA_WIDTH_OUT=32'b00000000000000000000000000000101
	NEARLY_FULL_THRESH=32'b00000000000000000000000000111111
	NEARLY_EMPTY_THRESH=32'b00000000000000000000000010000000
	FIFO_SIZE=32'b00000000000000000000000001000000
	FIFO_ADDR_WIDTH=32'b00000000000000000000000000000110
	NEARLY_EMPTY=32'b00000000000000000000000010000000
	NEARLY_FULL=32'b00000000000000000000000000111111
   Generated name = caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s

	MEM_DEPTH=32'b00000000000000000000000001000000
	ADDR_WIDTH=32'b00000000000000000000000000000110
	DATA_WIDTH=32'b00000000000000000000000000000101
	MASTER_BCHAN=32'b00000000000000000000000000000000
   Generated name = caxi4interconnect_RAM_BLOCK_64s_6s_5s_0s
Running optimization stage 1 on caxi4interconnect_RAM_BLOCK_64s_6s_5s_0s .......
@N:CL134 : RAM_BLOCK.v(65) | Found RAM mem, depth=64, width=5
Finished optimization stage 1 on caxi4interconnect_RAM_BLOCK_64s_6s_5s_0s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s .......
Finished optimization stage 1 on caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)
@W:CG360 : DWC_DownConv_writeWidthConv.v(161) | Removing wire brespFifoEmpty_temp, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(165) | Removing wire brespFifowe, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(178) | Removing wire tot_len_M_to_boundary_conv_pre, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(179) | Removing wire to_boundary_conv_M1_pre, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(183) | Removing wire tot_len_GT_max_length_comb_pre, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(184) | Removing wire tot_len_M_max_length_comb_pre, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(185) | Removing wire tot_axi_len_pre, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(192) | Removing wire MASTER_AWVALID_reg, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(193) | Removing wire from_ctrl_MASTER_READY, as there is no assignment to it.
@W:CG360 : DWC_DownConv_writeWidthConv.v(194) | Removing wire to_ctrl_MASTER_AWVALID, as there is no assignment to it.
@W:CG133 : DWC_DownConv_writeWidthConv.v(318) | Object id_range is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0 .......
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0 (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 204MB)

	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	USER_WIDTH=32'b00000000000000000000000000000001
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	READ_INTERLEAVE=1'b0
	TOTAL_IDS=32'b00000000000000000000000000000001
	SEND_TRANS=1'b0
	WAIT_AVALID=1'b1
   Generated name = caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_1s_0_1
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_1s_0_1 .......
@W:CL207 : DWC_DownConv_CmdFifoWriteCtrl.v(627) | All reachable assignments to SLAVE_AID[3:0] assign 0, register removed by optimization.
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_1s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 185MB peak: 204MB)

	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	WRITE_ENABLE=1'b0
	MASTER_MAX_SIZE=32'b00000000000000000000000000000110
	MASTER_SIZE_MAX_MASK=32'b00000000000000000000000000111111
	MAX_SIZE=32'b00000000000000000000000000000111
   Generated name = caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_0_6s_63s_7s
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_0_6s_63s_7s .......
@A:CL282 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Feedback mux created for signal unaligned_fixed_len_iter_pre[6:0]. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Feedback mux created for signal fixed_burst_pre. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@W:CL190 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Optimizing register bit ASIZE_pre[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Pruning register bit 2 of ASIZE_pre[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_0_6s_63s_7s (CPU Time 0h:00m:00s, Memory Used current: 185MB peak: 204MB)

	DATA_WIDTH_IN=32'b00000000000000000000000001000000
	ADDR_FIFO_DEPTH=32'b00000000000000000000000001000000
	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	DATA_WIDTH_OUT=32'b00000000000000000000001000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	USER_WIDTH=32'b00000000000000000000000000000001
	READ_INTERLEAVE=1'b0
	TOTAL_IDS=32'b00000000000000000000000000000001
   Generated name = caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s

	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	ID_WIDTH=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_DWC_DownConv_Hold_Reg_Rd_41s_4s
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_Hold_Reg_Rd_41s_4s .......
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_Hold_Reg_Rd_41s_4s (CPU Time 0h:00m:00s, Memory Used current: 185MB peak: 204MB)

	CMD_FIFO_DATA_WIDTH=32'b00000000000000000000000000101001
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
	DATA_WIDTH_IN=32'b00000000000000000000000001000000
	DATA_WIDTH_OUT=32'b00000000000000000000001000000000
	READ_INTERLEAVE=32'b00000000000000000000000000000001
   Generated name = caxi4interconnect_DWC_DownConv_widthConvrd_41s_1s_4s_64s_512s_1s
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_widthConvrd_41s_1s_4s_64s_512s_1s .......
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_widthConvrd_41s_1s_4s_64s_512s_1s (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

	DATA_WIDTH_IN=32'b00000000000000000000000001000000
	DATA_WIDTH_OUT=32'b00000000000000000000001000000000
   Generated name = caxi4interconnect_byte2bit_64s_512s
Running optimization stage 1 on caxi4interconnect_byte2bit_64s_512s .......
Finished optimization stage 1 on caxi4interconnect_byte2bit_64s_512s (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

Only the first 100 messages of id 'CG360' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CG360' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG360} -count unlimited' in the Tcl shell.
@W:CG133 : DWC_DownConv_readWidthConv.v(181) | Object i is declared but not assigned. Either assign a value or remove the declaration.

Only the first 100 messages of id 'CG133' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CG133' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG133} -count unlimited' in the Tcl shell.
Running optimization stage 1 on caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s .......
Finished optimization stage 1 on caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

	ADDR_FIFO_DEPTH=32'b00000000000000000000000001000000
	DATA_WIDTH_IN=32'b00000000000000000000001000000000
	DATA_WIDTH_OUT=32'b00000000000000000000000001000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	USER_WIDTH=32'b00000000000000000000000000000001
	STRB_WIDTH_IN=32'b00000000000000000000000001000000
	STRB_WIDTH_OUT=32'b00000000000000000000000000001000
	READ_INTERLEAVE=1'b0
   Generated name = caxi4interconnect_DownConverter_64s_512s_64s_32s_4s_1s_64s_8s_0
Running optimization stage 1 on caxi4interconnect_DownConverter_64s_512s_64s_32s_4s_1s_64s_8s_0 .......
Finished optimization stage 1 on caxi4interconnect_DownConverter_64s_512s_64s_32s_4s_1s_64s_8s_0 (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_MstrDataWidthConv_Z19_layer0 .......
Finished optimization stage 1 on caxi4interconnect_MstrDataWidthConv_Z19_layer0 (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000100
	MASTER_DATA_WIDTH=32'b00000000000000000000001000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	CLOCK_DOMAIN_CROSSING=1'b0
	MASTER_TYPE=2'b00
	READ_INTERLEAVE=1'b0
	ADDR_CHAN_WIDTH=32'b00000000000000000000000001000011
	WCHAN_WIDTH=32'b00000000000000000000001001000010
	BCHAN_WIDTH=32'b00000000000000000000000000000111
	RCHAN_WIDTH=32'b00000000000000000000001000001000
	MEM_DEPTH=32'b00000000000000000000000000001000
   Generated name = caxi4interconnect_MstrClockDomainCrossing_Z21_layer0
Running optimization stage 1 on caxi4interconnect_MstrClockDomainCrossing_Z21_layer0 .......
Finished optimization stage 1 on caxi4interconnect_MstrClockDomainCrossing_Z21_layer0 (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

	MASTER_TYPE=2'b00
	MASTER_NUMBER=32'b00000000000000000000000000000000
	AWCHAN_RS=1'b1
	ARCHAN_RS=1'b1
	RCHAN_RS=1'b1
	WCHAN_RS=1'b1
	BCHAN_RS=1'b1
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	ID_WIDTH=32'b00000000000000000000000000000100
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	MASTER_DATA_WIDTH=32'b00000000000000000000001000000000
	DEF_BURST_LEN=8'b00000000
	SUPPORT_USER_SIGNALS=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	DWC_DATA_FIFO_DEPTH=14'b00000000010000
	DWC_ADDR_FIFO_DEPTH_CEILING=32'b00000000000000000000000001000000
	CLOCK_DOMAIN_CROSSING=1'b0
	AHB_BRESP_CNT_WIDTH=32'b00000000000000000000000000001000
	AHB_BRESP_CHECK_MODE=2'b00
	READ_INTERLEAVE=1'b0
	NUM_THREADS=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_MasterConvertor_Z22_layer0

	NUM_MASTERS=32'b00000000000000000000000000000100
	MASTER_NUMBER=32'b00000000000000000000000000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000001000000000
	MASTER_TYPE=2'b00
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s
Running optimization stage 1 on caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s .......
Finished optimization stage 1 on caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_MasterConvertor_Z22_layer0 .......
Finished optimization stage 1 on caxi4interconnect_MasterConvertor_Z22_layer0 (CPU Time 0h:00m:00s, Memory Used current: 186MB peak: 204MB)

	AWCHAN=1'b1
	ARCHAN=1'b1
	RCHAN=1'b1
	WCHAN=1'b1
	BCHAN=1'b1
	ID_WIDTH=32'b00000000000000000000000000000101
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	SUPPORT_USER_SIGNALS=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
   Generated name = caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s

	CHAN_WIDTH=32'b00000000000000000000000001000100
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_68s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_68s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_68s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000001001001
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_73s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_73s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_73s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000001001111
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_79s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_79s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_79s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)

	CHAN_WIDTH=32'b00000000000000000000000000001000
	IDLE=2'b00
	NO_DAT=2'b01
	ONE_DAT=2'b11
	TWO_DAT=2'b10
   Generated name = caxi4interconnect_RegSliceFull_8s_0_1_3_2
Running optimization stage 1 on caxi4interconnect_RegSliceFull_8s_0_1_3_2 .......
Finished optimization stage 1 on caxi4interconnect_RegSliceFull_8s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s .......
Finished optimization stage 1 on caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)

	NUM_SLAVES=32'b00000000000000000000000000000100
	SLAVE_DATA_WIDTH=32'b00000000000000000000000001000000
	SLAVE_NUMBER=32'b00000000000000000000000000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	SLAVE_TYPE=2'b00
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000101
	SLAVE_AWCHAN_RS=4'b1111
	SLAVE_ARCHAN_RS=4'b1111
	SLAVE_WCHAN_RS=4'b1111
	SLAVE_RCHAN_RS=4'b1111
	SLAVE_BCHAN_RS=4'b1111
	DATA_FIFO_DEPTH=14'b00000000010000
	DWC_ADDR_FIFO_DEPTH_CEILING=32'b00000000000000000000000001000000
	READ_INTERLEAVE=1'b0
	NUM_THREADS=32'b00000000000000000000000000000100
   Generated name = caxi4interconnect_SlvDataWidthConverter_Z23_layer0
Running optimization stage 1 on caxi4interconnect_SlvDataWidthConverter_Z23_layer0 .......
Finished optimization stage 1 on caxi4interconnect_SlvDataWidthConverter_Z23_layer0 (CPU Time 0h:00m:00s, Memory Used current: 187MB peak: 204MB)

	NUM_SLAVES=32'b00000000000000000000000000000100
	SLAVE_NUMBER=32'b00000000000000000000000000000000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	SLAVE_TYPE=2'b00
	READ_ZERO_SLAVE_ID=1'b1
	WRITE_ZERO_SLAVE_ID=1'b1
	USER_WIDTH=32'b00000000000000000000000000000001
	ID_WIDTH=32'b00000000000000000000000000000101
	SLV_AXI4PRT_ADDRDEPTH=32'b00000000000000000000000000001000
	SLV_AXI4PRT_DATADEPTH=32'b00000000000000000000000000001001
	MAX_TRANS=32'b00000000000000000000000000100000
	READ_INTERLEAVE=1'b0
   Generated name = caxi4interconnect_SlvProtocolConverter_Z24_layer0

	ZERO_SLAVE_ID=1'b1
	ID_WIDTH=32'b00000000000000000000000000000101
	SLV_AXI4PRT_ADDRDEPTH=32'b00000000000000000000000000001000
	READ_INTERLEAVE=1'b0
   Generated name = caxi4interconnect_SlvAxi4ProtConvAXI4ID_1_5s_8s_0

	FIFO_SIZE=32'b00000000000000000000000100000000
	NEARLY_FULL=32'b00000000000000000000000011111111
	NEARLY_EMPTY=32'b00000000000000000000000000000000
	ADDRESS_WIDTH=32'b00000000000000000000000000001000
	fmax=32'b00000000000000000000000100000000
	fdiff=32'b00000000000000000000000000000000
   Generated name = caxi4interconnect_FIFO_CTRL_256s_255s_0s_8s_256s_0s
Running optimization stage 1 on caxi4interconnect_FIFO_CTRL_256s_255s_0s_8s_256s_0s .......
Finished optimization stage 1 on caxi4interconnect_FIFO_CTRL_256s_255s_0s_8s_256s_0s (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)

	MEM_DEPTH=32'b00000000000000000000000100000000
	DATA_WIDTH_IN=32'b00000000000000000000000000000101
	DATA_WIDTH_OUT=32'b00000000000000000000000000000101
	NEARLY_FULL_THRESH=32'b00000000000000000000000011111111
	NEARLY_EMPTY_THRESH=32'b00000000000000000000000000000000
	FIFO_SIZE=32'b00000000000000000000000100000000
	FIFO_ADDR_WIDTH=32'b00000000000000000000000000001000
	NEARLY_EMPTY=32'b00000000000000000000000000000000
	NEARLY_FULL=32'b00000000000000000000000011111111
   Generated name = caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s

	MEM_DEPTH=32'b00000000000000000000000100000000
	ADDR_WIDTH=32'b00000000000000000000000000001000
	DATA_WIDTH=32'b00000000000000000000000000000101
	MASTER_BCHAN=32'b00000000000000000000000000000000
   Generated name = caxi4interconnect_RAM_BLOCK_256s_8s_5s_0s
Running optimization stage 1 on caxi4interconnect_RAM_BLOCK_256s_8s_5s_0s .......
@N:CL134 : RAM_BLOCK.v(65) | Found RAM mem, depth=256, width=5
Finished optimization stage 1 on caxi4interconnect_RAM_BLOCK_256s_8s_5s_0s (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s .......
Finished optimization stage 1 on caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_SlvAxi4ProtConvAXI4ID_1_5s_8s_0 .......
Finished optimization stage 1 on caxi4interconnect_SlvAxi4ProtConvAXI4ID_1_5s_8s_0 (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)
Running optimization stage 1 on caxi4interconnect_SlvProtocolConverter_Z24_layer0 .......
Finished optimization stage 1 on caxi4interconnect_SlvProtocolConverter_Z24_layer0 (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)

	ADDR_WIDTH=32'b00000000000000000000000000100000
	ID_WIDTH=32'b00000000000000000000000000000101
	SLAVE_DATA_WIDTH=32'b00000000000000000000000001000000
	USER_WIDTH=32'b00000000000000000000000000000001
	CLOCK_DOMAIN_CROSSING=1'b0
	SLAVE_TYPE=2'b00
	READ_INTERLEAVE=1'b0
	ADDR_CHAN_WIDTH=32'b00000000000000000000000001000100
	WCHAN_WIDTH=32'b00000000000000000000000001001010
	BCHAN_WIDTH=32'b00000000000000000000000000001000
	RCHAN_WIDTH=32'b00000000000000000000000001001001
	MEM_DEPTH=32'b00000000000000000000000000001000
   Generated name = caxi4interconnect_SlvClockDomainCrossing_Z25_layer0
Running optimization stage 1 on caxi4interconnect_SlvClockDomainCrossing_Z25_layer0 .......
Finished optimization stage 1 on caxi4interconnect_SlvClockDomainCrossing_Z25_layer0 (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)

	ID_WIDTH=32'b00000000000000000000000000000101
	SLAVE_NUMBER=32'b00000000000000000000000000000000
	AWCHAN_RS=1'b1
	ARCHAN_RS=1'b1
	RCHAN_RS=1'b1
	WCHAN_RS=1'b1
	BCHAN_RS=1'b1
	OPEN_TRANS_MAX=32'b00000000000000000000000000001000
	ADDR_WIDTH=32'b00000000000000000000000000100000
	DATA_WIDTH=32'b00000000000000000000000001000000
	SLAVE_DATA_WIDTH=32'b00000000000000000000000001000000
	SUPPORT_USER_SIGNALS=32'b00000000000000000000000000000000
	USER_WIDTH=32'b00000000000000000000000000000001
	SLAVE_TYPE=2'b00
	READ_ZERO_SLAVE_ID=1'b1
	WRITE_ZERO_SLAVE_ID=1'b1
	SLV_AXI4PRT_ADDRDEPTH=32'b00000000000000000000000000001000
	SLV_AXI4PRT_DATADEPTH=32'b00000000000000000000000000001001
	DWC_DATA_FIFO_DEPTH=14'b00000000010000
	DWC_ADDR_FIFO_DEPTH_CEILING=32'b00000000000000000000000001000000
	CLOCK_DOMAIN_CROSSING=1'b0
	READ_INTERLEAVE=1'b0
	NUM_THREADS=32'b00000000000000000000000000000100
	MAX_TRANS=32'b00000000000000000000000000100000
   Generated name = caxi4interconnect_SlaveConvertor_Z26_layer0
Running optimization stage 1 on caxi4interconnect_SlaveConvertor_Z26_layer0 .......
Finished optimization stage 1 on caxi4interconnect_SlaveConvertor_Z26_layer0 (CPU Time 0h:00m:00s, Memory Used current: 188MB peak: 204MB)
Running optimization stage 1 on COREAXI4INTERCONNECT_Z18_layer0 .......
@W:CL318 : CoreAxi4Interconnect.v(112) | *Output MASTER1_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(126) | *Output MASTER2_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(140) | *Output MASTER3_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(154) | *Output MASTER4_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(168) | *Output MASTER5_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(182) | *Output MASTER6_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(196) | *Output MASTER7_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(210) | *Output MASTER8_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(224) | *Output MASTER9_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(238) | *Output MASTER10_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(252) | *Output MASTER11_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(266) | *Output MASTER12_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(280) | *Output MASTER13_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(294) | *Output MASTER14_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(308) | *Output MASTER15_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(326) | *Output MASTER1_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(334) | *Output MASTER2_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(342) | *Output MASTER3_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(350) | *Output MASTER4_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(358) | *Output MASTER5_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(366) | *Output MASTER6_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(374) | *Output MASTER7_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(382) | *Output MASTER8_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(390) | *Output MASTER9_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(398) | *Output MASTER10_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(406) | *Output MASTER11_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(414) | *Output MASTER12_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(422) | *Output MASTER13_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(430) | *Output MASTER14_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(438) | *Output MASTER15_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(447) | *Output MASTER1_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(448) | *Output MASTER1_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(449) | *Output MASTER1_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(450) | *Output MASTER1_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(453) | *Output MASTER2_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(454) | *Output MASTER2_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(455) | *Output MASTER2_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(456) | *Output MASTER2_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(459) | *Output MASTER3_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(460) | *Output MASTER3_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(461) | *Output MASTER3_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(462) | *Output MASTER3_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(465) | *Output MASTER4_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(466) | *Output MASTER4_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(467) | *Output MASTER4_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(468) | *Output MASTER4_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(471) | *Output MASTER5_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(472) | *Output MASTER5_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(473) | *Output MASTER5_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(474) | *Output MASTER5_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(477) | *Output MASTER6_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(478) | *Output MASTER6_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(479) | *Output MASTER6_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(480) | *Output MASTER6_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(483) | *Output MASTER7_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(484) | *Output MASTER7_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(485) | *Output MASTER7_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(486) | *Output MASTER7_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(489) | *Output MASTER8_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(490) | *Output MASTER8_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(491) | *Output MASTER8_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(492) | *Output MASTER8_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(495) | *Output MASTER9_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(496) | *Output MASTER9_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(497) | *Output MASTER9_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(498) | *Output MASTER9_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(501) | *Output MASTER10_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(502) | *Output MASTER10_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(503) | *Output MASTER10_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W:CL318 : CoreAxi4Interconnect.v(504) | *Output MASTER10_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.

Only the first 100 messages of id 'CL318' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CL318' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL318} -count unlimited' in the Tcl shell.
Finished optimization stage 1 on COREAXI4INTERCONNECT_Z18_layer0 (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on DMA_MASTER .......
Finished optimization stage 1 on DMA_MASTER (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on FIC_BRIDGE .......
Finished optimization stage 1 on FIC_BRIDGE (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on OUTBUF .......
Finished optimization stage 1 on OUTBUF (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on INBUF .......
Finished optimization stage 1 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on INV .......
Finished optimization stage 1 on INV (CPU Time 0h:00m:00s, Memory Used current: 189MB peak: 204MB)
Running optimization stage 1 on OUTBUF_DIFF .......
Finished optimization stage 1 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 190MB peak: 204MB)
Running optimization stage 1 on BIBUF_DIFF .......
Finished optimization stage 1 on BIBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 190MB peak: 204MB)
Running optimization stage 1 on MSS .......
Finished optimization stage 1 on MSS (CPU Time 0h:00m:00s, Memory Used current: 190MB peak: 204MB)
Running optimization stage 1 on MSS_SEV .......
Finished optimization stage 1 on MSS_SEV (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 1 on SEV_PFSoC_OpenVX .......
Finished optimization stage 1 on SEV_PFSoC_OpenVX (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on SEV_PFSoC_OpenVX .......
Finished optimization stage 2 on SEV_PFSoC_OpenVX (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on MSS_SEV .......
Finished optimization stage 2 on MSS_SEV (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on MSS .......
Finished optimization stage 2 on MSS (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on BIBUF_DIFF .......
Finished optimization stage 2 on BIBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on OUTBUF_DIFF .......
Finished optimization stage 2 on OUTBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on INV .......
Finished optimization stage 2 on INV (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on INBUF .......
Finished optimization stage 2 on INBUF (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on OUTBUF .......
Finished optimization stage 2 on OUTBUF (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on FIC_BRIDGE .......
Finished optimization stage 2 on FIC_BRIDGE (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on DMA_MASTER .......
Finished optimization stage 2 on DMA_MASTER (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_SlaveConvertor_Z26_layer0 .......
@N:CL159 : SlaveConvertor.v(63) | Input ARESETN is unused.
Finished optimization stage 2 on caxi4interconnect_SlaveConvertor_Z26_layer0 (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_SlvClockDomainCrossing_Z25_layer0 .......
@N:CL159 : SlvClockDomainCrossing.v(35) | Input SLV_CLK is unused.
@N:CL159 : SlvClockDomainCrossing.v(36) | Input XBAR_CLK is unused.
@N:CL159 : SlvClockDomainCrossing.v(37) | Input sysReset is unused.
@N:CL159 : SlvClockDomainCrossing.v(38) | Input ACLK_syncReset is unused.
Finished optimization stage 2 on caxi4interconnect_SlvClockDomainCrossing_Z25_layer0 (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RAM_BLOCK_256s_8s_5s_0s .......
Finished optimization stage 2 on caxi4interconnect_RAM_BLOCK_256s_8s_5s_0s (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s .......
Finished optimization stage 2 on caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s (CPU Time 0h:00m:00s, Memory Used current: 191MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_FIFO_CTRL_256s_255s_0s_8s_256s_0s .......
Finished optimization stage 2 on caxi4interconnect_FIFO_CTRL_256s_255s_0s_8s_256s_0s (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_SlvAxi4ProtConvAXI4ID_1_5s_8s_0 .......
@N:CL159 : SlvAxi4ProtConvAXI4ID.v(42) | Input SLAVE_ID is unused.
Finished optimization stage 2 on caxi4interconnect_SlvAxi4ProtConvAXI4ID_1_5s_8s_0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_SlvProtocolConverter_Z24_layer0 .......
@N:CL159 : SlvProtocolConverter.v(95) | Input int_slaveWID is unused.
Finished optimization stage 2 on caxi4interconnect_SlvProtocolConverter_Z24_layer0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_SlvDataWidthConverter_Z23_layer0 .......
@N:CL159 : SlvDataWidthConverter.v(53) | Input ACLK is unused.
@N:CL159 : SlvDataWidthConverter.v(54) | Input sysReset is unused.
Finished optimization stage 2 on caxi4interconnect_SlvDataWidthConverter_Z23_layer0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_8s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_8s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_79s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_79s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_73s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_73s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_68s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_68s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s .......
Finished optimization stage 2 on caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s .......
@N:CL159 : MstrProtocolConverter.v(43) | Input ACLK is unused.
@N:CL159 : MstrProtocolConverter.v(44) | Input sysReset is unused.
@N:CL159 : MstrProtocolConverter.v(142) | Input MASTER_WID is unused.
Finished optimization stage 2 on caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_MasterConvertor_Z22_layer0 .......
@N:CL159 : MasterConvertor.v(57) | Input ARESETN is unused.
@N:CL159 : MasterConvertor.v(174) | Input MASTER_HADDR is unused.
@N:CL159 : MasterConvertor.v(175) | Input MASTER_HBURST is unused.
@N:CL159 : MasterConvertor.v(176) | Input MASTER_HMASTLOCK is unused.
@N:CL159 : MasterConvertor.v(177) | Input MASTER_HPROT is unused.
@N:CL159 : MasterConvertor.v(178) | Input MASTER_HSIZE is unused.
@N:CL159 : MasterConvertor.v(179) | Input MASTER_HNONSEC is unused.
@N:CL159 : MasterConvertor.v(180) | Input MASTER_HTRANS is unused.
@N:CL159 : MasterConvertor.v(181) | Input MASTER_HWDATA is unused.
@N:CL159 : MasterConvertor.v(183) | Input MASTER_HWRITE is unused.
@N:CL159 : MasterConvertor.v(186) | Input MASTER_HSEL is unused.
Finished optimization stage 2 on caxi4interconnect_MasterConvertor_Z22_layer0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_MstrClockDomainCrossing_Z21_layer0 .......
@N:CL159 : MstrClockDomainCrossing.v(35) | Input MST_CLK is unused.
@N:CL159 : MstrClockDomainCrossing.v(36) | Input XBAR_CLK is unused.
@N:CL159 : MstrClockDomainCrossing.v(37) | Input sysReset is unused.
@N:CL159 : MstrClockDomainCrossing.v(38) | Input ACLK_syncReset is unused.
Finished optimization stage 2 on caxi4interconnect_MstrClockDomainCrossing_Z21_layer0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_DownConverter_64s_512s_64s_32s_4s_1s_64s_8s_0 .......
Finished optimization stage 2 on caxi4interconnect_DownConverter_64s_512s_64s_32s_4s_1s_64s_8s_0 (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_byte2bit_64s_512s .......
Finished optimization stage 2 on caxi4interconnect_byte2bit_64s_512s (CPU Time 0h:00m:00s, Memory Used current: 193MB peak: 204MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_widthConvrd_41s_1s_4s_64s_512s_1s .......
@W:CL246 : DWC_DownConv_widthConvrd.v(83) | Input port bits 39 to 30 of rdCmdFifoReadData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : DWC_DownConv_widthConvrd.v(83) | Input port bits 22 to 8 of rdCmdFifoReadData[40:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_widthConvrd_41s_1s_4s_64s_512s_1s (CPU Time 0h:00m:01s, Memory Used current: 199MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_Hold_Reg_Rd_41s_4s .......
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_Hold_Reg_Rd_41s_4s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s .......
@N:CL159 : DWC_DownConv_readWidthConv.v(103) | Input SLAVE_RID is unused.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_0_6s_63s_7s .......
@W:CL279 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Pruning register bits 5 to 4 of mask_addr_pre[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_0_6s_63s_7s (CPU Time 0h:00m:00s, Memory Used current: 199MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_1s_0_1 .......
@W:CL246 : DWC_DownConv_CmdFifoWriteCtrl.v(87) | Input port bits 31 to 6 of MASTER_AADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_1s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_RAM_BLOCK_64s_6s_5s_0s .......
Finished optimization stage 2 on caxi4interconnect_RAM_BLOCK_64s_6s_5s_0s (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s .......
Finished optimization stage 2 on caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_brespCtrl_1s_4s .......
Finished optimization stage 2 on caxi4interconnect_DWC_brespCtrl_1s_4s (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0 .......
@N:CL159 : DWC_DownConv_writeWidthConv.v(104) | Input SLAVE_BID is unused.
@N:CL159 : DWC_DownConv_writeWidthConv.v(138) | Input MASTER_WLAST is unused.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0 (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_1_6s_63s_7s .......
@W:CL279 : DWC_DownConv_preCalcCmdFifoWrCtrl.v(126) | Pruning register bits 5 to 4 of mask_addr_pre[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_preCalcCmdFifoWrCtrl_64s_512s_32s_1s_4s_1_6s_63s_7s (CPU Time 0h:00m:00s, Memory Used current: 207MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_16s_0_1 .......
@W:CL246 : DWC_DownConv_CmdFifoWriteCtrl.v(87) | Input port bits 31 to 6 of MASTER_AADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_CmdFifoWriteCtrl_32s_4s_1s_512s_64s_41s_0_16s_0_1 (CPU Time 0h:00m:00s, Memory Used current: 206MB peak: 281MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s .......
@W:CL246 : DWC_DownConv_widthConvwr.v(71) | Input port bits 39 to 30 of wrCmdFifoRdData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : DWC_DownConv_widthConvwr.v(71) | Input port bits 10 to 8 of wrCmdFifoRdData[40:0] are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s (CPU Time 0h:00m:03s, Memory Used current: 252MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_DWC_DownConv_Hold_Reg_Wr_41s_4s .......
Finished optimization stage 2 on caxi4interconnect_DWC_DownConv_Hold_Reg_Wr_41s_4s (CPU Time 0h:00m:00s, Memory Used current: 252MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_Hold_Reg_Ctrl .......
Finished optimization stage 2 on caxi4interconnect_Hold_Reg_Ctrl (CPU Time 0h:00m:00s, Memory Used current: 252MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RAM_BLOCK_64s_6s_41s_0s .......
Finished optimization stage 2 on caxi4interconnect_RAM_BLOCK_64s_6s_41s_0s (CPU Time 0h:00m:00s, Memory Used current: 252MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s .......
Finished optimization stage 2 on caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s (CPU Time 0h:00m:00s, Memory Used current: 252MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s .......
Finished optimization stage 2 on caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_MstrDataWidthConv_Z19_layer0 .......
Finished optimization stage 2 on caxi4interconnect_MstrDataWidthConv_Z19_layer0 (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_7s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_7s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_78s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_78s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_72s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_72s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RegSliceFull_67s_0_1_3_2 .......
@N:CL201 : RegSliceFull.v(185) | Trying to extract state machine for register currState.
Extracted state machine for register currState
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on caxi4interconnect_RegSliceFull_67s_0_1_3_2 (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s .......
Finished optimization stage 2 on caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s (CPU Time 0h:00m:00s, Memory Used current: 253MB peak: 290MB)
Running optimization stage 2 on COREAXI4INTERCONNECT_Z18_layer0 .......
@N:CL159 : CoreAxi4Interconnect.v(33) | Input M_CLK0 is unused.
@N:CL159 : CoreAxi4Interconnect.v(34) | Input M_CLK1 is unused.
@N:CL159 : CoreAxi4Interconnect.v(35) | Input M_CLK2 is unused.
@N:CL159 : CoreAxi4Interconnect.v(36) | Input M_CLK3 is unused.
@N:CL159 : CoreAxi4Interconnect.v(37) | Input M_CLK4 is unused.
@N:CL159 : CoreAxi4Interconnect.v(38) | Input M_CLK5 is unused.
@N:CL159 : CoreAxi4Interconnect.v(39) | Input M_CLK6 is unused.
@N:CL159 : CoreAxi4Interconnect.v(40) | Input M_CLK7 is unused.
@N:CL159 : CoreAxi4Interconnect.v(41) | Input M_CLK8 is unused.
@N:CL159 : CoreAxi4Interconnect.v(42) | Input M_CLK9 is unused.
@N:CL159 : CoreAxi4Interconnect.v(43) | Input M_CLK10 is unused.
@N:CL159 : CoreAxi4Interconnect.v(44) | Input M_CLK11 is unused.
@N:CL159 : CoreAxi4Interconnect.v(45) | Input M_CLK12 is unused.
@N:CL159 : CoreAxi4Interconnect.v(46) | Input M_CLK13 is unused.
@N:CL159 : CoreAxi4Interconnect.v(47) | Input M_CLK14 is unused.
@N:CL159 : CoreAxi4Interconnect.v(48) | Input M_CLK15 is unused.
@N:CL159 : CoreAxi4Interconnect.v(50) | Input S_CLK0 is unused.
@N:CL159 : CoreAxi4Interconnect.v(51) | Input S_CLK1 is unused.
@N:CL159 : CoreAxi4Interconnect.v(52) | Input S_CLK2 is unused.
@N:CL159 : CoreAxi4Interconnect.v(53) | Input S_CLK3 is unused.
@N:CL159 : CoreAxi4Interconnect.v(54) | Input S_CLK4 is unused.
@N:CL159 : CoreAxi4Interconnect.v(55) | Input S_CLK5 is unused.
@N:CL159 : CoreAxi4Interconnect.v(56) | Input S_CLK6 is unused.
@N:CL159 : CoreAxi4Interconnect.v(57) | Input S_CLK7 is unused.
@N:CL159 : CoreAxi4Interconnect.v(60) | Input S_CLK8 is unused.
@N:CL159 : CoreAxi4Interconnect.v(61) | Input S_CLK9 is unused.
@N:CL159 : CoreAxi4Interconnect.v(62) | Input S_CLK10 is unused.
@N:CL159 : CoreAxi4Interconnect.v(63) | Input S_CLK11 is unused.
@N:CL159 : CoreAxi4Interconnect.v(64) | Input S_CLK12 is unused.
@N:CL159 : CoreAxi4Interconnect.v(65) | Input S_CLK13 is unused.
@N:CL159 : CoreAxi4Interconnect.v(66) | Input S_CLK14 is unused.
@N:CL159 : CoreAxi4Interconnect.v(67) | Input S_CLK15 is unused.
@N:CL159 : CoreAxi4Interconnect.v(68) | Input S_CLK16 is unused.
@N:CL159 : CoreAxi4Interconnect.v(69) | Input S_CLK17 is unused.
@N:CL159 : CoreAxi4Interconnect.v(70) | Input S_CLK18 is unused.
@N:CL159 : CoreAxi4Interconnect.v(71) | Input S_CLK19 is unused.
@N:CL159 : CoreAxi4Interconnect.v(72) | Input S_CLK20 is unused.
@N:CL159 : CoreAxi4Interconnect.v(73) | Input S_CLK21 is unused.
@N:CL159 : CoreAxi4Interconnect.v(74) | Input S_CLK22 is unused.
@N:CL159 : CoreAxi4Interconnect.v(75) | Input S_CLK23 is unused.
@N:CL159 : CoreAxi4Interconnect.v(76) | Input S_CLK24 is unused.
@N:CL159 : CoreAxi4Interconnect.v(77) | Input S_CLK25 is unused.
@N:CL159 : CoreAxi4Interconnect.v(78) | Input S_CLK26 is unused.
@N:CL159 : CoreAxi4Interconnect.v(79) | Input S_CLK27 is unused.
@N:CL159 : CoreAxi4Interconnect.v(80) | Input S_CLK28 is unused.
@N:CL159 : CoreAxi4Interconnect.v(81) | Input S_CLK29 is unused.
@N:CL159 : CoreAxi4Interconnect.v(82) | Input S_CLK30 is unused.
@N:CL159 : CoreAxi4Interconnect.v(83) | Input S_CLK31 is unused.
@N:CL159 : CoreAxi4Interconnect.v(100) | Input MASTER1_AWID is unused.
@N:CL159 : CoreAxi4Interconnect.v(101) | Input MASTER1_AWADDR is unused.
@N:CL159 : CoreAxi4Interconnect.v(102) | Input MASTER1_AWLEN is unused.
@N:CL159 : CoreAxi4Interconnect.v(103) | Input MASTER1_AWSIZE is unused.
@N:CL159 : CoreAxi4Interconnect.v(104) | Input MASTER1_AWBURST is unused.
@N:CL159 : CoreAxi4Interconnect.v(105) | Input MASTER1_AWLOCK is unused.
@N:CL159 : CoreAxi4Interconnect.v(106) | Input MASTER1_AWCACHE is unused.
@N:CL159 : CoreAxi4Interconnect.v(107) | Input MASTER1_AWPROT is unused.
@N:CL159 : CoreAxi4Interconnect.v(108) | Input MASTER1_AWREGION is unused.
@N:CL159 : CoreAxi4Interconnect.v(109) | Input MASTER1_AWQOS is unused.
@N:CL159 : CoreAxi4Interconnect.v(110) | Input MASTER1_AWUSER is unused.
@N:CL159 : CoreAxi4Interconnect.v(111) | Input MASTER1_AWVALID is unused.
@N:CL159 : CoreAxi4Interconnect.v(114) | Input MASTER2_AWID is unused.
@N:CL159 : CoreAxi4Interconnect.v(115) | Input MASTER2_AWADDR is unused.
@N:CL159 : CoreAxi4Interconnect.v(116) | Input MASTER2_AWLEN is unused.
@N:CL159 : CoreAxi4Interconnect.v(117) | Input MASTER2_AWSIZE is unused.
@N:CL159 : CoreAxi4Interconnect.v(118) | Input MASTER2_AWBURST is unused.
@N:CL159 : CoreAxi4Interconnect.v(119) | Input MASTER2_AWLOCK is unused.
@N:CL159 : CoreAxi4Interconnect.v(120) | Input MASTER2_AWCACHE is unused.
@N:CL159 : CoreAxi4Interconnect.v(121) | Input MASTER2_AWPROT is unused.
@N:CL159 : CoreAxi4Interconnect.v(122) | Input MASTER2_AWREGION is unused.
@N:CL159 : CoreAxi4Interconnect.v(123) | Input MASTER2_AWQOS is unused.

Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell.
Finished optimization stage 2 on COREAXI4INTERCONNECT_Z18_layer0 (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_Axi4CrossBar_Z17_layer0 .......
@W:CL247 : Axi4CrossBar.v(166) | Input port bit 4 of SLAVE_BID[4:0] is unused

@W:CL247 : Axi4CrossBar.v(188) | Input port bit 4 of SLAVE_RID[4:0] is unused

Finished optimization stage 2 on caxi4interconnect_Axi4CrossBar_Z17_layer0 (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on caxi4interconnect_ResetSycnc .......
Finished optimization stage 2 on caxi4interconnect_ResetSycnc (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on DDR4_RD_WR .......
Finished optimization stage 2 on DDR4_RD_WR (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on video_processing .......
Finished optimization stage 2 on video_processing (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on Video_arbiter_top_LPDDR4 .......
Finished optimization stage 2 on Video_arbiter_top_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on write_top .......
Finished optimization stage 2 on write_top (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on read_top .......
Finished optimization stage 2 on read_top (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on DFN1 .......
Finished optimization stage 2 on DFN1 (CPU Time 0h:00m:00s, Memory Used current: 256MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_lpddr4_Z16_layer0 .......
@N:CL201 : ddr_rw_arbiter_lpddr4.v(400) | Trying to extract state machine for register video_bus_state.
Extracted state machine for register video_bus_state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   101
   110
@N:CL201 : ddr_rw_arbiter_lpddr4.v(303) | Trying to extract state machine for register local_wbus_state.
Extracted state machine for register local_wbus_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on ddr_rw_arbiter_lpddr4_Z16_layer0 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_16s_16s_3_3 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_16s_16s_3_3 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z15_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z15_layer0 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z14_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z14_layer0 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z13_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z13_layer0 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on RAM1K20 .......
Finished optimization stage 2 on RAM1K20 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_512s_512s_8_8 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_LSRAM_top_512s_512s_8_8 (CPU Time 0h:00m:00s, Memory Used current: 257MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z12_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_fwft_Z12_layer0 (CPU Time 0h:00m:00s, Memory Used current: 250MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z11_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_corefifo_sync_scntr_Z11_layer0 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0 .......
Finished optimization stage 2 on ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_XCVR_ERM_C0 .......
Finished optimization stage 2 on PF_XCVR_ERM_C0 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_XCVR_ERM_C0_I_XCVR_PF_XCVR .......
Finished optimization stage 2 on PF_XCVR_ERM_C0_I_XCVR_PF_XCVR (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on XCVR_PMA .......
Finished optimization stage 2 on XCVR_PMA (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on RCLKINT .......
Finished optimization stage 2 on RCLKINT (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on IMX334_IF_TOP .......
Finished optimization stage 2 on IMX334_IF_TOP (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on CAM_IOD_TIP_TOP .......
Finished optimization stage 2 on CAM_IOD_TIP_TOP (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0 .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on SLE .......
Finished optimization stage 2 on SLE (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_3 .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_3 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on LANECTRL .......
Finished optimization stage 2 on LANECTRL (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on INBUF_DIFF_MIPI .......
Finished optimization stage 2 on INBUF_DIFF_MIPI (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on IOD .......
Finished optimization stage 2 on IOD (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on ICB_CLKDIVDELAY .......
Finished optimization stage 2 on ICB_CLKDIVDELAY (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on MX2 .......
Finished optimization stage 2 on MX2 (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on HS_IO_CLK .......
Finished optimization stage 2 on HS_IO_CLK (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_TR .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_TR (CPU Time 0h:00m:00s, Memory Used current: 251MB peak: 290MB)
Running optimization stage 2 on ICB_BCLKSCLKALIGN_Z9_layer0 .......
@N:CL201 : ICB_BclkSclkAlign.v(214) | Trying to extract state machine for register clkalign_curr_state.
Extracted state machine for register clkalign_curr_state
State machine has 64 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001000
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   010111
   011000
   011001
   011010
   011011
   011100
   011101
   011110
   011111
   100000
   100001
   100010
   100011
   100100
   100101
   100110
   100111
   101000
   101001
   101010
   101011
   101100
   101101
   101110
   101111
   110000
   110001
   110010
   110011
   110100
   110101
   110110
   110111
   111000
   111001
   111010
   111011
   111100
   111101
   111110
   111111
Finished optimization stage 2 on ICB_BCLKSCLKALIGN_Z9_layer0 (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 290MB)
Running optimization stage 2 on PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0 .......
Finished optimization stage 2 on PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0 (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 290MB)
Running optimization stage 2 on INBUF_DIFF .......
Finished optimization stage 2 on INBUF_DIFF (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C3 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C3 (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 258MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0 .......
@N:CL201 : CoreRxIODBitAlign.v(269) | Trying to extract state machine for register bitalign_curr_state.
Extracted state machine for register bitalign_curr_state
State machine has 30 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11110
Finished optimization stage 2 on CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0 (CPU Time 0h:00m:01s, Memory Used current: 272MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C2 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C2 (CPU Time 0h:00m:00s, Memory Used current: 272MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 272MB peak: 290MB)
Running optimization stage 2 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0 .......
@N:CL201 : CoreRxIODBitAlign.v(269) | Trying to extract state machine for register bitalign_curr_state.
Extracted state machine for register bitalign_curr_state
State machine has 30 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11110
Finished optimization stage 2 on CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0 (CPU Time 0h:00m:01s, Memory Used current: 272MB peak: 295MB)
Running optimization stage 2 on CORERXIODBITALIGN_C1 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C1 (CPU Time 0h:00m:00s, Memory Used current: 272MB peak: 295MB)
Running optimization stage 2 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 272MB peak: 295MB)
Running optimization stage 2 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0 .......
@N:CL201 : CoreRxIODBitAlign.v(269) | Trying to extract state machine for register bitalign_curr_state.
Extracted state machine for register bitalign_curr_state
State machine has 30 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11110
Finished optimization stage 2 on CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0 (CPU Time 0h:00m:01s, Memory Used current: 274MB peak: 296MB)
Running optimization stage 2 on CORERXIODBITALIGN_C0 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C0 (CPU Time 0h:00m:00s, Memory Used current: 274MB peak: 296MB)
Running optimization stage 2 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 .......
Finished optimization stage 2 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_1s_0s_0s_26s_3s_1s_10s_10s_256_8 (CPU Time 0h:00m:00s, Memory Used current: 274MB peak: 296MB)
Running optimization stage 2 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0 .......
@N:CL201 : CoreRxIODBitAlign.v(269) | Trying to extract state machine for register bitalign_curr_state.
Extracted state machine for register bitalign_curr_state
State machine has 30 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
   10001
   10010
   10011
   10100
   10101
   10110
   10111
   11000
   11001
   11010
   11011
   11100
   11110
Finished optimization stage 2 on CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0 (CPU Time 0h:00m:01s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on AND4 .......
Finished optimization stage 2 on AND4 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C2 .......
Finished optimization stage 2 on PF_CCC_C2 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C2_PF_CCC_C2_0_PF_CCC .......
Finished optimization stage 2 on PF_CCC_C2_PF_CCC_C2_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipicsi2rxdecoderPF_C0 .......
Finished optimization stage 2 on mipicsi2rxdecoderPF_C0 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipicsi2rxdecoderPF_native_10s_4s_1s_0s_12s .......
Finished optimization stage 2 on mipicsi2rxdecoderPF_native_10s_4s_1s_0s_12s (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipi_csi2_rxdecoder_Z3_layer0 .......
@N:CL135 : mipicsi2rxdecoderPF.v(1514) | Found sequential shift data_type_o with address depth of 3 words and data bit width of 6.
@N:CL135 : mipicsi2rxdecoderPF.v(1569) | Found sequential shift word_count_o with address depth of 3 words and data bit width of 16.
@N:CL135 : mipicsi2rxdecoderPF.v(1548) | Found sequential shift ecc_error_o with address depth of 3 words and data bit width of 1.
@N:CL135 : mipicsi2rxdecoderPF.v(1588) | Found sequential shift virtual_channel_o with address depth of 3 words and data bit width of 2.
@W:CL190 : mipicsi2rxdecoderPF.v(1125) | Optimizing register bit genblk2.pixel_count[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : mipicsi2rxdecoderPF.v(1125) | Optimizing register bit genblk2.pixel_count[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : mipicsi2rxdecoderPF.v(1125) | Pruning register bits 1 to 0 of genblk2.pixel_count[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : mipicsi2rxdecoderPF.v(1125) | Trying to extract state machine for register genblk2.state_FS.
Extracted state machine for register genblk2.state_FS
State machine has 6 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
Finished optimization stage 2 on mipi_csi2_rxdecoder_Z3_layer0 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on byte2pixel_conversion_Z2_layer0 .......
@W:CL177 : mipicsi2rxdecoderPF.v(6309) | Sharing sequential element pixel_valid and merging line_valid_o. Add a syn_preserve attribute to the element to prevent sharing.
@N:CL201 : mipicsi2rxdecoderPF.v(6133) | Trying to extract state machine for register genblk7.pix_distribute_4lane.
Extracted state machine for register genblk7.pix_distribute_4lane
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
Finished optimization stage 2 on byte2pixel_conversion_Z2_layer0 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3 .......
Finished optimization stage 2 on mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipi_csi2_rx_cdcfiforam_12_40 .......
Finished optimization stage 2 on mipi_csi2_rx_cdcfiforam_12_40 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3 .......
Finished optimization stage 2 on mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on mipi_csi2_rx_cdcfiforam_8_8 .......
Finished optimization stage 2 on mipi_csi2_rx_cdcfiforam_8_8 (CPU Time 0h:00m:00s, Memory Used current: 273MB peak: 296MB)
Running optimization stage 2 on embsync_detect_Z1_layer0 .......
@N:CL135 : mipicsi2rxdecoderPF.v(1949) | Found sequential shift genblk1.L0_data_in_reg5 with address depth of 3 words and data bit width of 8.
@N:CL135 : mipicsi2rxdecoderPF.v(2982) | Found sequential shift genblk2.L1_data_in_reg5 with address depth of 3 words and data bit width of 8.
@N:CL135 : mipicsi2rxdecoderPF.v(3146) | Found sequential shift genblk3.L2_data_in_reg5 with address depth of 3 words and data bit width of 8.
@N:CL135 : mipicsi2rxdecoderPF.v(3311) | Found sequential shift genblk4.L3_data_in_reg5 with address depth of 3 words and data bit width of 8.
@W:CL190 : mipicsi2rxdecoderPF.v(1986) | Optimizing register bit genblk1.word_counter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : mipicsi2rxdecoderPF.v(1986) | Optimizing register bit genblk1.word_counter[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : mipicsi2rxdecoderPF.v(1986) | Pruning register bits 1 to 0 of genblk1.word_counter[16:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : mipicsi2rxdecoderPF.v(2557) | Trying to extract state machine for register genblk1.state_3.
Extracted state machine for register genblk1.state_3
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : mipicsi2rxdecoderPF.v(2496) | Trying to extract state machine for register genblk1.state_2.
Extracted state machine for register genblk1.state_2
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : mipicsi2rxdecoderPF.v(2435) | Trying to extract state machine for register genblk1.state_1.
Extracted state machine for register genblk1.state_1
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : mipicsi2rxdecoderPF.v(2374) | Trying to extract state machine for register genblk1.state_0.
Extracted state machine for register genblk1.state_0
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : mipicsi2rxdecoderPF.v(1986) | Trying to extract state machine for register genblk1.state_enb.
Extracted state machine for register genblk1.state_enb
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   100
Finished optimization stage 2 on embsync_detect_Z1_layer0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s .......
Finished optimization stage 2 on mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C2 .......
Finished optimization stage 2 on CORERESET_PF_C2 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C2_CORERESET_PF_C2_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on CORERESET_PF_C2_CORERESET_PF_C2_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C1 .......
Finished optimization stage 2 on CORERESET_PF_C1 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C1_CORERESET_PF_C1_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on CORERESET_PF_C1_CORERESET_PF_C1_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on DDR_Write_LPDDR4 .......
Finished optimization stage 2 on DDR_Write_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on DDR_Read_LPDDR4 .......
Finished optimization stage 2 on DDR_Read_LPDDR4 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C0 .......
Finished optimization stage 2 on CORERESET_PF_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C0_CORERESET_PF_C0_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on CORERESET_PF_C0_CORERESET_PF_C0_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CLOCKS_AND_RESETS .......
Finished optimization stage 2 on CLOCKS_AND_RESETS (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_XCVR_REF_CLK_C0 .......
Finished optimization stage 2 on PF_XCVR_REF_CLK_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK .......
Finished optimization stage 2 on PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on XCVR_REF_CLK .......
Finished optimization stage 2 on XCVR_REF_CLK (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_TX_PLL_C0 .......
Finished optimization stage 2 on PF_TX_PLL_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL .......
Finished optimization stage 2 on PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on TX_PLL .......
Finished optimization stage 2 on TX_PLL (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_OSC_C0 .......
Finished optimization stage 2 on PF_OSC_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_OSC_C0_PF_OSC_C0_0_PF_OSC .......
Finished optimization stage 2 on PF_OSC_C0_PF_OSC_C0_0_PF_OSC (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on OSC_RC2MHZ .......
Finished optimization stage 2 on OSC_RC2MHZ (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CLK_DIV_C0 .......
Finished optimization stage 2 on PF_CLK_DIV_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV .......
Finished optimization stage 2 on PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on ICB_CLKDIV .......
Finished optimization stage 2 on ICB_CLKDIV (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C1 .......
Finished optimization stage 2 on PF_CCC_C1 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C1_PF_CCC_C1_0_PF_CCC .......
Finished optimization stage 2 on PF_CCC_C1_PF_CCC_C1_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C0 .......
Finished optimization stage 2 on PF_CCC_C0 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PF_CCC_C0_PF_CCC_C0_0_PF_CCC .......
Finished optimization stage 2 on PF_CCC_C0_PF_CCC_C0_0_PF_CCC (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on PLL .......
Finished optimization stage 2 on PLL (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CLKINT .......
Finished optimization stage 2 on CLKINT (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on INIT_MONITOR .......
Finished optimization stage 2 on INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR .......
Finished optimization stage 2 on INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on GND .......
Finished optimization stage 2 on GND (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on BANKCTRL_HSIO .......
Finished optimization stage 2 on BANKCTRL_HSIO (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on VCC .......
Finished optimization stage 2 on VCC (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on BANKCTRL_GPIO .......
Finished optimization stage 2 on BANKCTRL_GPIO (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on INIT .......
Finished optimization stage 2 on INIT (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C4 .......
Finished optimization stage 2 on CORERESET_PF_C4 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C4_CORERESET_PF_C4_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on CORERESET_PF_C4_CORERESET_PF_C4_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C3 .......
Finished optimization stage 2 on CORERESET_PF_C3 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on CORERESET_PF_C3_CORERESET_PF_C3_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Finished optimization stage 2 on CORERESET_PF_C3_CORERESET_PF_C3_0_CORERESET_PF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on AND3 .......
Finished optimization stage 2 on AND3 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on BIBUF .......
Finished optimization stage 2 on BIBUF (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)
Running optimization stage 2 on AND2 .......
Finished optimization stage 2 on AND2 (CPU Time 0h:00m:00s, Memory Used current: 265MB peak: 296MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer0.rt.csv


At c_ver Exit (Real Time elapsed 0h:00m:59s; CPU Time elapsed 0h:00m:59s; Memory used current: 267MB peak: 296MB)


Process completed successfully.
# Mon Nov 21 15:25:42 2022

###########################################################]
###########################################################[
@N: : data_unpacker_FHD_RX_0.vhd(25) | Top entity is set to data_unpacker_FHD_RX.
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\register_config.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\ram2port.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\data_packer_lpddr4.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\synchronizer_circuit.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\read_demux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\read_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\request_scheduler.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\write_demux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\write_mux.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\YCbCrtoRGB\4.4.0\Encrypted\YCbCrtoRGB.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\RGBtoYCbCr\4.4.0\Encrypted\RGBtoYCbCr.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\apb3_interface.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\intensity_average.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Display_Controller_C0\Display_Controller_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\HDMI_TX_C0\HDMI_TX_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\YCbCrtoRGB_C0\YCbCrtoRGB_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Bayer_Interpolation_C0\Bayer_Interpolation_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Gamma_Correction_C0\Gamma_Correction_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\Image_Enhancement_C0\Image_Enhancement_C0.vhd'. 
@N:CD140 :  | Using the VHDL 2008 Standard for file 'D:\Delme\SEV_PFSoC_OpenVX\component\work\RGBtoYCbCr_C0\RGBtoYCbCr_C0.vhd'. 
VHDL syntax check successful!
@N:CD231 : std1164.vhd(889) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000".
@N:CD630 : YCbCrtoRGB_C0.vhd(31) | Synthesizing work.ycbcrtorgb_c0.rtl.
Post processing for work.ycbcr2rgb.rtl
Running optimization stage 1 on YCbCr2RGB .......
Finished optimization stage 1 on YCbCr2RGB (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 106MB)
Post processing for work.ycbcr_422to444.rtl
Running optimization stage 1 on YCbCr_422to444 .......
Finished optimization stage 1 on YCbCr_422to444 (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 106MB)
Post processing for work.ycbcrtorgb.rtl
Running optimization stage 1 on YCbCrtoRGB .......
Finished optimization stage 1 on YCbCrtoRGB (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 106MB)
Post processing for work.ycbcrtorgb_c0.rtl
Running optimization stage 1 on YCbCrtoRGB_C0 .......
Finished optimization stage 1 on YCbCrtoRGB_C0 (CPU Time 0h:00m:00s, Memory Used current: 105MB peak: 106MB)
@N:CD630 : HDMI_TX_C0.vhd(29) | Synthesizing work.hdmi_tx_c0.rtl.
@W:CD729 : HDMI_TX_C0.vhd(130) | Component declaration has 3 generics but entity declares only 2 generics
@N:CD630 : HDMI_TX.vhd(24) | Synthesizing work.hdmi_tx.rtl.
@W:CD638 : HDMI_TX.vhd(135) | Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : HDMI_TX.vhd(136) | Signal s_vsync_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : HDMI_TX.vhd(137) | Signal s_hsync_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : HDMI_TX.vhd(138) | Signal s_data_o is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : HDMI_TX.vhd(375) | Synthesizing work.hdmi_tx_native.hdmi_tx_native.
@N:CD630 : HDMI_TX.vhd(874) | Synthesizing work.tx_fifo_top.fifo_arch.
@N:CD630 : HDMI_TX.vhd(1032) | Synthesizing work.video_fifo_hdmi_tx.video_fifo_hdmi_tx.
@W:CD638 : HDMI_TX.vhd(1128) | Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : HDMI_TX.vhd(1129) | Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : HDMI_TX.vhd(1453) | Synthesizing work.ram2port_hdmi_tx.ram2port_hdmi_tx.
Post processing for work.ram2port_hdmi_tx.ram2port_hdmi_tx
Running optimization stage 1 on ram2port_hdmi_tx .......
@N:CL134 : HDMI_TX.vhd(1494) | Found RAM ram, depth=64, width=10
Finished optimization stage 1 on ram2port_hdmi_tx (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 106MB)
Post processing for work.video_fifo_hdmi_tx.video_fifo_hdmi_tx
Running optimization stage 1 on video_fifo_hdmi_tx .......
@W:CL265 : HDMI_TX.vhd(1381) | Removing unused bit 6 of wdata_count_2(6 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL265 : HDMI_TX.vhd(1277) | Removing unused bit 6 of rdata_count_2(6 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL260 : HDMI_TX.vhd(1228) | Pruning register bit 6 of rptr(6 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : HDMI_TX.vhd(1328) | Pruning register bit 6 of wptr(6 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on video_fifo_hdmi_tx (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB)
Post processing for work.tx_fifo_top.fifo_arch
Running optimization stage 1 on tx_fifo_top .......
Finished optimization stage 1 on tx_fifo_top (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB)
@N:CD630 : HDMI_TX.vhd(822) | Synthesizing work.synchronizer_hdmi_tx.behaviour.
Post processing for work.synchronizer_hdmi_tx.behaviour
Running optimization stage 1 on synchronizer_hdmi_tx .......
Finished optimization stage 1 on synchronizer_hdmi_tx (CPU Time 0h:00m:00s, Memory Used current: 106MB peak: 107MB)
@N:CD630 : HDMI_TX.vhd(634) | Synthesizing work.tmds_encoder.tmds_encoder_architecture.
Post processing for work.tmds_encoder.tmds_encoder_architecture
Running optimization stage 1 on tmds_encoder .......
Finished optimization stage 1 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 107MB)
Post processing for work.hdmi_tx_native.hdmi_tx_native
Running optimization stage 1 on HDMI_TX_Native .......
Finished optimization stage 1 on HDMI_TX_Native (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 107MB)
Post processing for work.hdmi_tx.rtl
Running optimization stage 1 on HDMI_TX .......
@W:CL252 : HDMI_TX.vhd(138) | Bit 0 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 1 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 2 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 3 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 4 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 5 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 6 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 7 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 8 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 9 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 10 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 11 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 12 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 13 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 14 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 15 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 16 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 17 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 18 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 19 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 20 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 21 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 22 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL252 : HDMI_TX.vhd(138) | Bit 23 of signal s_data_o is floating -- simulation mismatch possible.
@W:CL240 : HDMI_TX.vhd(51) | Signal TREADY_O is floating; a simulation mismatch is possible.
Finished optimization stage 1 on HDMI_TX (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 107MB)
Post processing for work.hdmi_tx_c0.rtl
Running optimization stage 1 on HDMI_TX_C0 .......
Finished optimization stage 1 on HDMI_TX_C0 (CPU Time 0h:00m:00s, Memory Used current: 107MB peak: 107MB)
@N:CD630 : Display_Controller_C0.vhd(30) | Synthesizing work.display_controller_c0.rtl.
@W:CD729 : Display_Controller_C0.vhd(138) | Component declaration has 4 generics but entity declares only 3 generics
@N:CD630 : Display_Controller.vhd(25) | Synthesizing work.display_controller.rtl.
@W:CD638 : Display_Controller.vhd(155) | Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Display_Controller.vhd(156) | Signal s_vsync_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Display_Controller.vhd(157) | Signal s_hsync_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Display_Controller.vhd(158) | Signal s_frame_end_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD796 : Display_Controller.vhd(159) | Bit 0 of signal s_trigger_mstr is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W:CD638 : Display_Controller.vhd(160) | Signal s_ext_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Display_Controller.vhd(161) | Signal s_vactive_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : Display_Controller.vhd(280) | Synthesizing work.display_controller_native.display_controller_native.
Post processing for work.display_controller_native.display_controller_native
Running optimization stage 1 on Display_Controller_Native .......
Finished optimization stage 1 on Display_Controller_Native (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB)
Post processing for work.display_controller.rtl
Running optimization stage 1 on Display_Controller .......
@W:CL240 : Display_Controller.vhd(86) | Signal TVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Display_Controller.vhd(83) | Signal TLAST_O is floating; a simulation mismatch is possible.
@W:CL252 : Display_Controller.vhd(81) | Bit 0 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(81) | Bit 1 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(81) | Bit 2 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(81) | Bit 3 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(80) | Bit 0 of signal TKEEP_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(80) | Bit 1 of signal TKEEP_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(80) | Bit 2 of signal TKEEP_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(78) | Bit 0 of signal TSTRB_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(78) | Bit 1 of signal TSTRB_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(78) | Bit 2 of signal TSTRB_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 0 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 1 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 2 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 3 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 4 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 5 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 6 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Display_Controller.vhd(76) | Bit 7 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL240 : Display_Controller.vhd(55) | Signal TREADY_O is floating; a simulation mismatch is possible.
Finished optimization stage 1 on Display_Controller (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB)
Post processing for work.display_controller_c0.rtl
Running optimization stage 1 on Display_Controller_C0 .......
Finished optimization stage 1 on Display_Controller_C0 (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB)
@N:CD630 : RGBtoYCbCr_C0.vhd(31) | Synthesizing work.rgbtoycbcr_c0.rtl.
Post processing for work.ycbcr_444to422.rtl
Running optimization stage 1 on YCbCr_444to422 .......
Finished optimization stage 1 on YCbCr_444to422 (CPU Time 0h:00m:00s, Memory Used current: 110MB peak: 111MB)
Post processing for work.rgb2ycbcr.rtl
Running optimization stage 1 on RGB2YCbCr .......
Finished optimization stage 1 on RGB2YCbCr (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB)
Post processing for work.rgbtoycbcr.rtl
Running optimization stage 1 on RGBtoYCbCr .......
Finished optimization stage 1 on RGBtoYCbCr (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB)
Post processing for work.rgbtoycbcr_c0.rtl
Running optimization stage 1 on RGBtoYCbCr_C0 .......
Finished optimization stage 1 on RGBtoYCbCr_C0 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB)
@N:CD630 : intensity_average.vhd(23) | Synthesizing work.intensity_average.architecture_intensity_average.
Post processing for work.intensity_average.architecture_intensity_average
Running optimization stage 1 on intensity_average .......
Finished optimization stage 1 on intensity_average (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 111MB)
@N:CD630 : Image_Enhancement_C0.vhd(31) | Synthesizing work.image_enhancement_c0.rtl.
@W:CD729 : Image_Enhancement_C0.vhd(214) | Component declaration has 5 generics but entity declares only 4 generics
@N:CD630 : Image_Enhancement.vhd(24) | Synthesizing work.image_enhancement.rtl.
@W:CD638 : Image_Enhancement.vhd(338) | Signal s_eof is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(339) | Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(340) | Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(341) | Signal s_data_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(342) | Signal s_data_i_4k is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(343) | Signal s_data_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(344) | Signal s_data_4k_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(345) | Signal s_r_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(346) | Signal s_g_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(347) | Signal s_b_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Image_Enhancement.vhd(348) | Signal s_c_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.image_enhancement_native.image_enhancement_native
Running optimization stage 1 on Image_Enhancement_Native .......
Finished optimization stage 1 on Image_Enhancement_Native (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB)
Post processing for work.image_enhancement.rtl
Running optimization stage 1 on Image_Enhancement .......
@W:CL240 : Image_Enhancement.vhd(187) | Signal TKEEP_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(185) | Signal TSTRB_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(183) | Signal TVALID_O is floating; a simulation mismatch is possible.
@W:CL252 : Image_Enhancement.vhd(180) | Bit 0 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(180) | Bit 1 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(180) | Bit 2 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(180) | Bit 3 of signal TUSER_O is floating -- simulation mismatch possible.
@W:CL240 : Image_Enhancement.vhd(178) | Signal TLAST_O is floating; a simulation mismatch is possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 0 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 1 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 2 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 3 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 4 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 5 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 6 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 7 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 8 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 9 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 10 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 11 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 12 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 13 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 14 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 15 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 16 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 17 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 18 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 19 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 20 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 21 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 22 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(176) | Bit 23 of signal TDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(141) | Bit 0 of signal AXI_BID_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(141) | Bit 1 of signal AXI_BID_O is floating -- simulation mismatch possible.
@W:CL240 : Image_Enhancement.vhd(139) | Signal AXI_RLAST_O is floating; a simulation mismatch is possible.
@W:CL252 : Image_Enhancement.vhd(137) | Bit 0 of signal AXI_RID_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(137) | Bit 1 of signal AXI_RID_O is floating -- simulation mismatch possible.
@W:CL240 : Image_Enhancement.vhd(135) | Signal AXI_RUSER_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(131) | Signal AXI_BUSER_O is floating; a simulation mismatch is possible.
@W:CL252 : Image_Enhancement.vhd(109) | Bit 0 of signal AXI_RRESP_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(109) | Bit 1 of signal AXI_RRESP_O is floating -- simulation mismatch possible.
@W:CL240 : Image_Enhancement.vhd(105) | Signal AXI_RVALID_O is floating; a simulation mismatch is possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 0 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 1 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 2 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 3 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 4 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 5 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 6 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 7 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 8 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 9 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 10 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 11 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 12 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 13 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 14 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 15 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 16 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 17 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 18 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 19 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 20 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 21 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 22 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W:CL252 : Image_Enhancement.vhd(103) | Bit 23 of signal AXI_RDATA_O is floating -- simulation mismatch possible.

Only the first 100 messages of id 'CL252' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_compiler.srr -id CL252' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL252} -count unlimited' in the Tcl shell.
@W:CL240 : Image_Enhancement.vhd(95) | Signal AXI_ARREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(87) | Signal AXI_BVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(83) | Signal AXI_WREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(71) | Signal AXI_AWREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Image_Enhancement.vhd(56) | Signal TREADY_O is floating; a simulation mismatch is possible.
Finished optimization stage 1 on Image_Enhancement (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB)
Post processing for work.image_enhancement_c0.rtl
Running optimization stage 1 on Image_Enhancement_C0 .......
Finished optimization stage 1 on Image_Enhancement_C0 (CPU Time 0h:00m:00s, Memory Used current: 111MB peak: 112MB)
@N:CD630 : Gamma_Correction_C0.vhd(30) | Synthesizing work.gamma_correction_c0.rtl.
@W:CD729 : Gamma_Correction_C0.vhd(128) | Component declaration has 4 generics but entity declares only 3 generics
@N:CD630 : Gamma_Correction.vhd(24) | Synthesizing work.gamma_correction.rtl.
@W:CD638 : Gamma_Correction.vhd(182) | Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(183) | Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(184) | Signal s_eof is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(185) | Signal s_data_o is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(186) | Signal s_red_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(187) | Signal s_green_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(188) | Signal s_blue_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(189) | Signal s_red_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(190) | Signal s_green_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(191) | Signal s_blue_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(193) | Signal s_data_4p_o is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(194) | Signal s_red_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(195) | Signal s_green_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(196) | Signal s_blue_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(197) | Signal s_red_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(198) | Signal s_green_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Gamma_Correction.vhd(199) | Signal s_blue_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.gamma_correction_native.gamma_correction_native
Running optimization stage 1 on Gamma_Correction_Native .......
Finished optimization stage 1 on Gamma_Correction_Native (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 129MB)
Post processing for work.gamma_correction.rtl
Running optimization stage 1 on Gamma_Correction .......
@W:CL240 : Gamma_Correction.vhd(88) | Signal TVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Gamma_Correction.vhd(85) | Signal TLAST_O is floating; a simulation mismatch is possible.
@W:CL240 : Gamma_Correction.vhd(83) | Signal TKEEP_O is floating; a simulation mismatch is possible.
@W:CL240 : Gamma_Correction.vhd(81) | Signal TSTRB_O is floating; a simulation mismatch is possible.
@W:CL240 : Gamma_Correction.vhd(53) | Signal TREADY_O is floating; a simulation mismatch is possible.
Finished optimization stage 1 on Gamma_Correction (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 129MB)
Post processing for work.gamma_correction_c0.rtl
Running optimization stage 1 on Gamma_Correction_C0 .......
Finished optimization stage 1 on Gamma_Correction_C0 (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 129MB)
@N:CD630 : Bayer_Interpolation_C0.vhd(32) | Synthesizing work.bayer_interpolation_c0.rtl.
@W:CD729 : Bayer_Interpolation_C0.vhd(229) | Component declaration has 6 generics but entity declares only 5 generics
@N:CD630 : Bayer_Interpolation.vhd(24) | Synthesizing work.bayer_interpolation.rtl.
@W:CD638 : Bayer_Interpolation.vhd(321) | Signal s_eof_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(322) | Signal s_eof_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(323) | Signal s_bayer_format_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(324) | Signal s_data_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(325) | Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(326) | Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(327) | Signal s_bayer_red_o is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(328) | Signal s_bayer_green_o is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(329) | Signal s_bayer_blue_o is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(333) | Signal s_red_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(334) | Signal s_green_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(335) | Signal s_blue_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : Bayer_Interpolation.vhd(337) | Signal s_data_o_axi is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : Bayer_Interpolation.vhd(686) | Synthesizing work.bayer_native.bayer_native_arch.
@N:CD630 : Bayer_Interpolation.vhd(856) | Synthesizing work.bayer_interpolation_1p.bayer_interpolation_1p.
@N:CD630 : Bayer_Interpolation.vhd(2211) | Synthesizing work.ramdualport_bayer.rtl.
Post processing for work.ramdualport_bayer.rtl
Running optimization stage 1 on ramDualPort_bayer .......
@N:CL134 : Bayer_Interpolation.vhd(2234) | Found RAM ram, depth=2048, width=8
Finished optimization stage 1 on ramDualPort_bayer (CPU Time 0h:00m:00s, Memory Used current: 129MB peak: 129MB)
@N:CD630 : Bayer_Interpolation.vhd(1240) | Synthesizing work.bayer_filter.bayer_filter.
Post processing for work.bayer_filter.bayer_filter
Running optimization stage 1 on BAYER_FILTER .......
@W:CL271 : Bayer_Interpolation.vhd(1410) | Pruning unused bits 12 to 8 of s_b_11(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : Bayer_Interpolation.vhd(1410) | Pruning unused bits 12 to 8 of s_g_11(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL271 : Bayer_Interpolation.vhd(1410) | Pruning unused bits 12 to 8 of s_r_16(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 1 on BAYER_FILTER (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
@N:CD630 : Bayer_Interpolation.vhd(1780) | Synthesizing work.read_lsram.read_lsram.
@N:CD233 : Bayer_Interpolation.vhd(1889) | Using sequential encoding for type fsm_state.
@N:CD364 : Bayer_Interpolation.vhd(2078) | Removing redundant assignment.
@N:CD604 : Bayer_Interpolation.vhd(2140) | OTHERS clause is not synthesized.
Post processing for work.read_lsram.read_lsram
Running optimization stage 1 on READ_LSRAM .......
@A:CL282 : Bayer_Interpolation.vhd(2090) | Feedback mux created for signal s_last_pixel. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
@A:CL282 : Bayer_Interpolation.vhd(2001) | Feedback mux created for signal s_data_valid_o_dly3. It is possible a set/reset assignment for this is signal missing. To improve timing and area, specify a set/reset value.
Finished optimization stage 1 on READ_LSRAM (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
@N:CD630 : Bayer_Interpolation.vhd(1519) | Synthesizing work.write_lsram.write_lsram.
@N:CD364 : Bayer_Interpolation.vhd(1737) | Removing redundant assignment.
Post processing for work.write_lsram.write_lsram
Running optimization stage 1 on WRITE_LSRAM .......
Finished optimization stage 1 on WRITE_LSRAM (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
Post processing for work.bayer_interpolation_1p.bayer_interpolation_1p
Running optimization stage 1 on Bayer_Interpolation_1p .......
Finished optimization stage 1 on Bayer_Interpolation_1p (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
Post processing for work.bayer_native.bayer_native_arch
Running optimization stage 1 on Bayer_Native .......
Finished optimization stage 1 on Bayer_Native (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
Post processing for work.bayer_interpolation.rtl
Running optimization stage 1 on Bayer_Interpolation .......
@W:CL240 : Bayer_Interpolation.vhd(191) | Signal TVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(189) | Signal TLAST_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(187) | Signal TKEEP_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(185) | Signal TSTRB_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(146) | Signal AXI_RLAST_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(142) | Signal AXI_RUSER_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(138) | Signal AXI_BUSER_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(112) | Signal AXI_RVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(102) | Signal AXI_ARREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(94) | Signal AXI_BVALID_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(90) | Signal AXI_WREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(78) | Signal AXI_AWREADY_O is floating; a simulation mismatch is possible.
@W:CL240 : Bayer_Interpolation.vhd(57) | Signal TREADY_O is floating; a simulation mismatch is possible.
Finished optimization stage 1 on Bayer_Interpolation (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
Post processing for work.bayer_interpolation_c0.rtl
Running optimization stage 1 on Bayer_Interpolation_C0 .......
Finished optimization stage 1 on Bayer_Interpolation_C0 (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
@N: :  | Setting default value for generic g_apb3_interface_data_width to 32; 
@N: :  | Setting default value for generic g_const_width to 12; 
@N:CD630 : apb3_interface.vhd(23) | Synthesizing work.apb3_interface.apb3_interface.
@W:CD638 : apb3_interface.vhd(96) | Signal s_signature is undriven. Either assign the signal a value or remove the signal declaration.
Post processing for work.apb3_interface.apb3_interface
Running optimization stage 1 on work_apb3_interface_apb3_interface_32_12_1_g_APB3_INTERFACE_DATA_WIDTHg_CONST_WIDTH .......
Finished optimization stage 1 on work_apb3_interface_apb3_interface_32_12_1_g_APB3_INTERFACE_DATA_WIDTHg_CONST_WIDTH (CPU Time 0h:00m:00s, Memory Used current: 130MB peak: 135MB)
@N:CD630 : write_mux.vhd(23) | Synthesizing work.write_mux.write_mux.
Post processing for work.write_mux.write_mux
Running optimization stage 1 on write_mux .......
Finished optimization stage 1 on write_mux (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : write_demux.vhd(23) | Synthesizing work.write_demux.write_demux.
Post processing for work.write_demux.write_demux
Running optimization stage 1 on write_demux .......
Finished optimization stage 1 on write_demux (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : request_scheduler.vhd(23) | Synthesizing work.request_scheduler.request_scheduler.
@N:CD231 : request_scheduler.vhd(68) | Using onehot encoding for type scheduler_states. For example, enumeration idle is mapped to "100000".
@N:CD604 : request_scheduler.vhd(262) | OTHERS clause is not synthesized.
Post processing for work.request_scheduler.request_scheduler
Running optimization stage 1 on request_scheduler .......
Finished optimization stage 1 on request_scheduler (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : read_mux.vhd(23) | Synthesizing work.read_mux.read_mux.
Post processing for work.read_mux.read_mux
Running optimization stage 1 on read_mux .......
Finished optimization stage 1 on read_mux (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : read_demux.vhd(23) | Synthesizing work.read_demux.read_demux.
Post processing for work.read_demux.read_demux
Running optimization stage 1 on read_demux .......
Finished optimization stage 1 on read_demux (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N: :  | Setting default value for generic g_video_fifo_awidth to 9; 
@N: :  | Setting default value for generic g_input_video_data_bit_width to 512; 
@N: :  | Setting default value for generic g_half_empty_threshold to 256; 
@N:CD630 : video_fifo.vhd(25) | Synthesizing work.video_fifo.video_fifo.
@W:CD638 : video_fifo.vhd(121) | Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : video_fifo.vhd(122) | Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : ram2port.vhd(5) | Synthesizing work.ram2port.ram2port.
Post processing for work.ram2port.ram2port
Running optimization stage 1 on ram2PORT .......
@N:CL134 : ram2port.vhd(22) | Found RAM io1l, depth=512, width=512
Finished optimization stage 1 on ram2PORT (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
Post processing for work.video_fifo.video_fifo
Running optimization stage 1 on work_video_fifo_video_fifo_9_512_256_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD .......
@W:CL265 : video_fifo.vhd(374) | Removing unused bit 9 of wdata_count_2(9 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL265 : video_fifo.vhd(270) | Removing unused bit 9 of rdata_count_2(9 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL260 : video_fifo.vhd(221) | Pruning register bit 9 of rptr(9 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : video_fifo.vhd(321) | Pruning register bit 9 of wptr(9 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on work_video_fifo_video_fifo_9_512_256_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N: :  | Setting default value for generic g_data_width to 1; 
@N:CD630 : synchronizer_circuit.vhd(22) | Synthesizing work.synchronizer_circuit.behaviour.
@W:CG296 : synchronizer_circuit.vhd(38) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W:CG290 : synchronizer_circuit.vhd(40) | Referenced variable reset_n is not in sensitivity list.
Post processing for work.synchronizer_circuit.behaviour
Running optimization stage 1 on work_synchronizer_circuit_behaviour_1_1_g_data_width .......
Finished optimization stage 1 on work_synchronizer_circuit_behaviour_1_1_g_data_width (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : DDR_write_controller_lpddr4.vhd(25) | Synthesizing work.ddr_write_controller_lpddr4.ddr_write_controller.
@N:CD233 : DDR_write_controller_lpddr4.vhd(98) | Using sequential encoding for type fsm_state.
@N:CD604 : DDR_write_controller_lpddr4.vhd(238) | OTHERS clause is not synthesized.
Post processing for work.ddr_write_controller_lpddr4.ddr_write_controller
Running optimization stage 1 on DDR_write_controller_lpddr4 .......
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(10) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(11) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(12) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_count_max(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : DDR_write_controller_lpddr4.vhd(187) | Pruning register bits 15 to 10 of s_count_max(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
Finished optimization stage 1 on DDR_write_controller_lpddr4 (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : data_packer_lpddr4.vhd(25) | Synthesizing work.data_packer_lpddr4.data_packer_arch.
Post processing for work.data_packer_lpddr4.data_packer_arch
Running optimization stage 1 on data_packer_lpddr4 .......
Finished optimization stage 1 on data_packer_lpddr4 (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N: :  | Setting default value for generic g_video_fifo_awidth to 12; 
@N: :  | Setting default value for generic g_input_video_data_bit_width to 512; 
@N: :  | Setting default value for generic g_half_empty_threshold to 1048; 
@N:CD630 : video_fifo.vhd(25) | Synthesizing work.video_fifo.video_fifo.
@W:CD638 : video_fifo.vhd(121) | Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W:CD638 : video_fifo.vhd(122) | Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@N:CD630 : ram2port.vhd(5) | Synthesizing work.ram2port.ram2port.
Post processing for work.ram2port.ram2port
Running optimization stage 1 on ram2PORT .......
@N:CL134 : ram2port.vhd(22) | Found RAM io1l, depth=4096, width=512
Finished optimization stage 1 on ram2PORT (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
Post processing for work.video_fifo.video_fifo
Running optimization stage 1 on work_video_fifo_video_fifo_12_512_1048_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD .......
@W:CL265 : video_fifo.vhd(374) | Removing unused bit 12 of wdata_count_2(12 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL265 : video_fifo.vhd(270) | Removing unused bit 12 of rdata_count_2(12 downto 0). Either assign all bits or reduce the width of the signal.
@W:CL260 : video_fifo.vhd(221) | Pruning register bit 12 of rptr(12 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : video_fifo.vhd(321) | Pruning register bit 12 of wptr(12 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on work_video_fifo_video_fifo_12_512_1048_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N: :  | Setting default value for generic g_register_width to 513; 
@N:CD630 : register_config.vhd(26) | Synthesizing work.register_config.register_config.
Post processing for work.register_config.register_config
Running optimization stage 1 on work_register_config_register_config_513_1_G_REGISTER_WIDTH .......
Finished optimization stage 1 on work_register_config_register_config_513_1_G_REGISTER_WIDTH (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : DDR_read_controller_FHD_HDMI_RX.vhd(25) | Synthesizing work.ddr_read_controller_fhd_hdmi_rx.ddr_read_controller_hdmi_rx.
@N:CD233 : DDR_read_controller_FHD_HDMI_RX.vhd(90) | Using sequential encoding for type fsm_state.
@N:CD604 : DDR_read_controller_FHD_HDMI_RX.vhd(209) | OTHERS clause is not synthesized.
@W:CG296 : DDR_read_controller_FHD_HDMI_RX.vhd(169) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W:CG290 : DDR_read_controller_FHD_HDMI_RX.vhd(174) | Referenced variable frame_index_i is not in sensitivity list.
Post processing for work.ddr_read_controller_fhd_hdmi_rx.ddr_read_controller_hdmi_rx
Running optimization stage 1 on DDR_read_controller_FHD_HDMI_RX .......
@W:CL260 : DDR_read_controller_FHD_HDMI_RX.vhd(137) | Pruning register bit 0 of s_pan_h_dly(11 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : DDR_read_controller_FHD_HDMI_RX.vhd(137) | Pruning register bit 0 of s_pan_h(11 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
Finished optimization stage 1 on DDR_read_controller_FHD_HDMI_RX (CPU Time 0h:00m:00s, Memory Used current: 132MB peak: 136MB)
@N:CD630 : data_unpacker_FHD_RX_0.vhd(25) | Synthesizing work.data_unpacker_fhd_rx.data_unpacker_fhd_rx.
Post processing for work.data_unpacker_fhd_rx.data_unpacker_fhd_rx
Running optimization stage 1 on data_unpacker_FHD_RX .......
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(496) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(497) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(498) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(499) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(500) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(501) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(502) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(503) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(504) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(505) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(506) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(507) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(508) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(509) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(510) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W:CL111 : data_unpacker_FHD_RX_0.vhd(169) | All reachable assignments to s_data_pack(511) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
Finished optimization stage 1 on data_unpacker_FHD_RX (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 136MB)
Running optimization stage 2 on data_unpacker_FHD_RX .......
@W:CL246 : data_unpacker_FHD_RX_0.vhd(44) | Input port bits 4 to 0 of horz_resl_i(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on data_unpacker_FHD_RX (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 136MB)
Running optimization stage 2 on DDR_read_controller_FHD_HDMI_RX .......
@N:CL201 : DDR_read_controller_FHD_HDMI_RX.vhd(171) | Trying to extract state machine for register s_state.
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@W:CL247 : DDR_read_controller_FHD_HDMI_RX.vhd(55) | Input port bit 0 of h_pan_i(11 downto 0) is unused 
Finished optimization stage 2 on DDR_read_controller_FHD_HDMI_RX (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 136MB)
Running optimization stage 2 on work_register_config_register_config_513_1_G_REGISTER_WIDTH .......
Finished optimization stage 2 on work_register_config_register_config_513_1_G_REGISTER_WIDTH (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 136MB)
Running optimization stage 2 on ram2PORT_work_video_fifo_video_fifo_1layer1 .......
Finished optimization stage 2 on ram2PORT_work_video_fifo_video_fifo_1layer1 (CPU Time 0h:00m:00s, Memory Used current: 133MB peak: 136MB)
Running optimization stage 2 on work_video_fifo_video_fifo_12_512_1048_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD .......
Finished optimization stage 2 on work_video_fifo_video_fifo_12_512_1048_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 136MB)
Running optimization stage 2 on data_packer_lpddr4 .......
Finished optimization stage 2 on data_packer_lpddr4 (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 136MB)
Running optimization stage 2 on DDR_write_controller_lpddr4 .......
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(1) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(2) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(6) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(7) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : DDR_write_controller_lpddr4.vhd(187) | Optimizing register bit s_line_counter(8) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : DDR_write_controller_lpddr4.vhd(187) | Pruning register bits 8 to 0 of s_line_counter(22 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@N:CL201 : DDR_write_controller_lpddr4.vhd(187) | Trying to extract state machine for register s_state.
Extracted state machine for register s_state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Finished optimization stage 2 on DDR_write_controller_lpddr4 (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 136MB)
Running optimization stage 2 on work_synchronizer_circuit_behaviour_1_1_g_data_width .......
Finished optimization stage 2 on work_synchronizer_circuit_behaviour_1_1_g_data_width (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 136MB)
Running optimization stage 2 on ram2PORT_work_video_fifo_video_fifo_0layer1 .......
Finished optimization stage 2 on ram2PORT_work_video_fifo_video_fifo_0layer1 (CPU Time 0h:00m:00s, Memory Used current: 134MB peak: 136MB)
Running optimization stage 2 on work_video_fifo_video_fifo_9_512_256_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD .......
Finished optimization stage 2 on work_video_fifo_video_fifo_9_512_256_1_g_VIDEO_FIFO_AWIDTHg_INPUT_VIDEO_DATA_BIT_WIDTHg_HALF_EMPTY_THRESHOLD (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 137MB)
Running optimization stage 2 on read_demux .......
Finished optimization stage 2 on read_demux (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 137MB)
Running optimization stage 2 on read_mux .......
Finished optimization stage 2 on read_mux (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 137MB)
Running optimization stage 2 on request_scheduler .......
@N:CL201 : request_scheduler.vhd(190) | Trying to extract state machine for register s_state.
Extracted state machine for register s_state
State machine has 6 reachable states with original encodings of:
   000001
   000010
   000100
   001000
   010000
   100000
Finished optimization stage 2 on request_scheduler (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 137MB)
Running optimization stage 2 on write_demux .......
Finished optimization stage 2 on write_demux (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 137MB)
Running optimization stage 2 on write_mux .......
Finished optimization stage 2 on write_mux (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 140MB)
Running optimization stage 2 on work_apb3_interface_apb3_interface_32_12_1_g_APB3_INTERFACE_DATA_WIDTHg_CONST_WIDTH .......
@W:CL246 : apb3_interface.vhd(42) | Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : apb3_interface.vhd(43) | Input port bits 31 to 20 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on work_apb3_interface_apb3_interface_32_12_1_g_APB3_INTERFACE_DATA_WIDTHg_CONST_WIDTH (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 140MB)
Running optimization stage 2 on WRITE_LSRAM_16 .......
Finished optimization stage 2 on WRITE_LSRAM_16 (CPU Time 0h:00m:00s, Memory Used current: 135MB peak: 140MB)
Running optimization stage 2 on READ_LSRAM_8_16 .......
@N:CL135 : Bayer_Interpolation.vhd(2001) | Found sequential shift s_v_counter_dly3 with address depth of 3 words and data bit width of 16.
@N:CL135 : Bayer_Interpolation.vhd(2001) | Found sequential shift s_h_counter_dly3 with address depth of 3 words and data bit width of 16.
@N:CL201 : Bayer_Interpolation.vhd(2090) | Trying to extract state machine for register s_state.
Extracted state machine for register s_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
Finished optimization stage 2 on READ_LSRAM_8_16 (CPU Time 0h:00m:00s, Memory Used current: 136MB peak: 140MB)
Running optimization stage 2 on BAYER_FILTER_8 .......
Finished optimization stage 2 on BAYER_FILTER_8 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on ramDualPort_bayer_8_16_2048 .......
Finished optimization stage 2 on ramDualPort_bayer_8_16_2048 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Bayer_Interpolation_1p_8_2048 .......
Finished optimization stage 2 on Bayer_Interpolation_1p_8_2048 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Bayer_Native_1_8_2048 .......
Finished optimization stage 2 on Bayer_Native_1_8_2048 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Bayer_Interpolation_1_8_2048_0_0 .......
@N:CL159 : Bayer_Interpolation.vhd(52) | Input TDATA_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(55) | Input TVALID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(59) | Input TUSER_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(71) | Input AXI_RESETN_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(73) | Input AXI_CLK_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(76) | Input AXI_AWVALID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(80) | Input AXI_AWADDR_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(82) | Input AXI_AWPROT_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(84) | Input AXI_AWBURST_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(86) | Input AXI_WDATA_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(88) | Input AXI_WVALID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(92) | Input AXI_WSTRB_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(96) | Input AXI_BREADY_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(100) | Input AXI_ARVALID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(104) | Input AXI_ARADDR_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(106) | Input AXI_ARPROT_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(108) | Input AXI_ARBURST_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(114) | Input AXI_RREADY_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(118) | Input AXI_AWID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(120) | Input AXI_AWLEN_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(122) | Input AXI_AWSIZE_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(124) | Input AXI_AWLOCK_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(126) | Input AXI_AWCACHE_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(128) | Input AXI_AWUSER_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(130) | Input AXI_AWQOS_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(132) | Input AXI_AWREGION_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(134) | Input AXI_WLAST_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(136) | Input AXI_WUSER_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(140) | Input AXI_ARUSER_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(150) | Input AXI_ARID_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(152) | Input AXI_ARLEN_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(154) | Input AXI_ARSIZE_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(156) | Input AXI_ARLOCK_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(158) | Input AXI_ARCACHE_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(160) | Input AXI_ARQOS_I is unused.
@N:CL159 : Bayer_Interpolation.vhd(162) | Input AXI_ARREGION_I is unused.
Finished optimization stage 2 on Bayer_Interpolation_1_8_2048_0_0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Bayer_Interpolation_C0 .......
Finished optimization stage 2 on Bayer_Interpolation_C0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Gamma_Correction_Native_8 .......
Finished optimization stage 2 on Gamma_Correction_Native_8 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Gamma_Correction_1_8_0 .......
@N:CL159 : Gamma_Correction.vhd(45) | Input TDATA_I is unused.
@N:CL159 : Gamma_Correction.vhd(48) | Input TVALID_I is unused.
@N:CL159 : Gamma_Correction.vhd(50) | Input TUSER_I is unused.
Finished optimization stage 2 on Gamma_Correction_1_8_0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Gamma_Correction_C0 .......
Finished optimization stage 2 on Gamma_Correction_C0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Image_Enhancement_Native_8 .......
Finished optimization stage 2 on Image_Enhancement_Native_8 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Image_Enhancement_8_1_0_0 .......
@N:CL159 : Image_Enhancement.vhd(51) | Input TDATA_I is unused.
@N:CL159 : Image_Enhancement.vhd(54) | Input TVALID_I is unused.
@N:CL159 : Image_Enhancement.vhd(58) | Input TUSER_I is unused.
@N:CL159 : Image_Enhancement.vhd(64) | Input AXI_RESETN_I is unused.
@N:CL159 : Image_Enhancement.vhd(66) | Input AXI_CLK_I is unused.
@N:CL159 : Image_Enhancement.vhd(69) | Input AXI_AWVALID_I is unused.
@N:CL159 : Image_Enhancement.vhd(73) | Input AXI_AWADDR_I is unused.
@N:CL159 : Image_Enhancement.vhd(75) | Input AXI_AWPROT_I is unused.
@N:CL159 : Image_Enhancement.vhd(77) | Input AXI_AWBURST_I is unused.
@N:CL159 : Image_Enhancement.vhd(79) | Input AXI_WDATA_I is unused.
@N:CL159 : Image_Enhancement.vhd(81) | Input AXI_WVALID_I is unused.
@N:CL159 : Image_Enhancement.vhd(85) | Input AXI_WSTRB_I is unused.
@N:CL159 : Image_Enhancement.vhd(89) | Input AXI_BREADY_I is unused.
@N:CL159 : Image_Enhancement.vhd(93) | Input AXI_ARVALID_I is unused.
@N:CL159 : Image_Enhancement.vhd(97) | Input AXI_ARADDR_I is unused.
@N:CL159 : Image_Enhancement.vhd(99) | Input AXI_ARPROT_I is unused.
@N:CL159 : Image_Enhancement.vhd(101) | Input AXI_ARBURST_I is unused.
@N:CL159 : Image_Enhancement.vhd(107) | Input AXI_RREADY_I is unused.
@N:CL159 : Image_Enhancement.vhd(111) | Input AXI_AWID_I is unused.
@N:CL159 : Image_Enhancement.vhd(113) | Input AXI_AWLEN_I is unused.
@N:CL159 : Image_Enhancement.vhd(115) | Input AXI_AWSIZE_I is unused.
@N:CL159 : Image_Enhancement.vhd(117) | Input AXI_AWLOCK_I is unused.
@N:CL159 : Image_Enhancement.vhd(119) | Input AXI_AWCACHE_I is unused.
@N:CL159 : Image_Enhancement.vhd(121) | Input AXI_AWUSER_I is unused.
@N:CL159 : Image_Enhancement.vhd(123) | Input AXI_AWQOS_I is unused.
@N:CL159 : Image_Enhancement.vhd(125) | Input AXI_AWREGION_I is unused.
@N:CL159 : Image_Enhancement.vhd(127) | Input AXI_WLAST_I is unused.
@N:CL159 : Image_Enhancement.vhd(129) | Input AXI_WUSER_I is unused.
@N:CL159 : Image_Enhancement.vhd(133) | Input AXI_ARUSER_I is unused.
@N:CL159 : Image_Enhancement.vhd(143) | Input AXI_ARID_I is unused.
@N:CL159 : Image_Enhancement.vhd(145) | Input AXI_ARLEN_I is unused.
@N:CL159 : Image_Enhancement.vhd(147) | Input AXI_ARSIZE_I is unused.
@N:CL159 : Image_Enhancement.vhd(149) | Input AXI_ARLOCK_I is unused.
@N:CL159 : Image_Enhancement.vhd(151) | Input AXI_ARCACHE_I is unused.
@N:CL159 : Image_Enhancement.vhd(153) | Input AXI_ARQOS_I is unused.
@N:CL159 : Image_Enhancement.vhd(155) | Input AXI_ARREGION_I is unused.
Finished optimization stage 2 on Image_Enhancement_8_1_0_0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on Image_Enhancement_C0 .......
Finished optimization stage 2 on Image_Enhancement_C0 (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on intensity_average .......
@W:CL247 : intensity_average.vhd(29) | Input port bit 0 of r_i(7 downto 0) is unused 
@W:CL246 : intensity_average.vhd(31) | Input port bits 1 to 0 of b_i(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
Finished optimization stage 2 on intensity_average (CPU Time 0h:00m:00s, Memory Used current: 139MB peak: 141MB)
Running optimization stage 2 on RGB2YCbCr_8_8 .......
Finished optimization stage 2 on RGB2YCbCr_8_8 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on YCbCr_444to422_8_8 .......
Finished optimization stage 2 on YCbCr_444to422_8_8 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on RGBtoYCbCr_8_8_2_0_1 .......
Finished optimization stage 2 on RGBtoYCbCr_8_8_2_0_1 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on RGBtoYCbCr_C0 .......
Finished optimization stage 2 on RGBtoYCbCr_C0 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on Display_Controller_Native_0_1 .......
@W:CL190 : Display_Controller.vhd(509) | Optimizing register bit s_h_counter(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(637) | Optimizing register bit s_h_counterx(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL260 : Display_Controller.vhd(637) | Pruning register bit 15 of s_h_counterx(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : Display_Controller.vhd(549) | Pruning register bit 15 of s_v_counter(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W:CL260 : Display_Controller.vhd(509) | Pruning register bit 15 of s_h_counter(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@N:CL189 : Display_Controller.vhd(509) | Register bit s_h_counter(14) is always 0.
@N:CL189 : Display_Controller.vhd(509) | Register bit s_h_counter(13) is always 0.
@N:CL189 : Display_Controller.vhd(509) | Register bit s_h_counter(12) is always 0.
@N:CL189 : Display_Controller.vhd(509) | Register bit s_h_counter(11) is always 0.
@N:CL189 : Display_Controller.vhd(637) | Register bit s_h_counterx(14) is always 0.
@N:CL189 : Display_Controller.vhd(637) | Register bit s_h_counterx(13) is always 0.
@N:CL189 : Display_Controller.vhd(637) | Register bit s_h_counterx(12) is always 0.
@N:CL189 : Display_Controller.vhd(637) | Register bit s_h_counterx(11) is always 0.
@W:CL279 : Display_Controller.vhd(637) | Pruning register bits 14 to 11 of s_h_counterx(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL279 : Display_Controller.vhd(509) | Pruning register bits 14 to 11 of s_h_counter(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(10) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(11) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(12) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : Display_Controller.vhd(549) | Optimizing register bit s_v_counter(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL279 : Display_Controller.vhd(549) | Pruning register bits 14 to 10 of s_v_counter(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W:CL190 : Display_Controller.vhd(692) | Optimizing register bit s_v_counterx(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : Display_Controller.vhd(692) | Pruning unused register s_v_counterx(15). Make sure that there are no unused intermediate registers.
Finished optimization stage 2 on Display_Controller_Native_0_1 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on Display_Controller_0_1_0 .......
@N:CL159 : Display_Controller.vhd(53) | Input TVALID_I is unused.
Finished optimization stage 2 on Display_Controller_0_1_0 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on Display_Controller_C0 .......
Finished optimization stage 2 on Display_Controller_C0 (CPU Time 0h:00m:00s, Memory Used current: 140MB peak: 141MB)
Running optimization stage 2 on tmds_encoder .......
Finished optimization stage 2 on tmds_encoder (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 143MB)
Running optimization stage 2 on synchronizer_hdmi_tx .......
Finished optimization stage 2 on synchronizer_hdmi_tx (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 143MB)
Running optimization stage 2 on ram2port_hdmi_tx_6_10 .......
Finished optimization stage 2 on ram2port_hdmi_tx_6_10 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 143MB)
Running optimization stage 2 on video_fifo_hdmi_tx_work_hdmi_tx_c0_rtl_0layer1 .......
Finished optimization stage 2 on video_fifo_hdmi_tx_work_hdmi_tx_c0_rtl_0layer1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on tx_fifo_top_work_hdmi_tx_c0_rtl_0layer1 .......
Finished optimization stage 2 on tx_fifo_top_work_hdmi_tx_c0_rtl_0layer1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on HDMI_TX_Native_1 .......
Finished optimization stage 2 on HDMI_TX_Native_1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on HDMI_TX_1_0 .......
@N:CL159 : HDMI_TX.vhd(44) | Input TDATA_I is unused.
@N:CL159 : HDMI_TX.vhd(47) | Input TVALID_I is unused.
@N:CL159 : HDMI_TX.vhd(49) | Input TUSER_I is unused.
Finished optimization stage 2 on HDMI_TX_1_0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on HDMI_TX_C0 .......
Finished optimization stage 2 on HDMI_TX_C0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on YCbCr_422to444_8_8 .......
Finished optimization stage 2 on YCbCr_422to444_8_8 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on YCbCr2RGB_8_8 .......
Finished optimization stage 2 on YCbCr2RGB_8_8 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on YCbCrtoRGB_8_8_2_0_1 .......
Finished optimization stage 2 on YCbCrtoRGB_8_8_2_0_1 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)
Running optimization stage 2 on YCbCrtoRGB_C0 .......
Finished optimization stage 2 on YCbCrtoRGB_C0 (CPU Time 0h:00m:00s, Memory Used current: 141MB peak: 146MB)

For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File:  layer1.rt.csv


At c_vhdl Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 141MB peak: 146MB)


Process completed successfully.
# Mon Nov 21 15:25:53 2022

###########################################################]
###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 10 or later
Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp2, Build 152R, Built Jun 14 2022 11:35:28, @

@N: :  | Running in 64-bit mode 
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

=======================================================================================
For a summary of linker messages for components that did not bind, please see log file:
Linked File:  SEV_PFSoC_OpenVX_comp.linkerlog
=======================================================================================


At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 183MB peak: 185MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Mon Nov 21 15:25:55 2022

###########################################################]

For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File:  SEV_PFSoC_OpenVX_comp.rt.csv

@END

At c_hdl Exit (Real Time elapsed 0h:01m:14s; CPU Time elapsed 0h:01m:14s; Memory used current: 25MB peak: 27MB)

Process took 0h:01m:14s realtime, 0h:01m:14s cputime

Process completed successfully.
# Mon Nov 21 15:25:55 2022

###########################################################]

###########################################################[

Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 10 or later
Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202109synp2, Build 152R, Built Jun 14 2022 11:35:28, @

@N: :  | Running in 64-bit mode 
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances: slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances: mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 234MB peak: 236MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime

Process completed successfully.
# Mon Nov 21 15:25:58 2022

###########################################################]

Premap Report

# Mon Nov 21 15:25:59 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys Microchip Technology Pre-mapping, Version map202109actsp1, Build 056R, Built Jun 14 2022 13:56:21, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)


Done reading skeleton netlist (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 184MB peak: 184MB)

Reading constraint file: D:\Delme\SEV_PFSoC_OpenVX\designer\SEV_PFSoC_OpenVX\synthesis.fdc
Linked File:  SEV_PFSoC_OpenVX_scck.rpt
See clock summary report "D:\Delme\SEV_PFSoC_OpenVX\synthesis\SEV_PFSoC_OpenVX_scck.rpt"
@N:MF472 :  | Synthesis running in Automatic Compile Point mode 
@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 289MB peak: 289MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 289MB peak: 289MB)

@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

Start loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 297MB peak: 297MB)


Finished loading timing files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 297MB peak: 299MB)

@W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_50MHz.CORERESET_PF_C3_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W:BN114 : pf_osc_c0_pf_osc_c0_0_pf_osc.v(15) | Removing instance gnd_inst (in view: work.PF_OSC_C0_PF_OSC_C0_0_PF_OSC(verilog)) because it does not drive other instances.
@W:BN114 : pf_xcvr_ref_clk_c0_pf_xcvr_ref_clk_c0_0_pf_xcvr_ref_clk.v(26) | Removing instance vcc_inst (in view: work.PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK(verilog)) because it does not drive other instances.
@W:BN114 : pf_xcvr_ref_clk_c0_pf_xcvr_ref_clk_c0_0_pf_xcvr_ref_clk.v(27) | Removing instance gnd_inst (in view: work.PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK(verilog)) because it does not drive other instances.
@W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance DDR4_RD_WR_inst_0.CORERESET_PF_148p5MHz.CORERESET_PF_C0_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W:BN132 : data_packer_lpddr4.vhd(205) | Removing sequential instance DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_dv_fe_ctr_en because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_ddr_start. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C2_0.CORERESET_PF_C2_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W:BN114 : pf_iod_generic_rx_c0_pf_iod_clk_training_pf_iod.v(32) | Removing instance vcc_inst (in view: work.PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD(verilog)) because it does not drive other instances.
@W:BN114 : pf_iod_generic_rx_c0_pf_iod_rx_pf_iod.v(262) | Removing instance vcc_inst (in view: work.PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD(verilog)) because it does not drive other instances.
@W:FX1172 : hdmi_tx.vhd(756) | User-specified initial value defined for instance DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST.TMDS_B_generate.1.tmds_b.dc_bias[3:0] is being ignored due to limitations in architecture. 
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ASIZE[2:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.ASIZE_reg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.max_length_comb_pre[8:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ASIZE[2:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.max_length_comb_pre[8:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

Starting HSTDM IP insertion (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 342MB peak: 342MB)


Finished HSTDM IP insertion (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 342MB peak: 343MB)

@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

Start optimization across hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 343MB peak: 343MB)

NConnInternalConnection caching in on
@W:MO129 : corerxiodbitalign.v(1099) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.CORERXIODBITALIGN_C0_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@N:BN362 : corerxiodbitalign.v(1352) | Removing sequential instance rx_BIT_ALGN_ERR (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_LEFT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_RGHT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1344) | Removing sequential instance RX_BIT_ALIGN_TAPDLY[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(269) | Removing sequential instance bit_align_start (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@W:MO129 : corerxiodbitalign.v(1099) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@N:BN362 : corerxiodbitalign.v(1352) | Removing sequential instance rx_BIT_ALGN_ERR (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_LEFT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_RGHT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1344) | Removing sequential instance RX_BIT_ALIGN_TAPDLY[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(269) | Removing sequential instance bit_align_start (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@W:MO129 : corerxiodbitalign.v(1099) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@N:BN362 : corerxiodbitalign.v(1352) | Removing sequential instance rx_BIT_ALGN_ERR (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_LEFT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_RGHT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1344) | Removing sequential instance RX_BIT_ALIGN_TAPDLY[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(269) | Removing sequential instance bit_align_start (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@W:MO129 : corerxiodbitalign.v(1099) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@N:BN362 : corerxiodbitalign.v(1352) | Removing sequential instance rx_BIT_ALGN_ERR (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_LEFT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1392) | Removing sequential instance RX_BIT_ALIGN_RGHT_WIN[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(1344) | Removing sequential instance RX_BIT_ALIGN_TAPDLY[7:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : corerxiodbitalign.v(269) | Removing sequential instance bit_align_start (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:MO111 : corebclksclkalign.v(82) | Tristate driver PLL_VCOPHSEL_SCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_VCOPHSEL_SCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(85) | Tristate driver PLL_VCOPHSEL_MCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_VCOPHSEL_MCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(83) | Tristate driver PLL_VCOPHSEL_BCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_VCOPHSEL_BCLK_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(84) | Tristate driver PLL_VCOPHSEL_BCLK90_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_VCOPHSEL_BCLK90_SEL (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(87) | Tristate driver PLL_PHS_ROTATE (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_PHS_ROTATE (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(88) | Tristate driver PLL_PHS_DIRECTION (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_PHS_DIRECTION (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(86) | Tristate driver PLL_LOADPHS (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net PLL_LOADPHS (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(99) | Tristate driver BCLKSCLK_BCLK_VCOPHSEL_7 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net BCLKSCLK_BCLK_VCOPHSEL_7 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(99) | Tristate driver BCLKSCLK_BCLK_VCOPHSEL_6 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net BCLKSCLK_BCLK_VCOPHSEL_6 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@N:MO111 : corebclksclkalign.v(99) | Tristate driver BCLKSCLK_BCLK_VCOPHSEL_5 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) on net BCLKSCLK_BCLK_VCOPHSEL_5 (in view: work.PF_IOD_GENERIC_RX_C0_TR_PF_IOD_GENERIC_RX_C0_TR_0_COREBCLKSCLKALIGN_Z8_layer0(verilog)) has its enable tied to GND.
@W:MO129 : icb_bclksclkalign.v(660) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.PF_IOD_GENERIC_RX_C0_TR_0.genblk1.U_ICB_BCLKSCLKALIGN.internal_rst_en_2 is reduced to a combinational gate by constant propagation.
@W:MO129 : icb_bclksclkalign.v(652) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.PF_IOD_GENERIC_RX_C0_TR_0.genblk1.U_ICB_BCLKSCLKALIGN.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@N:BN362 : icb_bclksclkalign.v(829) | Removing sequential instance RX_CLK_ALIGN_START (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : icb_bclksclkalign.v(821) | Removing sequential instance RX_CLK_ALIGN_ERR (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : icb_bclksclkalign.v(815) | Removing sequential instance RX_CLK_ALIGN_TAPDLY[7:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : icb_bclksclkalign.v(1112) | Removing sequential instance clk_align_start (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrfull (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6543) | Removing sequential instance rdusedw[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrusedw_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_rr[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrfull (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6543) | Removing sequential instance rdusedw[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrusedw_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_rr[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrfull (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6543) | Removing sequential instance rdusedw[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrusedw_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_rr[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrfull (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6543) | Removing sequential instance rdusedw[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance wrusedw_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_rr[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(6450) | Removing sequential instance rdaddr_sync_r[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[2] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[3] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[4] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_o_2[5] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1588) | Removing sequential instance virtual_channel_o_2[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1588) | Removing sequential instance virtual_channel_o_2[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1548) | Removing sequential instance ecc_error_o (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[2] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[3] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[4] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[5] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[6] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[7] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[8] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[9] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[10] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[11] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[12] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[13] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[14] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_o_2[15] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1484) | Removing sequential instance frame_end_o (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1125) | Removing sequential instance genblk2\.frame_number_o[15:0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[2] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[3] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[4] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg2_1[5] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1588) | Removing sequential instance virtual_channel_reg2_1[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1588) | Removing sequential instance virtual_channel_reg2_1[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1548) | Removing sequential instance ecc_error_reg2 (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[2] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[3] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[4] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[5] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[6] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[7] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[8] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[9] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[10] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[11] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[12] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[13] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[14] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1569) | Removing sequential instance word_count_reg2_1[15] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg1_0[0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg1_0[1] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg1_0[2] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:BN362 : mipicsi2rxdecoderpf.v(1514) | Removing sequential instance data_type_reg1_0[3] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\synlog\SEV_PFSoC_OpenVX_premap.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.
@W:BN117 : rgbtoycbcr_c0.vhd(127) | Instance RGBtoYCbCr_C0_0 of partition view:work.RGBtoYCbCr_8_8_2_0_1(rtl) has no references to its outputs; instance not removed. 
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req1_dly is reduced to a combinational gate by constant propagation.
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req2_dly is reduced to a combinational gate by constant propagation.
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req3_dly is reduced to a combinational gate by constant propagation.
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req1_dly is reduced to a combinational gate by constant propagation.
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req2_dly is reduced to a combinational gate by constant propagation.
@W:MO129 : request_scheduler.vhd(121) | Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req3_dly is reduced to a combinational gate by constant propagation.
@W:BN117 : ycbcrtorgb_c0.vhd(137) | Instance YCbCrtoRGB_C0_0 of partition view:work.YCbCrtoRGB_8_8_2_0_1(rtl) has no references to its outputs; instance not removed. 
@W:MO129 : dwc_downconv_precalccmdfifowrctrl.v(126) | Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.unaligned_fixed_len_iter_pre[0] is reduced to a combinational gate by constant propagation.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.mask_addr_pre_1[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ABURST_out[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ASIZE_out[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_out[31:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[31:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.MASTER_ABURST_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.MASTER_ASIZE_reg[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.max_length[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.length[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN115 : dwc_downconv_readwidthconv.v(489) | Removing instance genblk1\.byte2bit_inst (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@W:MO129 : dwc_downconv_precalccmdfifowrctrl.v(126) | Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.unaligned_fixed_len_iter_pre[0] is reduced to a combinational gate by constant propagation.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.mask_addr_pre_1[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ABURST_out[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ASIZE_out[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[31:9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_out[31:9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.MASTER_ABURST_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.max_length[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.length[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.MASTER_ASIZE_reg[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.ASIZE_reg[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:MO129 : dwc_downconv_widthconvwr.v(377) | Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WUSER[0] is reduced to a combinational gate by constant propagation.
@W:MO129 : dwc_downconv_widthconvwr.v(915) | Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.fixed_burst_f1 is reduced to a combinational gate by constant propagation.
@W:MO129 : dwc_downconv_widthconvwr.v(907) | Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.fixed_burst_det_reg is reduced to a combinational gate by constant propagation.
@N:BN115 : masterconvertor.v(637) | Removing instance genblk2\.mstrProtConv (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N:BN115 : masterconvertor.v(871) | Removing instance mstrCDC (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N:BN115 : slaveconvertor.v(522) | Removing instance slvdwc (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)) because it does not drive other instances.
@N:BN115 : slaveconvertor.v(754) | Removing instance slvCDC (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)) because it does not drive other instances.
@N:BN115 : coreaxi4interconnect.v(9615) | Removing instance axicb (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) because it does not drive other instances.
@N:BN115 : fifo.v(98) | Removing instance genblk1\[0\]\.ram (in view: work.caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s_0(verilog)) because it does not drive other instances.
@N:BN115 : fifo.v(98) | Removing instance genblk1\[0\]\.ram (in view: work.caxi4interconnect_FIFO_256s_5s_5s_255s_0s_256s_8s_0s_255s_1(verilog)) because it does not drive other instances.

Finished optimization across hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 346MB peak: 346MB)

@N:FP130 :  | Promoting Net CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_arst on CLKINT  I_2  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND2_0_Y_arst on CLKINT  I_1  
@N:FP130 :  | Promoting Net FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.arst_aclk_sync.sysReset_arst on CLKINT  I_2  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_arst on CLKINT  I_2  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C2_0.CORERESET_PF_C2_0.dff_arst on CLKINT  I_2  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_FIFO_Y on CLKINT  I_1  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.RX_DQS_90[0] on CLKINT  I_1  
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_CASCADED_Y on CLKINT  I_2  
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@N:FX1185 :  | Applying syn_allowed_resources blockrams=4 on compile point embsync_detect_Z1_layer0  
@N:FX1185 :  | Applying syn_allowed_resources blockrams=8 on compile point IMX334_IF_TOP  
@N:FX1185 :  | Applying syn_allowed_resources blockrams=163,dsps=51 on compile point DDR4_RD_WR  
@N:FX1185 :  | Applying syn_allowed_resources blockrams=2 on compile point caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s  
@N:FX1185 :  | Applying syn_allowed_resources blockrams=3 on compile point caxi4interconnect_MasterConvertor_Z22_layer0  
@N:FX1184 :  | Applying syn_allowed_resources blockrams=812,dsps=733 on top level netlist SEV_PFSoC_OpenVX  

Finished netlist restructuring (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 355MB peak: 355MB)



Clock Summary
******************

          Start                                                                                               Requested     Requested     Clock                              Clock                Clock
Level     Clock                                                                                               Frequency     Period        Type                               Group                Load 
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0 -       CAM1_RX_CLK_P                                                                                       250.0 MHz     4.000         declared                           default_clkgroup     13   
1 .         DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     62.5 MHz      16.000        generated (from CAM1_RX_CLK_P)     default_clkgroup     5097 
2 ..          DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                       170.0 MHz     5.882         generated (from CAM1_RX_CLK_P)     default_clkgroup     2015 
                                                                                                                                                                                                       
0 -       REF_CLK_PAD_P                                                                                       148.5 MHz     6.734         declared                           default_clkgroup     1    
1 .         CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                                  50.0 MHz      20.000        generated (from REF_CLK_PAD_P)     default_clkgroup     118  
2 ..          CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                                200.0 MHz     5.000         generated (from REF_CLK_PAD_P)     default_clkgroup     6437 
                                                                                                                                                                                                       
0 -       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                            74.3 MHz      13.468        declared                           default_clkgroup     1048 
                                                                                                                                                                                                       
0 -       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                            74.3 MHz      13.468        declared                           default_clkgroup     37   
                                                                                                                                                                                                       
0 -       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                            74.3 MHz      13.468        declared                           default_clkgroup     37   
                                                                                                                                                                                                       
0 -       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                            74.3 MHz      13.468        declared                           default_clkgroup     37   
                                                                                                                                                                                                       
0 -       CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK                                        2.0 MHz       500.000       declared                           default_clkgroup     1    
                                                                                                                                                                                                       
0 -       System                                                                                              100.0 MHz     10.000        system                             system_clkgroup      0    
=======================================================================================================================================================================================================



Clock Load Summary
***********************

                                                                                                  Clock     Source                                                                                                             Clock Pin                                                                                                                                                                                                            Non-clock Pin     Non-clock Pin                                                                                    
Clock                                                                                             Load      Pin                                                                                                                Seq Example                                                                                                                                                                                                          Seq Example       Comb Example                                                                                     
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CAM1_RX_CLK_P                                                                                     13        CAM1_RX_CLK_P(port)                                                                                                DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1]                                                                                                              -                 DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_CASCADED.A(HS_IO_CLK)
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     5097      DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_CLK_DIV_FIFO.I_CDD.Y_DIV(ICB_CLKDIVDELAY)     DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL.FAB_CLK                                                                                                                   -                 DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.CLKINT_0.I(BUFG)               
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                         2015      DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_CCC_C2_0.PF_CCC_C2_0.pll_inst_0.OUT0(PLL)                                     DDR4_RD_WR_inst_0.video_processing_0.Bayer_Interpolation_C0_0.Bayer_Interpolation_C0_0.Bayer_Native_FORMAT\.Bayer_Native_INST_0.bayer_interpolation_1pix\.Bayer_Interpolation_1pix_inst.RAM3_INST.q_b_reg[7:0].C     -                 DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_CCC_C2_0.PF_CCC_C2_0.clkint_0.I(BUFG)                       
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
REF_CLK_PAD_P                                                                                     1         REF_CLK_PAD_P(port)                                                                                                CLOCKS_AND_RESETS_inst_0.PF_CCC_C0_0.PF_CCC_C0_0.pll_inst_0.REF_CLK_0                                                                                                                                                -                 CLOCKS_AND_RESETS_inst_0.PF_XCVR_REF_CLK_C0_0.PF_XCVR_REF_CLK_C0_0.I_IO.PAD_P(XCVR_REF_CLK)      
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                                  118       CLOCKS_AND_RESETS_inst_0.PF_CCC_C0_0.PF_CCC_C0_0.pll_inst_0.OUT0(PLL)                                              MSS.I_MSS.FIC_3_PCLK                                                                                                                                                                                                 -                 CLOCKS_AND_RESETS_inst_0.PF_CCC_C0_0.PF_CCC_C0_0.clkint_0.I(BUFG)                                
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                                  6437      CLOCKS_AND_RESETS_inst_0.PF_CCC_C1_0.PF_CCC_C1_0.pll_inst_0.OUT0(PLL)                                              MSS.I_MSS.FIC_1_ACLK                                                                                                                                                                                                 -                 CLOCKS_AND_RESETS_inst_0.PF_CCC_C1_0.PF_CCC_C1_0.clkint_0.I(BUFG)                                
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                          1048      DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE0.TX_CLK_R(XCVR_PMA)                                                 DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_h_active_dly.C                                                                                -                 DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE0_TX_rclkint.A(RCLKINT)                            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                          37        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1.TX_CLK_R(XCVR_PMA)                                                 DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.rwptr2[6:0].C                                                                                   -                 DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1_TX_rclkint.A(RCLKINT)                            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                          37        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2.TX_CLK_R(XCVR_PMA)                                                 DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.rwptr2[6:0].C                                                                                   -                 DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2_TX_rclkint.A(RCLKINT)                            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                          37        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3.TX_CLK_R(XCVR_PMA)                                                 DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.rwptr2[6:0].C                                                                                   -                 DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3_TX_rclkint.A(RCLKINT)                            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK                                      1         CLOCKS_AND_RESETS_inst_0.PF_OSC_C0_0.PF_OSC_C0_0.I_OSC_2.CLK(OSC_RC2MHZ)                                           CLOCKS_AND_RESETS_inst_0.PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD.A                                                                                                                                                      -                 -                                                                                                
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
System                                                                                            0         -                                                                                                                  -                                                                                                                                                                                                                    -                 -                                                                                                
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================

@N:FX1143 :  | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. 
Finished Pre Mapping Phase.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@N:BN225 :  | Writing default property annotation file D:\Delme\SEV_PFSoC_OpenVX\synthesis\SEV_PFSoC_OpenVX.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:22s; Memory used current: 327MB peak: 355MB)

Encoding state machine s_state[0:2] (in view: work.DDR_read_controller_FHD_HDMI_RX(ddr_read_controller_hdmi_rx))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine s_state[0:2] (in view: work.DDR_write_controller_lpddr4(ddr_write_controller))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine local_wbus_state[3:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : ddr_rw_arbiter_lpddr4.v(303) | There are no possible illegal states for state machine local_wbus_state[3:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine video_bus_state[4:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog))
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   101 -> 01000
   110 -> 10000
Encoding state machine s_state[0:5] (in view: work.request_scheduler_0(request_scheduler))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
Encoding state machine s_state[0:5] (in view: work.request_scheduler_1(request_scheduler))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
Encoding state machine s_state[0:3] (in view: work.READ_LSRAM_8_16(read_lsram))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : bayer_interpolation.vhd(2090) | There are no possible illegal states for state machine s_state[0:3] (in view: work.READ_LSRAM_8_16(read_lsram)); safe FSM implementation is not required.
Encoding state machine genblk1\.state_enb[3:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   100 -> 11
@N:MO225 : mipicsi2rxdecoderpf.v(1986) | There are no possible illegal states for state machine genblk1\.state_enb[3:0] (in view: work.embsync_detect_Z1_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\.state_3[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_2[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_1[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_0[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk7\.pix_distribute_4lane[3:0] (in view: work.byte2pixel_conversion_Z2_layer0(verilog))
original code -> new code
   000 -> 000
   001 -> 001
   010 -> 010
   011 -> 011
Encoding state machine genblk2\.state_FS[5:0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
Encoding state machine clkalign_curr_state[63:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog))
original code -> new code
   000000 -> 000000
   000001 -> 000001
   000010 -> 000011
   000011 -> 000010
   000100 -> 000110
   000101 -> 000111
   000110 -> 000101
   000111 -> 000100
   001000 -> 001100
   001001 -> 001101
   001010 -> 001111
   001011 -> 001110
   001100 -> 001010
   001101 -> 001011
   001110 -> 001001
   001111 -> 001000
   010000 -> 011000
   010001 -> 011001
   010010 -> 011011
   010011 -> 011010
   010100 -> 011110
   010101 -> 011111
   010110 -> 011101
   010111 -> 011100
   011000 -> 010100
   011001 -> 010101
   011010 -> 010111
   011011 -> 010110
   011100 -> 010010
   011101 -> 010011
   011110 -> 010001
   011111 -> 010000
   100000 -> 110000
   100001 -> 110001
   100010 -> 110011
   100011 -> 110010
   100100 -> 110110
   100101 -> 110111
   100110 -> 110101
   100111 -> 110100
   101000 -> 111100
   101001 -> 111101
   101010 -> 111111
   101011 -> 111110
   101100 -> 111010
   101101 -> 111011
   101110 -> 111001
   101111 -> 111000
   110000 -> 101000
   110001 -> 101001
   110010 -> 101011
   110011 -> 101010
   110100 -> 101110
   110101 -> 101111
   110110 -> 101101
   110111 -> 101100
   111000 -> 100100
   111001 -> 100101
   111010 -> 100111
   111011 -> 100110
   111100 -> 100010
   111101 -> 100011
   111110 -> 100001
   111111 -> 100000
@N:MO225 : icb_bclksclkalign.v(214) | There are no possible illegal states for state machine clkalign_curr_state[63:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_67s_0_1_3_1(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_67s_0_1_3_1(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_67s_0_1_3_0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_67s_0_1_3_0(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_72s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_72s_0_1_3_2(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_78s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_78s_0_1_3_2(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_7s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_7s_0_1_3_2(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_68s_0_1_3_1(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_68s_0_1_3_1(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_68s_0_1_3_0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_68s_0_1_3_0(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_73s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_73s_0_1_3_2(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_79s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_79s_0_1_3_2(verilog)); safe FSM implementation is not required.
Encoding state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_8s_0_1_3_2(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine currState[3:0] (in view: work.caxi4interconnect_RegSliceFull_8s_0_1_3_2(verilog)); safe FSM implementation is not required.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W:BN108 : slaveconvertor.v(24) | syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W:BN108 : masterconvertor.v(23) | syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.

Finished constraint checker preprocessing (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 352MB peak: 355MB)

@W:MF511 :  | Found issues with constraints. Please check constraint checker report "D:\Delme\SEV_PFSoC_OpenVX\synthesis\SEV_PFSoC_OpenVX_cck.rpt" . 

Finished constraint checker (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:27s; Memory used current: 353MB peak: 373MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:27s; Memory used current: 218MB peak: 373MB)

Process took 0h:00m:27s realtime, 0h:00m:27s cputime
# Mon Nov 21 15:26:27 2022

###########################################################]

Map & Optimize Report

# Mon Nov 21 15:26:27 2022


Copyright (C) 1994-2021 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: S-2021.09M-SP1
Install: D:\Microchip\Libero_SoC_v2022.2\SynplifyPro
OS: Windows 6.2

Hostname: HYD-LT-I52882B

Implementation : synthesis
Synopsys Microchip Technology Mapper, Version map202109actsp1, Build 056R, Built Jun 14 2022 13:56:21, @


Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 120MB)

@N:MF916 :  | Option synthesis_strategy=base is enabled.  
@N:MF248 :  | Running in 64-bit mode. 
@N:MF667 :  | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 132MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 132MB)


Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 125MB peak: 132MB)


Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 127MB peak: 132MB)


@N:MF104 : mipicsi2rxdecoderpf.v(1677) | Found compile point of type hard on View view:work.embsync_detect_Z1_layer0(verilog) 
@N:MF104 : imx334_if_top.v(9) | Found compile point of type hard on View view:work.IMX334_IF_TOP(verilog) 
@N:MF104 : ddr4_rd_wr.v(9) | Found compile point of type hard on View view:work.DDR4_RD_WR(verilog) 
@N:MF104 : dwc_downconv_readwidthconv.v(20) | Found compile point of type hard on View view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) 
@N:MF104 : masterconvertor.v(23) | Found compile point of type hard on View view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) 

Synthesis running in Multiprocessing mode
Maximum number of parallel jobs set to 4
Multiprocessing started at : Mon Nov 21 15:26:29 2022
Mapping IMX334_IF_TOP as a separate process
Mapping DDR4_RD_WR as a separate process
Mapping embsync_detect_Z1_layer0 as a separate process
@W:BN114 :  | Removing instance CP_fanout_cell_SEV_PFSoC_OpenVX_verilog_inst (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0_acp(verilog)) because it does not drive other instances. 
Mapping caxi4interconnect_MasterConvertor_Z22_layer0 as a separate process
MCP Status: 4 jobs running

@N:MF106 : mipicsi2rxdecoderpf.v(1677) | Mapping Compile point view:work.embsync_detect_Z1_layer0(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 172MB peak: 172MB)

@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_3 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_3 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_4 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_4 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_5 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_5 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_6 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_6 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_7 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_7 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1709) | Tristate driver L7_DATA_O_8 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_8 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1708) | Tristate driver L6_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L6_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(1708) | Tristate driver L6_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L6_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.

#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 176MB peak: 176MB)

Encoding state machine genblk1\.state_enb[3:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   000 -> 00
   001 -> 01
   010 -> 10
   100 -> 11
@N:MO225 : mipicsi2rxdecoderpf.v(1986) | There are no possible illegal states for state machine genblk1\.state_enb[3:0] (in view: work.embsync_detect_Z1_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine genblk1\.state_3[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_2[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_1[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine genblk1\.state_0[2:0] (in view: work.embsync_detect_Z1_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MO231 : mipicsi2rxdecoderpf.v(1986) | Found counter in view:work.embsync_detect_Z1_layer0(verilog) instance genblk1\.word_counter[16:2] 
@W:FX107 : mipicsi2rxdecoderpf.v(6641) | RAM dcram.ram_block[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : mipicsi2rxdecoderpf.v(6641) | RAM dcram.ram_block[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : mipicsi2rxdecoderpf.v(6641) | RAM dcram.ram_block[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_2(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : mipicsi2rxdecoderpf.v(6641) | RAM dcram.ram_block[7:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967288s_8s_1_3_3(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 179MB peak: 179MB)


Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 188MB peak: 188MB)


Available hyper_sources - for debug and ip models
	None Found


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 184MB peak: 189MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 185MB peak: 189MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 185MB peak: 189MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 185MB peak: 189MB)


Finished preparing to map (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 185MB peak: 189MB)


Finished technology mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 186MB peak: 189MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:05s		     1.77ns		 985 /       788

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 187MB peak: 189MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 187MB peak: 189MB)


Finished mapping embsync_detect_Z1_layer0
Mapping SEV_PFSoC_OpenVX as a separate process
MCP Status: 4 jobs running

@N:MF106 : masterconvertor.v(23) | Mapping Compile point view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB)

@W:BN114 :  | Removing instance CP_fanout_cell_work_caxi4interconnect_MasterConvertor_Z22_layer0_verilog_0_0_inst (in view: work.SEV_PFSoC_OpenVX(verilog)) because it does not drive other instances. 
@W:BN114 :  | Removing instance CP_fanout_cell_work_caxi4interconnect_MasterConvertor_Z22_layer0_verilog_0_0_0_inst (in view: work.SEV_PFSoC_OpenVX(verilog)) because it does not drive other instances. 
Dissolving instances under view:work.caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s(verilog) (flattening)


#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)

Encoding state machine DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.SEV_PFSoC_OpenVX(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : ddr_rw_arbiter_lpddr4.v(303) | There are no possible illegal states for state machine DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.SEV_PFSoC_OpenVX(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk5.brs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk5.brs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk5.brs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk5.brs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk4.wrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk4.wrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk3.rrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk3.rrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk2.arrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk2.arrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk2.arrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk2.arrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk1.awrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk1.awrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk3.rrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk3.rrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk1.awrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk1.awrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk4.wrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.rgsl.genblk4.wrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[1] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[0] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[2] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[1] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[0] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[12] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[2] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:FX107 : ram_block.v(65) | RAM genblk1\[0\]\.ram.mem[32:0] (in view: work.caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MO231 : dwc_downconv_widthconvwr.v(428) | Found counter in view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog) instance sizeCnt_reg[5:0] 
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[5] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[4] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[3] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[2] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[1] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvwr.v(958) | Register bit fixed_burst_sizecnt[0] (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@N:BN362 : dwc_downconv_widthconvwr.v(884) | Removing sequential instance slave_wrdone (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N:MF179 : dwc_downconv_widthconvwr.v(937) | Found 9 by 9 bit equality operator ('==') cnt_match (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog))
@N:MF179 : dwc_downconv_widthconvwr.v(938) | Found 9 by 9 bit equality operator ('==') un4_cnt_match_next (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog))
@W:MO160 : dwc_downconv_widthconvwr.v(979) | Register bit fixed_valid_data_reg (in view view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[15] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[14] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[13] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[12] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[11] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[10] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[7] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[30] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[29] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[28] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[27] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[26] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[25] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[24] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[23] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[22] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[21] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[20] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[19] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[18] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[17] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[16] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[45] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[44] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[43] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[42] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[41] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[40] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[39] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[38] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[37] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[36] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[35] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[34] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[33] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[32] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[31] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[60] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[59] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[58] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[57] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[56] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[55] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[54] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[53] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[52] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[51] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[50] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[49] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[48] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[47] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[46] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[63] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[62] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[61] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[7] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(377) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WSTRB[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:FX107 : ram_block.v(65) | RAM genblk1\[0\]\.ram.mem[0] (in view: work.caxi4interconnect_FIFO_64s_5s_5s_63s_128s_64s_6s_128s_63s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[12] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.mask_addr_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.mask_addr_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.mask_addr_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Starting factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 194MB peak: 194MB)

@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.sizeCnt_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Only the first 100 messages of id 'BN132' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\caxi4interconnect_MasterConvertor_Z22_layer0\caxi4interconnect_MasterConvertor_Z22_layer0.srr -id BN132' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN132} -count unlimited' in the Tcl shell.
Auto Dissolve of widthConvwr (inst of view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog))
@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance wrCmdFifoWriteCtrl.SizeMax_reg[3] (in view: work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 200MB peak: 200MB)


Available hyper_sources - for debug and ip models
	None Found

@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[34] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 203MB peak: 203MB)

@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[29] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.fixed_flag (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 204MB peak: 204MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 204MB peak: 204MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 204MB peak: 205MB)


Finished preparing to map (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 205MB peak: 205MB)


Finished technology mapping (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 209MB peak: 209MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:16s		    -2.98ns		1502 /      1892
   2		0h:00m:16s		    -2.98ns		1437 /      1892
   3		0h:00m:16s		    -2.64ns		1437 /      1892
@N:FX271 : regslicefull.v(185) | Replicating instance rgsl.genblk4\.wrs.currState[0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 11 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY_2 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 515 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(396) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WVALID (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 8 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(396) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WLAST (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.SEV_PFSoC_OpenVX(verilog)) with 514 loads 3 times to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 9 LUTs via timing driven replication

   4		0h:00m:17s		    -2.54ns		1449 /      1895
   5		0h:00m:17s		    -2.32ns		1449 /      1895
   6		0h:00m:17s		    -2.24ns		1449 /      1895
   7		0h:00m:18s		    -2.24ns		1450 /      1895
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY_2 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(396) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.cnt_eq_0 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 11 loads 1 time to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep2 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep1 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_fast (in view: work.SEV_PFSoC_OpenVX(verilog)) with 127 loads 3 times to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 16 LUTs via timing driven replication


   8		0h:00m:18s		    -2.03ns		1466 /      1896

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 212MB peak: 212MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 213MB peak: 213MB)


Finished mapping caxi4interconnect_MasterConvertor_Z22_layer0
@W:BN114 :  | Removing instance CP_fanout_cell_SEV_PFSoC_OpenVX_verilog_inst (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s_acp(verilog)) because it does not drive other instances. 
Mapping caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s as a separate process
MCP Status: 4 jobs running

@N:MF106 : dwc_downconv_readwidthconv.v(20) | Mapping Compile point view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 179MB peak: 179MB)

@W:BN114 :  | Removing instance CP_fanout_cell_work_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s_verilog_inst (in view: work.SEV_PFSoC_OpenVX(verilog)) because it does not drive other instances. 

#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 184MB peak: 184MB)

@N:MO231 : dwc_downconv_widthconvrd.v(408) | Found counter in view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance genblk1\.widthConvrd.sizeCnt_reg[5:0] 
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[2] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[1] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_widthconvrd.v(620) | Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[0] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_hold_reg_rd.v(80) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_hold_reg_rd.v(80) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_hold_reg_rd.v(80) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:FX107 : ram_block.v(65) | RAM genblk1\[0\]\.ram.mem[23:0] (in view: work.caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MO231 : fifo_ctrl.v(98) | Found counter in view:work.caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance rdptr[5:0] 
@N:MO231 : fifo_ctrl.v(98) | Found counter in view:work.caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance wrptr[5:0] 
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[12] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 191MB peak: 191MB)

@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[39] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[38] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[37] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[10] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_cmdfifowritectrl.v(522) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[11] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance rdCmdFifoWriteCtrl.SizeMax_reg[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:04s; Memory used current: 200MB peak: 200MB)


Available hyper_sources - for debug and ip models
	None Found

@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance rdCmdFifoWriteCtrl.CmdFifoWrData[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:05s; Memory used current: 198MB peak: 201MB)

@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance rdCmdFifoWriteCtrl.CmdFifoWrData[29] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N:BN362 : dwc_downconv_cmdfifowritectrl.v(522) | Removing sequential instance rdCmdFifoWriteCtrl.fixed_flag (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[11] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it is equivalent to instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[12] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it is equivalent to instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.

Starting Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 198MB peak: 201MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 211MB peak: 211MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 211MB peak: 212MB)

@W:BN132 : dwc_downconv_hold_reg_rd.v(80) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : dwc_downconv_hold_reg_rd.v(80) | Removing sequential instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.

Finished preparing to map (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 211MB peak: 212MB)

@N:BN362 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[7] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N:BN362 : dwc_downconv_precalccmdfifowrctrl.v(126) | Removing sequential instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.

Finished technology mapping (Real Time elapsed 0h:00m:21s; CPU Time elapsed 0h:00m:21s; Memory used current: 229MB peak: 245MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:21s		    -0.69ns		1459 /       796
   2		0h:00m:21s		    -0.69ns		1454 /       796
   3		0h:00m:21s		    -0.63ns		1456 /       796
   4		0h:00m:21s		    -0.63ns		1456 /       796
@N:FX271 :  | Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_4_0_a3_xx_mm[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 45 loads 3 times to improve timing. 
@N:FX271 : dwc_downconv_widthconvrd.v(426) | Replicating instance genblk1\.widthConvrd.cnt_EQ_zero (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 26 loads 2 times to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[2] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 8 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[6] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[5] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[8] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_hold_reg_rd.v(80) | Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 14 loads 2 times to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[7] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[9] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[12] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.len_latched[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(582) | Replicating instance genblk1\.widthConvrd.m3 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 46 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.SLAVE_ALEN[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 8 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_hold_reg_rd.v(80) | Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 24 loads 2 times to improve timing.
@N:FX271 : dwc_downconv_cmdfifowritectrl.v(522) | Replicating instance rdCmdFifoWriteCtrl.SLAVE_ALEN[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 6 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(569) | Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_2_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 138 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(569) | Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_3_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 136 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(408) | Replicating instance genblk1\.widthConvrd.current_addr_reg[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_hold_reg_rd.v(80) | Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.DWC_DownConv_hold_data_out[23] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N:FX271 : dwc_downconv_hold_reg_rd.v(80) | Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[2] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 18 loads 2 times to improve timing.
@N:FX271 : dwc_downconv_hold_reg_rd.v(80) | Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 17 loads 2 times to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(569) | Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 146 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(569) | Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_1_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 62 loads 3 times to improve timing.
@N:FX271 :  | Replicating instance rdCmdFifoWriteCtrl.m29_0_0 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 42 loads 2 times to improve timing. 
@N:FX271 : dwc_downconv_widthconvrd.v(581) | Replicating instance genblk1\.widthConvrd.m32_4_03_2_0 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 69 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvrd.v(605) | Replicating instance genblk1\.widthConvrd.MASTER_RDATA_next_3_i_o2_1[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 40 loads 3 times to improve timing.
Timing driven replication report
Added 26 Registers via timing driven replication
Added 41 LUTs via timing driven replication

   5		0h:00m:24s		    -0.27ns		1515 /       822
   6		0h:00m:24s		    -0.17ns		1515 /       822
   7		0h:00m:24s		    -0.13ns		1517 /       822
   8		0h:00m:25s		    -0.13ns		1519 /       822


   9		0h:00m:26s		    -0.11ns		1539 /       822
  10		0h:00m:26s		    -0.01ns		1541 /       822
  11		0h:00m:26s		     0.03ns		1544 /       822
  12		0h:00m:26s		     0.03ns		1546 /       822

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:27s; Memory used current: 230MB peak: 245MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:27s; Memory used current: 230MB peak: 245MB)


Finished mapping caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s
MCP Status: 3 jobs running

@N:MF106 : imx334_if_top.v(9) | Mapping Compile point view:work.IMX334_IF_TOP(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 194MB peak: 194MB)

@N:MO111 : mipicsi2rxdecoderpf.v(56) | Tristate driver TUSER_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(56) | Tristate driver TUSER_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(56) | Tristate driver TUSER_O_3 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_3 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(56) | Tristate driver TUSER_O_4 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_4 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(55) | Tristate driver TLAST_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TLAST_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(54) | Tristate driver TVALID_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TVALID_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(53) | Tristate driver TKEEP_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TKEEP_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(52) | Tristate driver TSTRB_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TSTRB_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(51) | Tristate driver TDATA_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TDATA_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N:MO111 : mipicsi2rxdecoderpf.v(51) | Tristate driver TDATA_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TDATA_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.

#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 199MB peak: 199MB)

Encoding state machine genblk2\.state_FS[5:0] (in view: work.mipi_csi2_rxdecoder_Z3_layer0(verilog))
original code -> new code
   0000 -> 000001
   0001 -> 000010
   0010 -> 000100
   0011 -> 001000
   0100 -> 010000
   0101 -> 100000
@N:MO231 : mipicsi2rxdecoderpf.v(1125) | Found counter in view:work.mipi_csi2_rxdecoder_Z3_layer0(verilog) instance genblk2\.pixel_count[15:2] 
Encoding state machine genblk7\.pix_distribute_4lane[3:0] (in view: work.byte2pixel_conversion_Z2_layer0(verilog))
original code -> new code
   000 -> 000
   001 -> 001
   010 -> 010
   011 -> 011
@W:MO129 : mipicsi2rxdecoderpf.v(6133) | Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.genblk7.pix_distribute_4lane[2] is reduced to a combinational gate by constant propagation.
@N:MO231 : mipicsi2rxdecoderpf.v(5888) | Found counter in view:work.byte2pixel_conversion_Z2_layer0(verilog) instance wait_count[5:0] 
@W:FX107 : mipicsi2rxdecoderpf.v(6641) | RAM dcram.ram_block[31:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MF179 : mipicsi2rxdecoderpf.v(6589) | Found 12 by 12 bit equality operator ('==') rdempty (in view: work.mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3(verilog))
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
@N:MO230 : corerxiodbitalign.v(269) | Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance tap_cnt[7:0]  
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance emflag_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance timeout_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(991) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance rst_cnt[9:0] 
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
@N:MO230 : corerxiodbitalign.v(269) | Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance tap_cnt[7:0]  
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance emflag_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance timeout_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(991) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance rst_cnt[9:0] 
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
@N:MO230 : corerxiodbitalign.v(269) | Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance tap_cnt[7:0]  
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance emflag_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance timeout_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(991) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance rst_cnt[9:0] 
Encoding state machine bitalign_curr_state[29:0] (in view: CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog))
original code -> new code
   00000 -> 000000000000000000000000000001
   00001 -> 000000000000000000000000000010
   00010 -> 000000000000000000000000000100
   00011 -> 000000000000000000000000001000
   00100 -> 000000000000000000000000010000
   00101 -> 000000000000000000000000100000
   00110 -> 000000000000000000000001000000
   00111 -> 000000000000000000000010000000
   01000 -> 000000000000000000000100000000
   01001 -> 000000000000000000001000000000
   01010 -> 000000000000000000010000000000
   01011 -> 000000000000000000100000000000
   01100 -> 000000000000000001000000000000
   01101 -> 000000000000000010000000000000
   01110 -> 000000000000000100000000000000
   01111 -> 000000000000001000000000000000
   10000 -> 000000000000010000000000000000
   10001 -> 000000000000100000000000000000
   10010 -> 000000000001000000000000000000
   10011 -> 000000000010000000000000000000
   10100 -> 000000000100000000000000000000
   10101 -> 000000001000000000000000000000
   10110 -> 000000010000000000000000000000
   10111 -> 000000100000000000000000000000
   11000 -> 000001000000000000000000000000
   11001 -> 000010000000000000000000000000
   11010 -> 000100000000000000000000000000
   11011 -> 001000000000000000000000000000
   11100 -> 010000000000000000000000000000
   11110 -> 100000000000000000000000000000
@N:MO230 : corerxiodbitalign.v(269) | Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance tap_cnt[7:0]  
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance emflag_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(269) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance timeout_cnt[7:0] 
@N:MO231 : corerxiodbitalign.v(991) | Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance rst_cnt[9:0] 
Encoding state machine clkalign_curr_state[63:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog))
original code -> new code
   000000 -> 000000
   000001 -> 000001
   000010 -> 000011
   000011 -> 000010
   000100 -> 000110
   000101 -> 000111
   000110 -> 000101
   000111 -> 000100
   001000 -> 001100
   001001 -> 001101
   001010 -> 001111
   001011 -> 001110
   001100 -> 001010
   001101 -> 001011
   001110 -> 001001
   001111 -> 001000
   010000 -> 011000
   010001 -> 011001
   010010 -> 011011
   010011 -> 011010
   010100 -> 011110
   010101 -> 011111
   010110 -> 011101
   010111 -> 011100
   011000 -> 010100
   011001 -> 010101
   011010 -> 010111
   011011 -> 010110
   011100 -> 010010
   011101 -> 010011
   011110 -> 010001
   011111 -> 010000
   100000 -> 110000
   100001 -> 110001
   100010 -> 110011
   100011 -> 110010
   100100 -> 110110
   100101 -> 110111
   100110 -> 110101
   100111 -> 110100
   101000 -> 111100
   101001 -> 111101
   101010 -> 111111
   101011 -> 111110
   101100 -> 111010
   101101 -> 111011
   101110 -> 111001
   101111 -> 111000
   110000 -> 101000
   110001 -> 101001
   110010 -> 101011
   110011 -> 101010
   110100 -> 101110
   110101 -> 101111
   110110 -> 101101
   110111 -> 101100
   111000 -> 100100
   111001 -> 100101
   111010 -> 100111
   111011 -> 100110
   111100 -> 100010
   111101 -> 100011
   111110 -> 100001
   111111 -> 100000
@N:MO225 : icb_bclksclkalign.v(214) | There are no possible illegal states for state machine clkalign_curr_state[63:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)); safe FSM implementation is not required.
@N:MO231 : icb_bclksclkalign.v(991) | Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance tapcnt_offset[7:0] 
@N:MO231 : icb_bclksclkalign.v(947) | Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance tap_cnt[7:0] 
@N:MO231 : icb_bclksclkalign.v(907) | Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance timeout_cnt[7:0] 
@N:MO231 : icb_bclksclkalign.v(1007) | Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance emflag_cnt[7:0] 
@N:MO231 : icb_bclksclkalign.v(1191) | Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance rst_cnt[9:0] 

Starting factoring (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 235MB peak: 235MB)


Finished factoring (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 266MB peak: 266MB)


Available hyper_sources - for debug and ip models
	None Found

@W:BN132 : corerxiodbitalign.v(991) | Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : corerxiodbitalign.v(991) | Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : corerxiodbitalign.v(991) | Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.CORERXIODBITALIGN_C0_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:25s; Memory used current: 246MB peak: 283MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:28s; Memory used current: 247MB peak: 283MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:33s; Memory used current: 247MB peak: 283MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:34s; Memory used current: 247MB peak: 283MB)


Finished preparing to map (Real Time elapsed 0h:00m:39s; CPU Time elapsed 0h:00m:39s; Memory used current: 248MB peak: 283MB)


Finished technology mapping (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:43s; Memory used current: 326MB peak: 326MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:44s		    -0.15ns		7622 /      4240



Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:57s; CPU Time elapsed 0h:00m:56s; Memory used current: 259MB peak: 326MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:57s; CPU Time elapsed 0h:00m:57s; Memory used current: 263MB peak: 326MB)


Finished mapping IMX334_IF_TOP
MCP Status: 2 jobs running

@N:MF106 : sev_pfsoc_openvx.v(9) | Mapping Top level view:work.SEV_PFSoC_OpenVX(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 240MB peak: 290MB)

@N:MO111 : coreaxi4interconnect.v(2737) | Tristate driver SLAVE31_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE31_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2729) | Tristate driver SLAVE30_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE30_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2721) | Tristate driver SLAVE29_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE29_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2713) | Tristate driver SLAVE28_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE28_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2705) | Tristate driver SLAVE27_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE27_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2697) | Tristate driver SLAVE26_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE26_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2689) | Tristate driver SLAVE25_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE25_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2681) | Tristate driver SLAVE24_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE24_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2673) | Tristate driver SLAVE23_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE23_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N:MO111 : coreaxi4interconnect.v(2665) | Tristate driver SLAVE22_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE22_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
Dissolving instances under view:work.caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s(verilog) (flattening)


#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:31s; CPU Time elapsed 0h:00m:31s; Memory used current: 244MB peak: 290MB)

Encoding state machine Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.DDR4_RD_WR(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : ddr_rw_arbiter_lpddr4.v(303) | There are no possible illegal states for state machine Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.DDR4_RD_WR(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : regslicefull.v(185) | There are no possible illegal states for state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : regslicefull.v(185) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.

Starting factoring (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:33s; Memory used current: 246MB peak: 290MB)


Finished factoring (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:34s; Memory used current: 246MB peak: 290MB)


Available hyper_sources - for debug and ip models
	None Found


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:37s; CPU Time elapsed 0h:00m:37s; Memory used current: 224MB peak: 290MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:38s; CPU Time elapsed 0h:00m:38s; Memory used current: 224MB peak: 290MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:40s; CPU Time elapsed 0h:00m:40s; Memory used current: 225MB peak: 290MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:41s; CPU Time elapsed 0h:00m:41s; Memory used current: 225MB peak: 290MB)


Finished preparing to map (Real Time elapsed 0h:00m:42s; CPU Time elapsed 0h:00m:42s; Memory used current: 225MB peak: 290MB)


Finished technology mapping (Real Time elapsed 0h:00m:43s; CPU Time elapsed 0h:00m:42s; Memory used current: 227MB peak: 290MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:43s		    -2.93ns		 632 /      2249
   2		0h:00m:43s		    -2.58ns		 625 /      2249
   3		0h:00m:43s		    -2.55ns		 625 /      2249
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 515 loads 3 times to improve timing.
@N:FX271 : regslicefull.v(185) | Replicating instance rgsl.genblk4\.wrs.mReady (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(129) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0 (in view: work.DDR4_RD_WR(verilog)) with 513 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.DDR4_RD_WR(verilog)) with 512 loads 3 times to improve timing.
Timing driven replication report
Added 1 Registers via timing driven replication
Added 9 LUTs via timing driven replication

   4		0h:00m:44s		    -2.94ns		 634 /      2250
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(129) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_rep1 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(129) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_rep2 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(129) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_fast (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep1 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep2 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(129) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_fast (in view: work.DDR4_RD_WR(verilog)) with 126 loads 3 times to improve timing.
Timing driven replication report
Added 0 Registers via timing driven replication
Added 27 LUTs via timing driven replication


   5		0h:00m:44s		    -2.89ns		 661 /      2250
   6		0h:00m:44s		    -2.63ns		 661 /      2250
@N:FP130 :  | Promoting Net DDR4_RD_WR_inst_0.synchronizer_circuit_0.dff_arst_i on CLKINT  I_12970  

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:45s; CPU Time elapsed 0h:00m:45s; Memory used current: 229MB peak: 290MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:55s; CPU Time elapsed 0h:00m:55s; Memory used current: 230MB peak: 290MB)


Finished mapping SEV_PFSoC_OpenVX
MCP Status: 1 jobs running

@N:MF106 : ddr4_rd_wr.v(9) | Mapping Compile point view:work.DDR4_RD_WR(verilog) because 
		 no database from previous run found.


Starting Optimization and Mapping (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 232MB)

@W:BN114 :  | Removing instance CP_fanout_cell_work_DDR4_RD_WR_verilog_inst (in view: work.SEV_PFSoC_OpenVX(verilog)) because it does not drive other instances. 
@N:MO111 : axi_lbus_ram_wrapper.v(60) | Tristate driver B_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) on net B_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(59) | Tristate driver A_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) on net A_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(58) | Tristate driver B_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) on net B_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(57) | Tristate driver A_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) on net A_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_512s_512s_8_8_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : video_axi_fifo.v(151) | Tristate driver DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0(verilog)) on net DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0(verilog)) has its enable tied to GND.
@N:MO111 : video_axi_fifo.v(150) | Tristate driver SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0(verilog)) on net SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_video_axi_fifo_Z10_layer0(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(60) | Tristate driver B_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) on net B_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(59) | Tristate driver A_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) on net A_DB_DETECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(58) | Tristate driver B_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) on net B_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) has its enable tied to GND.
@N:MO111 : axi_lbus_ram_wrapper.v(57) | Tristate driver A_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) on net A_SB_CORRECT (in view: work.ddr_rw_arbiter_C0_ddr_rw_arbiter_C0_0_ram_wrapper_16s_16s_3_3_1s_1s_2s(verilog)) has its enable tied to GND.

#### START OF SSF LOG MESSAGES ####

#### END OF SSF LOG MESSAGES ####
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 
@W:FX185 :  | Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18). 

Finished RTL optimizations (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 224MB peak: 232MB)

@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[5] (in view view:work.SEV_PFSoC_OpenVX(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[4] (in view view:work.SEV_PFSoC_OpenVX(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : dwc_downconv_precalccmdfifowrctrl.v(126) | Register bit FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[3] (in view view:work.SEV_PFSoC_OpenVX(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[21] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[20] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[19] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[18] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[17] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[16] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[15] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[14] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[13] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[12] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[11] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[10] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[7] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[36] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[35] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[34] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[33] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[32] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[31] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[30] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[29] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[28] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[27] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[26] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[25] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[24] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[23] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[22] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[51] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[50] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[49] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[48] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[47] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[46] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[45] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[44] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[43] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[42] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[41] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[40] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[39] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[38] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[37] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[63] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[62] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[61] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[60] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[59] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[58] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[57] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[56] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[55] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[54] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[53] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : dwc_downconv_widthconvwr.v(819) | Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[52] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WSTRB_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:FX107 : ram2port.vhd(22) | RAM DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l[511:0] (in view: work.DDR4_RD_WR(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : ram2port.vhd(22) | RAM DDR_Read_LPDDR4_0.video_fifo_0.ram2port_inst.io1l[511:0] (in view: work.DDR4_RD_WR(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MF179 : video_fifo.vhd(256) | Found 10 by 10 bit equality operator ('==') DDR_Write_LPDDR4_0.video_fifo_0.REMPTY_ASSIGN_PROC\.un6_rgnext (in view: work.DDR4_RD_WR(verilog))
@N:MF179 : video_fifo.vhd(359) | Found 10 by 10 bit equality operator ('==') DDR_Write_LPDDR4_0.video_fifo_0.FIFO_FULL_ASSIGN\.un5_wgnext (in view: work.DDR4_RD_WR(verilog))
@N:MF179 : video_fifo.vhd(256) | Found 13 by 13 bit equality operator ('==') DDR_Read_LPDDR4_0.video_fifo_0.REMPTY_ASSIGN_PROC\.un6_rgnext (in view: work.DDR4_RD_WR(verilog))
@N:MF179 : video_fifo.vhd(359) | Found 13 by 13 bit equality operator ('==') DDR_Read_LPDDR4_0.video_fifo_0.FIFO_FULL_ASSIGN\.un5_wgnext (in view: work.DDR4_RD_WR(verilog))
@W:BN132 : write_mux.vhd(138) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[15] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : write_mux.vhd(138) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[14] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : write_mux.vhd(138) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[13] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : write_mux.vhd(138) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[12] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : write_mux.vhd(138) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[11] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.write_mux_0.burst_size_o[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
Encoding state machine s_state[0:2] (in view: work.DDR_read_controller_FHD_HDMI_RX(ddr_read_controller_hdmi_rx))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MO231 : data_unpacker_fhd_rx_0.vhd(169) | Found counter in view:work.data_unpacker_FHD_RX(data_unpacker_fhd_rx) instance s_line_counter[15:0] 
@N:MO231 : data_unpacker_fhd_rx_0.vhd(138) | Found counter in view:work.data_unpacker_FHD_RX(data_unpacker_fhd_rx) instance s_read_counter[4:0] 
@N:MO231 : data_packer_lpddr4.vhd(153) | Found counter in view:work.data_packer_lpddr4(data_packer_arch) instance s_h_count[15:0] 
@N:MO231 : data_packer_lpddr4.vhd(233) | Found counter in view:work.data_packer_lpddr4(data_packer_arch) instance s_counter[4:0] 
Encoding state machine s_state[0:2] (in view: work.DDR_write_controller_lpddr4(ddr_write_controller))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
@N:MO231 : ddr_write_controller_lpddr4.vhd(187) | Found counter in view:work.DDR_write_controller_lpddr4(ddr_write_controller) instance s_counter[15:0] 
Encoding state machine local_wbus_state[3:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : ddr_rw_arbiter_lpddr4.v(303) | There are no possible illegal states for state machine local_wbus_state[3:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog)); safe FSM implementation is not required.
Encoding state machine video_bus_state[4:0] (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog))
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   101 -> 01000
   110 -> 10000
@N:MO231 : ddr_rw_arbiter_lpddr4.v(303) | Found counter in view:work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog) instance wd_trans_Cnt[15:0] 
@N:MO230 : axi_lbus_corefifo_sync_scntr.v(284) | Found up-down counter in view:work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog) instance v_wr_data_fifo.genblk18\.fifo_corefifo_sync_scntr.sc_r_fwft[8:0]  
@N:MO230 : axi_lbus_corefifo_sync_scntr.v(269) | Found up-down counter in view:work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog) instance v_wr_data_fifo.genblk18\.fifo_corefifo_sync_scntr.sc_r[8:0]  
@N:MO231 : axi_lbus_corefifo_sync_scntr.v(507) | Found counter in view:work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog) instance v_wr_data_fifo.genblk18\.fifo_corefifo_sync_scntr.memraddr_r[7:0] 
@N:MO231 : axi_lbus_corefifo_sync_scntr.v(491) | Found counter in view:work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog) instance v_wr_data_fifo.genblk18\.fifo_corefifo_sync_scntr.memwaddr_r[7:0] 
@N:MF179 : ddr_rw_arbiter_lpddr4.v(349) | Found 16 by 16 bit equality operator ('==') un1_v_wr_len_fifo_rdata (in view: work.ddr_rw_arbiter_lpddr4_Z16_layer0(verilog))
Encoding state machine s_state[0:5] (in view: work.request_scheduler_DDR4_RD_WR(request_scheduler))
original code -> new code
   000001 -> 000001
   000010 -> 000010
   000100 -> 000100
   001000 -> 001000
   010000 -> 010000
   100000 -> 100000
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_2[1] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_2[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_3[1] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_3[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_0[1] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_0[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_1[1] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(190) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.mux_sel_o[1] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.mux_sel_o[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_3[2] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_3[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_0[2] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_0[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_1[2] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(140) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_2[2] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.WRITE_FIFO_PROC.s_fifo_2[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM2_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM1_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM3_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM1_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM2_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM3_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM1_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM3_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM2_INST.ram[7:0] with specified coding style. Inferring block RAM.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM3_INST.ram[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : bayer_interpolation.vhd(2234) | RAM RAM3_INST.ram[7:0] (in view: work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM2_INST.ram[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : bayer_interpolation.vhd(2234) | RAM RAM2_INST.ram[7:0] (in view: work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:FX403 : bayer_interpolation.vhd(2234) | Property "block_ram" or "no_rw_check" found for RAM RAM1_INST.ram[7:0] with specified coding style. Inferring block RAM.
@W:FX107 : bayer_interpolation.vhd(2234) | RAM RAM1_INST.ram[7:0] (in view: work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MO231 : bayer_interpolation.vhd(1748) | Found counter in view:work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p) instance WRITE_LSRAM_INST.s_v_counter[15:0] 
@N:MO231 : bayer_interpolation.vhd(1710) | Found counter in view:work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p) instance WRITE_LSRAM_INST.s_ram_address[15:0] 
@N:MO231 : bayer_interpolation.vhd(1674) | Found counter in view:work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p) instance WRITE_LSRAM_INST.s_h_res[15:0] 
@N:MF179 :  | Found 16 by 16 bit equality operator ('==') BAYER_INTERPOLATION_1P_INST.op_eq\.un16_s_boundary_hc_vc (in view: work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p)) 
@N:MF179 :  | Found 16 by 16 bit equality operator ('==') BAYER_INTERPOLATION_1P_INST.op_eq\.un9_s_boundary_hc_vc (in view: work.Bayer_Interpolation_1p_8_2048(bayer_interpolation_1p)) 
Encoding state machine s_state[0:3] (in view: work.READ_LSRAM_8_16(read_lsram))
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
   11 -> 11
@N:MO225 : bayer_interpolation.vhd(2090) | There are no possible illegal states for state machine s_state[0:3] (in view: work.READ_LSRAM_8_16(read_lsram)); safe FSM implementation is not required.
@N:MO231 : bayer_interpolation.vhd(2154) | Found counter in view:work.READ_LSRAM_8_16(read_lsram) instance s_v_counter[15:0] 
@N:MO231 : bayer_interpolation.vhd(2154) | Found counter in view:work.READ_LSRAM_8_16(read_lsram) instance s_h_counter[15:0] 
@N:MF179 : signed.vhd(101) | Found 16 by 16 bit equality operator ('==') LSRAM_READ_FSM_PROC\.op_eq\.s_state15 (in view: work.READ_LSRAM_8_16(read_lsram))
@W:FX107 : hdmi_tx.vhd(1494) | RAM ram2port_hdmi_tx_inst.ram[9:0] (in view: work.video_fifo_hdmi_tx_work_hdmi_tx_c0_rtl_0layer1_2(video_fifo_hdmi_tx)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : hdmi_tx.vhd(1494) | RAM ram2port_hdmi_tx_inst.ram[9:0] (in view: work.video_fifo_hdmi_tx_work_hdmi_tx_c0_rtl_0layer1_1(video_fifo_hdmi_tx)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W:FX107 : hdmi_tx.vhd(1494) | RAM ram2port_hdmi_tx_inst.ram[9:0] (in view: work.video_fifo_hdmi_tx_work_hdmi_tx_c0_rtl_0layer1_0(video_fifo_hdmi_tx)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@N:MO231 : display_controller.vhd(637) | Found counter in view:work.Display_Controller_Native_0_1(display_controller_native) instance s_h_counterx[10:0] 
@N:MO231 : display_controller.vhd(549) | Found counter in view:work.Display_Controller_Native_0_1(display_controller_native) instance s_v_counter[9:0] 
@N:MO231 : display_controller.vhd(595) | Found counter in view:work.Display_Controller_Native_0_1(display_controller_native) instance s_sync_counter[15:0] 
@N:MO231 : display_controller.vhd(509) | Found counter in view:work.Display_Controller_Native_0_1(display_controller_native) instance s_h_counter[10:0] 
@W:MO160 : display_controller.vhd(692) | Register bit s_v_counterx[14] (in view view:work.Display_Controller_Native_0_1(display_controller_native)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : display_controller.vhd(692) | Register bit s_v_counterx[13] (in view view:work.Display_Controller_Native_0_1(display_controller_native)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : display_controller.vhd(692) | Register bit s_v_counterx[12] (in view view:work.Display_Controller_Native_0_1(display_controller_native)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : display_controller.vhd(692) | Register bit s_v_counterx[11] (in view view:work.Display_Controller_Native_0_1(display_controller_native)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W:MO160 : display_controller.vhd(692) | Register bit s_v_counterx[10] (in view view:work.Display_Controller_Native_0_1(display_controller_native)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.

Starting factoring (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 235MB peak: 235MB)

@W:BN132 : bayer_interpolation.vhd(1655) | Removing instance DDR4_RD_WR_inst_0.video_processing_0.Bayer_Interpolation_C0_0.Bayer_Interpolation_C0_0.Bayer_Native_FORMAT.Bayer_Native_INST_0.bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst.WRITE_LSRAM_INST.s_data_valid_dly1 because it is equivalent to instance DDR4_RD_WR_inst_0.video_processing_0.Bayer_Interpolation_C0_0.Bayer_Interpolation_C0_0.Bayer_Native_FORMAT.Bayer_Native_INST_0.bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst.READ_LSRAM_INST.s_data_valid_dly1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : request_scheduler.vhd(190) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_state[5] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_state[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : data_packer_lpddr4.vhd(189) | Removing sequential instance DDR_Write_LPDDR4_0.data_packer_0.s_h_count_latch[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.
@N:BN362 : data_packer_lpddr4.vhd(189) | Removing sequential instance DDR_Write_LPDDR4_0.data_packer_0.s_h_count_latch[1] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.
@N:BN362 : data_packer_lpddr4.vhd(189) | Removing sequential instance DDR_Write_LPDDR4_0.data_packer_0.s_h_count_latch[2] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.
@N:BN362 : data_packer_lpddr4.vhd(189) | Removing sequential instance DDR_Write_LPDDR4_0.data_packer_0.s_h_count_latch[3] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.
@N:BN362 : data_packer_lpddr4.vhd(189) | Removing sequential instance DDR_Write_LPDDR4_0.data_packer_0.s_h_count_latch[4] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.

Finished factoring (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:19s; Memory used current: 244MB peak: 244MB)


Available hyper_sources - for debug and ip models
	None Found

@W:BN132 : ddr_rw_arbiter_lpddr4.v(400) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[14] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_rw_arbiter_lpddr4.v(400) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[15] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_rw_arbiter_lpddr4.v(400) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[13] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_rw_arbiter_lpddr4.v(400) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[12] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_rw_arbiter_lpddr4.v(400) | Removing instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[11] because it is equivalent to instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_len_fifo_wrdata[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : bayer_interpolation.vhd(1655) | Removing instance DDR4_RD_WR_inst_0.video_processing_0.Bayer_Interpolation_C0_0.Bayer_Interpolation_C0_0.Bayer_Native_FORMAT.Bayer_Native_INST_0.bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst.WRITE_LSRAM_INST.s_data_valid_dly2 because it is equivalent to instance DDR4_RD_WR_inst_0.video_processing_0.Bayer_Interpolation_C0_0.Bayer_Interpolation_C0_0.Bayer_Native_FORMAT.Bayer_Native_INST_0.bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst.READ_LSRAM_INST.s_data_valid_dly2. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : request_scheduler.vhd(190) | Removing sequential instance Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.mux_sel_o[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.
@N:BN362 : request_scheduler.vhd(190) | Removing sequential instance Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.mux_sel_o[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.

Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:26s; Memory used current: 260MB peak: 262MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:30s; Memory used current: 261MB peak: 262MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:44s; CPU Time elapsed 0h:00m:44s; Memory used current: 265MB peak: 265MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:45s; CPU Time elapsed 0h:00m:45s; Memory used current: 265MB peak: 265MB)

@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[5] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[4] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[2] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[7] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[8] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[1] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[3] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:BN132 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[6] because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@N:BN362 : ddr_read_controller_fhd_hdmi_rx.vhd(171) | Removing sequential instance DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.s_read_start_addr[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances.

Finished preparing to map (Real Time elapsed 0h:00m:50s; CPU Time elapsed 0h:00m:50s; Memory used current: 266MB peak: 266MB)


Finished technology mapping (Real Time elapsed 0h:00m:53s; CPU Time elapsed 0h:00m:53s; Memory used current: 298MB peak: 298MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:54s		    -4.36ns		4965 /      5825
   2		0h:00m:54s		    -4.36ns		4910 /      5825
@N:FX271 : axi_lbus_corefifo_fwft.v(185) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.N_5686_i (in view: work.DDR4_RD_WR(verilog)) with 513 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.g0 (in view: work.DDR4_RD_WR(verilog)) with 512 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.g0 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 515 loads 3 times to improve timing.
@N:FX271 : apb3_interface.vhd(186) | Replicating instance video_processing_0.apb3_interface_0.bayer_o[0] (in view: work.DDR4_RD_WR(verilog)) with 22 loads 2 times to improve timing.
Timing driven replication report
Added 2 Registers via timing driven replication
Added 9 LUTs via timing driven replication

   3		0h:00m:58s		    -3.01ns		4931 /      5827
   4		0h:00m:58s		    -2.98ns		4938 /      5827
@N:FX271 : axi_lbus_corefifo_fwft.v(185) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.N_5686_i_rep1 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(185) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.N_5686_i_rep2 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : dwc_downconv_widthconvwr.v(952) | Replicating instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.g0 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(185) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.N_5686_i (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.g0_rep1 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.g0_rep2 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.g0_fast (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(130) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.g0 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N:FX271 : axi_lbus_corefifo_fwft.v(185) | Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.N_5686_i_fast (in view: work.DDR4_RD_WR(verilog)) with 126 loads 3 times to improve timing.
@N:FX271 : display_controller.vhd(549) | Replicating instance Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[6] (in view: work.DDR4_RD_WR(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : display_controller.vhd(549) | Replicating instance Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[7] (in view: work.DDR4_RD_WR(verilog)) with 4 loads 1 time to improve timing.
@N:FX271 : display_controller.vhd(549) | Replicating instance Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[1] (in view: work.DDR4_RD_WR(verilog)) with 5 loads 1 time to improve timing.
Timing driven replication report
Added 3 Registers via timing driven replication
Added 27 LUTs via timing driven replication

@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[0] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[1] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[2] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[3] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[4] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[5] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[6] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[7] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[8] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[9] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[10] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
@N:FX271 : video_fifo.vhd(321) | Replicating instance DDR_Read_LPDDR4_0.video_fifo_0.wbin[11] (in view: work.DDR4_RD_WR(verilog)) with 104 loads 3 times to improve timing.
Timing driven replication report
Added 36 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   5		0h:00m:59s		    -2.67ns		4961 /      5866
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[1] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[2] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[3] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[4] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[5] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[6] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[7] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[8] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[9] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[10] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[11] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[12] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[13] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[14] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[15] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[16] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[17] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[18] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[19] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[20] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[21] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[22] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[23] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[24] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[25] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[26] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[27] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[28] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[29] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[30] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_12_OLDA[31] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[1] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[2] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[3] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[4] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[5] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[6] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[7] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[8] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[9] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[10] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[11] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[12] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[13] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[14] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[15] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[16] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[17] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[18] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[19] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[20] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[21] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[22] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[23] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[24] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[25] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[26] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[27] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[28] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[29] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[30] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[31] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[32] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[33] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[34] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[35] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[36] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[37] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[38] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_11_OLDA[39] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[0] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[1] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[2] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[3] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[4] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[5] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[6] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[7] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[8] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[9] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[10] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[11] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[12] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[13] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[14] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[15] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[16] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[17] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[18] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 
@N:BN362 :  | Removing sequential instance DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_10_OLDA[19] (in view: work.DDR4_RD_WR(verilog)) because it does not drive other instances. 

Only the first 100 messages of id 'BN362' are reported. To see all messages use 'report_messages -log D:\Delme\SEV_PFSoC_OpenVX\synthesis\DDR4_RD_WR\DDR4_RD_WR.srr -id BN362' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {BN362} -count unlimited' in the Tcl shell.

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Added 0 Buffers
Added 0 Cells via replication
	Added 0 Sequential Cells via replication
	Added 0 Combinational Cells via replication

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:01m:03s; CPU Time elapsed 0h:01m:03s; Memory used current: 310MB peak: 310MB)


Finished restoring hierarchy (Real Time elapsed 0h:01m:04s; CPU Time elapsed 0h:01m:04s; Memory used current: 311MB peak: 313MB)


Finished mapping DDR4_RD_WR
Multiprocessing finished at : Mon Nov 21 15:27:38 2022
Multiprocessing took 0h:01m:08s realtime, 0h:00m:04s cputime

Summary of Compile Points :
*************************** 
Name                                                                             Status     Reason          Start Time                   End Time                     Realtime       CPU Time       Fast Synthesis
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
embsync_detect_Z1_layer0                                                         Mapped     No database     Mon Nov 21 15:26:31 2022     Mon Nov 21 15:26:38 2022     0h:00m:06s     0h:00m:07s     No            
caxi4interconnect_MasterConvertor_Z22_layer0                                     Mapped     No database     Mon Nov 21 15:26:32 2022     Mon Nov 21 15:26:52 2022     0h:00m:19s     0h:00m:20s     No            
caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s     Mapped     No database     Mon Nov 21 15:26:53 2022     Mon Nov 21 15:27:20 2022     0h:00m:27s     0h:00m:27s     No            
IMX334_IF_TOP                                                                    Mapped     No database     Mon Nov 21 15:26:30 2022     Mon Nov 21 15:27:29 2022     0h:00m:58s     0h:00m:58s     No            
DDR4_RD_WR                                                                       Mapped     No database     Mon Nov 21 15:26:31 2022     Mon Nov 21 15:27:37 2022     0h:01m:06s     0h:01m:06s     No            
SEV_PFSoC_OpenVX                                                                 Mapped     No database     Mon Nov 21 15:26:41 2022     Mon Nov 21 15:27:36 2022     0h:00m:55s     0h:00m:55s     No            
==================================================================================================================================================================================================================
Total number of compile points: 6
===================================

Links to Compile point Reports:
******************************
Linked File:  DDR4_RD_WR.srr
Linked File:  SEV_PFSoC_OpenVX.srr
Linked File:  IMX334_IF_TOP.srr
Linked File:  caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s.srr
Linked File:  caxi4interconnect_MasterConvertor_Z22_layer0.srr
Linked File:  embsync_detect_Z1_layer0.srr

==============================


Start loading CP mapped netlist (Real Time elapsed 0h:01m:10s; CPU Time elapsed 0h:00m:07s; Memory used current: 270MB peak: 271MB)


Finished loading CP mapped netlist (Real Time elapsed 0h:01m:12s; CPU Time elapsed 0h:00m:09s; Memory used current: 331MB peak: 331MB)



@S |Clock Optimization Summary


#### START OF CLOCK OPTIMIZATION REPORT #####[

Clock optimization not enabled
6 non-gated/non-generated clock tree(s) driving 1102 clock pin(s) of sequential element(s)
17 gated/generated clock tree(s) driving 11528 clock pin(s) of sequential element(s)
0 instances converted, 11528 sequential instances remain driven by gated/generated clocks

==================================================================================== Non-Gated/Non-Generated Clocks =====================================================================================
Clock Tree ID     Driving Element                                                             Drive Element Type                 Fanout     Sample Instance                                              
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0018        CLOCKS_AND_RESETS_inst_0.PF_XCVR_REF_CLK_C0_0.PF_XCVR_REF_CLK_C0_0.I_IO     XCVR_REF_CLK                       1          CLOCKS_AND_RESETS_inst_0.PF_CCC_C0_0.PF_CCC_C0_0.pll_inst_0  
ClockId0019        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE0                             clock definition on XCVR_PMA       1004       DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE0              
ClockId0020        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3                             clock definition on XCVR_PMA       32         DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3              
ClockId0021        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2                             clock definition on XCVR_PMA       32         DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2              
ClockId0022        DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1                             clock definition on XCVR_PMA       32         DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1              
ClockId0023        CLOCKS_AND_RESETS_inst_0.PF_OSC_C0_0.PF_OSC_C0_0.I_OSC_2                    clock definition on OSC_RC2MHZ     1          CLOCKS_AND_RESETS_inst_0.PF_CLK_DIV_C0_0.PF_CLK_DIV_C0_0.I_CD
=========================================================================================================================================================================================================
================================================================================================================================================= Gated/Generated Clocks =================================================================================================================================================
Clock Tree ID     Driving Element                                                                                     Drive Element Type     Fanout     Sample Instance                                                                                Explanation                                                        
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
ClockId0001        CLOCKS_AND_RESETS_inst_0.PF_CCC_C1_0.PF_CCC_C1_0.pll_inst_0                                         PLL                    5205       MSS.I_MSS                                                                                      No gated clock conversion method for cell cell:work.MSS            
ClockId0002        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_CCC_C2_0.PF_CCC_C2_0.pll_inst_0                                PLL                    1274       DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_14                   No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0003        CLOCKS_AND_RESETS_inst_0.PF_CCC_C0_0.PF_CCC_C0_0.pll_inst_0                                         PLL                    120        MSS.I_MSS                                                                                      No gated clock conversion method for cell cell:work.MSS            
ClockId0004        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_FIFO                    HS_IO_CLK              6          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL     No gated clock conversion method for cell cell:work.LANECTRL       
ClockId0005        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL          LANECTRL               4          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_2            No gated clock conversion method for cell cell:work.IOD            
ClockId0006        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_CASCADED                HS_IO_CLK              2          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_CLK_DIV_RXCLK.I_CDD       No gated clock conversion method for cell cell:work.ICB_CLKDIVDELAY
ClockId0007        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.HS_IO_CLK_RX                      HS_IO_CLK              1          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL     No gated clock conversion method for cell cell:work.LANECTRL       
ClockId0008        DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_CLK_DIV_FIFO.I_CDD             ICB_CLKDIVDELAY        4907       DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL     No gated clock conversion method for cell cell:work.LANECTRL       
ClockId0009        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_10     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_27_rs        No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0010        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_9      CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_6_rs         No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0011        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_13     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_8_rs         No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0012        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_12     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_3_rs         No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0013        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_11     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_16_rs        No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0014        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_15     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_9_rs         No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0015        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_14     CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_19_rs        No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0016        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_start_addr_i_8      CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_21_rs        No gated clock conversion method for cell cell:ACG4.SLE            
ClockId0017        DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_frame_index_i_1           CFG2                   1          DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_1_rs         No gated clock conversion method for cell cell:ACG4.SLE            
==========================================================================================================================================================================================================================================================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:01m:14s; CPU Time elapsed 0h:00m:11s; Memory used current: 159MB peak: 337MB)

Writing Analyst data base D:\Delme\SEV_PFSoC_OpenVX\synthesis\synwork\SEV_PFSoC_OpenVX_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:01m:20s; CPU Time elapsed 0h:00m:16s; Memory used current: 278MB peak: 337MB)

Writing Verilog Simulation files
@N:BW103 :  | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:BW107 :  | Synopsys Constraint File capacitance units using default value of 1pF  

Finished Writing Verilog Simulation files (Real Time elapsed 0h:01m:30s; CPU Time elapsed 0h:00m:26s; Memory used current: 263MB peak: 337MB)


Finished Writing Netlists (Real Time elapsed 0h:01m:30s; CPU Time elapsed 0h:00m:26s; Memory used current: 263MB peak: 337MB)


Start final timing analysis (Real Time elapsed 0h:01m:32s; CPU Time elapsed 0h:00m:28s; Memory used current: 266MB peak: 337MB)

@W:MT246 : pf_osc_c0_pf_osc_c0_0_pf_osc.v(13) | Blackbox OSC_RC2MHZ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : init_monitor_init_monitor_0_pfsoc_init_monitor.v(71) | Blackbox BANKCTRL_GPIO is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : init_monitor_init_monitor_0_pfsoc_init_monitor.v(63) | Blackbox BANKCTRL_HSIO is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W:MT246 : init_monitor_init_monitor_0_pfsoc_init_monitor.v(44) | Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@N:MT615 :  | Found clock REF_CLK_PAD_P with period 6.73ns  
@N:MT615 :  | Found clock CAM1_RX_CLK_P with period 4.00ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R with period 13.47ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R with period 13.47ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R with period 13.47ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R with period 13.47ns  
@N:MT615 :  | Found clock CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK with period 500.00ns  
@N:MT615 :  | Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 with period 20.00ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV with period 16.00ns  
@N:MT615 :  | Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 with period 5.00ns  
@N:MT615 :  | Found clock DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 with period 5.88ns  


##### START OF TIMING REPORT #####[
# Timing report written on Mon Nov 21 15:28:00 2022
#


Top view:               SEV_PFSoC_OpenVX
Requested Frequency:    2.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    D:\Delme\SEV_PFSoC_OpenVX\designer\SEV_PFSoC_OpenVX\synthesis.fdc
                       
@N:MT320 :  | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:MT322 :  | Clock constraints include only register-to-register paths associated with each individual clock. 



Performance Summary
*******************


Worst slack in design: -4.095

                                                                                                  Requested     Estimated     Requested     Estimated                Clock                              Clock           
Starting Clock                                                                                    Frequency     Frequency     Period        Period        Slack      Type                               Group           
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CAM1_RX_CLK_P                                                                                     250.0 MHz     NA            4.000         NA            NA         declared                           default_clkgroup
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                                  50.0 MHz      18.7 MHz      20.000        53.384        -1.964     generated (from REF_CLK_PAD_P)     default_clkgroup
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                                  200.0 MHz     0.2 MHz       5.000         5124.125      -2.456     generated (from REF_CLK_PAD_P)     default_clkgroup
CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK                                      2.0 MHz       NA            500.000       NA            NA         declared                           default_clkgroup
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                         170.0 MHz     13.9 MHz      5.882         71.718        -2.111     generated (from CAM1_RX_CLK_P)     default_clkgroup
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     62.5 MHz      5.1 MHz       16.000        195.073       -2.634     generated (from CAM1_RX_CLK_P)     default_clkgroup
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                          74.3 MHz      0.1 MHz       13.468        13802.343     -4.095     declared                           default_clkgroup
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                          74.3 MHz      191.5 MHz     13.468        5.221         8.247      declared                           default_clkgroup
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                          74.3 MHz      191.5 MHz     13.468        5.221         8.247      declared                           default_clkgroup
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                          74.3 MHz      191.5 MHz     13.468        5.221         8.247      declared                           default_clkgroup
REF_CLK_PAD_P                                                                                     148.5 MHz     NA            6.734         NA            NA         declared                           default_clkgroup
System                                                                                            100.0 MHz     121.5 MHz     10.000        8.232         1.768      system                             system_clkgroup 
========================================================================================================================================================================================================================
Estimated period and frequency reported as NA means no slack depends directly on the clock waveform


@W:MT116 :  | Paths from clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV:r) to clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.24 ns is too small.   
@W:MT116 :  | Paths from clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0:r) to clock (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R:r) are overconstrained because the required time of 0.00 ns is too small.   
@W:MT116 :  | Paths from clock (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R:r) to clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.00 ns is too small.   
@W:MT116 :  | Paths from clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0:r) to clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.29 ns is too small.   
@W:MT116 :  | Paths from clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) to clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.29 ns is too small.   
@W:MT116 :  | Paths from clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0:r) to clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 1.18 ns is too small.   
@W:MT116 :  | Paths from clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) to clock (CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 1.18 ns is too small.   



Clock Relationships
*******************

Clocks                                                                                                                                                                                        |    rise  to  rise    |    fall  to  fall   |    rise  to  fall    |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Starting                                                                                       Ending                                                                                         |  constraint  slack   |  constraint  slack  |  constraint  slack   |  constraint  slack
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                                                                         CAM1_RX_CLK_P                                                                                  |  4.000       1.768   |  No paths    -      |  No paths    -       |  No paths    -    
System                                                                                         DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  13.468      10.464  |  No paths    -      |  No paths    -       |  No paths    -    
System                                                                                         CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               |  20.000      16.870  |  No paths    -      |  No paths    -       |  No paths    -    
System                                                                                         DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV  |  16.000      11.459  |  No paths    -      |  16.000      14.097  |  No paths    -    
System                                                                                         CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               |  5.000       1.870   |  No paths    -      |  No paths    -       |  No paths    -    
System                                                                                         DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      |  5.882       2.751   |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  13.468      6.397   |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               |  0.004       -4.095  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R                                       |  13.468      8.247   |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R                                       |  13.468      8.247   |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  13.468      13.126  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                       DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R                                       |  13.468      8.247   |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               System                                                                                         |  20.000      18.178  |  No paths    -      |  20.000      18.172  |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               |  20.000      14.770  |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               |  5.000       3.020   |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      |  1.177       -1.964  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV  DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV  |  16.000      11.187  |  No paths    -      |  8.000       7.664   |  No paths    -    
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV  DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      |  0.235       -2.634  |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               System                                                                                         |  5.000       2.756   |  No paths    -      |  5.000       2.748   |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R                                       |  0.004       -2.456  |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               |  5.000       -0.539  |  No paths    -      |  No paths    -       |  No paths    -    
CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      |  0.294       -0.048  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0                               |  1.177       0.548   |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0                               |  0.294       -2.111  |  No paths    -      |  No paths    -       |  No paths    -    
DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0                      |  5.882       0.290   |  No paths    -      |  No paths    -       |  No paths    -    
======================================================================================================================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0
====================================



Starting Points with Worst Slack
********************************

                                                                      Starting                                                                                                               Arrival           
Instance                                                              Reference                                                            Type     Pin     Net                              Time        Slack 
                                                                      Clock                                                                                                                                    
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[0]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[0]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[1]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[1]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[2]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[2]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[3]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[3]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[4]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[4]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[5]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[5]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[6]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[6]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[7]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[7]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[8]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[8]     0.218       -1.964
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[9]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      Q       apb3_interface_0_bconst_o[9]     0.218       -1.964
===============================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                        Starting                                                                                             Required           
Instance                Reference                                                            Type     Pin     Net            Time         Slack 
                        Clock                                                                                                                   
------------------------------------------------------------------------------------------------------------------------------------------------
IKrxtbnogwuwa9erJ       CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       dgzoBd6Dn      1.177        -1.964
IKrxtbnogwuwa9exn       CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       dgzoBd6I3      1.177        -1.964
IKrxtbnogwuwa9e23       CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       dgzoBd7bJ      1.177        -1.964
eLDnmBwCHsx3ftHd6bJ     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91rDn     1.177        -1.964
eLDnmBwCHsx3ftHd6hn     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91rI3     1.177        -1.964
eLDnmBwCHsx3ftHd6m3     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91sbJ     1.177        -1.964
eLDnmBwCHsx3ftHd6rJ     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91shn     1.177        -1.964
eLDnmBwCHsx3ftHd6xn     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91sm3     1.177        -1.964
eLDnmBwCHsx3ftHd623     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91srJ     1.177        -1.964
eLDnmBwCHsx3ftHd67J     CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0     SLE      D       q8CKB91sxn     1.177        -1.964
================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      1.177
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.177

    - Propagation time:                      3.140
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.964

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[0] / Q
    Ending point:                            eLDnmBwCHsx3ftHfv7J / D
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                  Type        Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[0]     SLE         Q         Out     0.218     0.218 r     -         
apb3_interface_0_bconst_o[0]                                          Net         -         -       0.612     -           1         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     A[0]      In      -         0.830 r     -         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     P[20]     Out     2.192     3.022 f     -         
q8CKB91Km3                                                            Net         -         -       0.118     -           1         
eLDnmBwCHsx3ftHfv7J                                                   SLE         D         In      -         3.140 f     -         
====================================================================================================================================
Total path delay (propagation time + setup) of 3.140 is 2.410(76.8%) logic and 0.730(23.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      1.177
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.177

    - Propagation time:                      3.140
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.964

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[1] / Q
    Ending point:                            eLDnmBwCHsx3ftHfv7J / D
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                  Type        Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[1]     SLE         Q         Out     0.218     0.218 r     -         
apb3_interface_0_bconst_o[1]                                          Net         -         -       0.612     -           1         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     A[1]      In      -         0.830 r     -         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     P[20]     Out     2.192     3.022 f     -         
q8CKB91Km3                                                            Net         -         -       0.118     -           1         
eLDnmBwCHsx3ftHfv7J                                                   SLE         D         In      -         3.140 f     -         
====================================================================================================================================
Total path delay (propagation time + setup) of 3.140 is 2.410(76.8%) logic and 0.730(23.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      1.177
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.177

    - Propagation time:                      3.140
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.964

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[2] / Q
    Ending point:                            eLDnmBwCHsx3ftHfv7J / D
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                  Type        Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[2]     SLE         Q         Out     0.218     0.218 r     -         
apb3_interface_0_bconst_o[2]                                          Net         -         -       0.612     -           1         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     A[2]      In      -         0.830 r     -         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     P[20]     Out     2.192     3.022 f     -         
q8CKB91Km3                                                            Net         -         -       0.118     -           1         
eLDnmBwCHsx3ftHfv7J                                                   SLE         D         In      -         3.140 f     -         
====================================================================================================================================
Total path delay (propagation time + setup) of 3.140 is 2.410(76.8%) logic and 0.730(23.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      1.177
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.177

    - Propagation time:                      3.140
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.964

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[3] / Q
    Ending point:                            eLDnmBwCHsx3ftHfv7J / D
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                  Type        Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[3]     SLE         Q         Out     0.218     0.218 r     -         
apb3_interface_0_bconst_o[3]                                          Net         -         -       0.612     -           1         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     A[3]      In      -         0.830 r     -         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     P[20]     Out     2.192     3.022 f     -         
q8CKB91Km3                                                            Net         -         -       0.118     -           1         
eLDnmBwCHsx3ftHfv7J                                                   SLE         D         In      -         3.140 f     -         
====================================================================================================================================
Total path delay (propagation time + setup) of 3.140 is 2.410(76.8%) logic and 0.730(23.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      1.177
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.177

    - Propagation time:                      3.140
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.964

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[4] / Q
    Ending point:                            eLDnmBwCHsx3ftHfv7J / D
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=10.000 period=20.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                    Pin       Pin               Arrival     No. of    
Name                                                                  Type        Name      Dir     Delay     Time        Fan Out(s)
------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.video_processing_0.apb3_interface_0.bconst_o[4]     SLE         Q         Out     0.218     0.218 r     -         
apb3_interface_0_bconst_o[4]                                          Net         -         -       0.612     -           1         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     A[4]      In      -         0.830 r     -         
d8iwwwIhD1o1dfgFEExKbh0bqLfwHvEhoibb2zeFDn                            MACC_PA     P[20]     Out     2.192     3.022 f     -         
q8CKB91Km3                                                            Net         -         -       0.118     -           1         
eLDnmBwCHsx3ftHfv7J                                                   SLE         D         In      -         3.140 f     -         
====================================================================================================================================
Total path delay (propagation time + setup) of 3.140 is 2.410(76.8%) logic and 0.730(23.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0
====================================



Starting Points with Worst Slack
********************************

                                                                                                           Starting                                                                                                      Arrival           
Instance                                                                                                   Reference                                                            Type     Pin     Net                     Time        Slack 
                                                                                                           Clock                                                                                                                           
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15                                     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       dff                     0.218       -2.456
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15_rep                                 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       dff_15_rep              0.218       -2.401
FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.rgsl.genblk4\.wrs.currState[0]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       dwc_sr_masterWREADY     0.218       -0.539
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[12]                                                  CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wbin[12]                0.218       -0.338
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[0]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[0]                 0.218       -0.332
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[1]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[1]                 0.218       -0.332
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[2]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[2]                 0.218       -0.332
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[3]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[3]                 0.218       -0.332
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[4]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[4]                 0.218       -0.332
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[5]                                                   CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      Q       wptr[5]                 0.218       -0.332
===========================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                             Starting                                                                                           Required           
Instance                                                     Reference                                                            Type     Pin     Net          Time         Slack 
                                                             Clock                                                                                                                 
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[0]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[1]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[2]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[3]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[4]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[5]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[6]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[7]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[8]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[9]     CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0     SLE      ALn     AND2_0_Y     0.004        -2.456
===================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      2.460
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.456

    Number of logic level(s):                1
    Starting point:                          CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[0] / ALn
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15     SLE      Q        Out     0.218     0.218 r     -         
dff                                                                        Net      -        -       1.001     -           40        
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     A        In      -         1.219 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     Y        Out     0.103     1.322 r     -         
AND2_0_Y                                                                   Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rbin[0]                   SLE      ALn      In      -         2.460 r     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 2.460 is 0.321(13.0%) logic and 2.139(87.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      2.460
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.456

    Number of logic level(s):                1
    Starting point:                          CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[10] / ALn
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15     SLE      Q        Out     0.218     0.218 r     -         
dff                                                                        Net      -        -       1.001     -           40        
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     A        In      -         1.219 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     Y        Out     0.103     1.322 r     -         
AND2_0_Y                                                                   Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[10]                  SLE      ALn      In      -         2.460 r     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 2.460 is 0.321(13.0%) logic and 2.139(87.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      2.460
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.456

    Number of logic level(s):                1
    Starting point:                          CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[11] / ALn
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15     SLE      Q        Out     0.218     0.218 r     -         
dff                                                                        Net      -        -       1.001     -           40        
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     A        In      -         1.219 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     Y        Out     0.103     1.322 r     -         
AND2_0_Y                                                                   Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[11]                  SLE      ALn      In      -         2.460 r     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 2.460 is 0.321(13.0%) logic and 2.139(87.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      2.460
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.456

    Number of logic level(s):                1
    Starting point:                          CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[0] / ALn
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15     SLE      Q        Out     0.218     0.218 r     -         
dff                                                                        Net      -        -       1.001     -           40        
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     A        In      -         1.219 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     Y        Out     0.103     1.322 r     -         
AND2_0_Y                                                                   Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[0]                   SLE      ALn      In      -         2.460 r     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 2.460 is 0.321(13.0%) logic and 2.139(87.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      2.460
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.456

    Number of logic level(s):                1
    Starting point:                          CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[1] / ALn
    The start point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK

Instance / Net                                                                      Pin      Pin               Arrival     No. of    
Name                                                                       Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_15     SLE      Q        Out     0.218     0.218 r     -         
dff                                                                        Net      -        -       1.001     -           40        
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     A        In      -         1.219 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                 AND2     Y        Out     0.103     1.322 r     -         
AND2_0_Y                                                                   Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.rptr[1]                   SLE      ALn      In      -         2.460 r     -         
=====================================================================================================================================
Total path delay (propagation time + setup) of 2.460 is 0.321(13.0%) logic and 2.139(87.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0
====================================



Starting Points with Worst Slack
********************************

                                                                                     Starting                                                                                                                          Arrival           
Instance                                                                             Reference                                                                     Type        Pin           Net                       Time        Slack 
                                                                                     Clock                                                                                                                                               
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     SLE         Q             dff_15_rep                0.218       -2.111
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_frame_valid_dly2                DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     SLE         Q             s_frame_valid_dly2        0.218       -1.860
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[0]     write_top_0_data_o[0]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[1]     write_top_0_data_o[1]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[2]     write_top_0_data_o[2]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[3]     write_top_0_data_o[3]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[4]     write_top_0_data_o[4]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[5]     write_top_0_data_o[5]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[6]     write_top_0_data_o[6]     0.483       -1.803
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0        DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DOUT[7]     write_top_0_data_o[7]     0.483       -1.803
=========================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                                                                                                 Starting                                                                                                                         Required           
Instance                                                                                                                                                         Reference                                                                     Type        Pin          Net                       Time         Slack 
                                                                                                                                                                 Clock                                                                                                                                               
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0]                                                                                         DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     SLE         ALn          dff_arst_1                0.294        -2.111
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.sync_out[0]                                                                                          DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     SLE         ALn          dff_arst_1                0.294        -2.111
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0]                                                                                         DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     SLE         D            AND2_0_Y                  0.294        -1.860
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[0]     write_top_0_data_o[0]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[1]     write_top_0_data_o[1]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[2]     write_top_0_data_o[2]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[3]     write_top_0_data_o[3]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[4]     write_top_0_data_o[4]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[5]     write_top_0_data_o[5]     -0.509       -1.803
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0     RAM1K20     B_DIN[6]     write_top_0_data_o[6]     -0.509       -1.803
=====================================================================================================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      0.294
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.294

    - Propagation time:                      2.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.111

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                          Pin      Pin               Arrival     No. of    
Name                                                                                         Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep             SLE        Q        Out     0.218     0.218 r     -         
dff_15_rep                                                                                   Net        -        -       0.680     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep_RNITC8F     CLKINT     A        In      -         0.898 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep_RNITC8F     CLKINT     Y        Out     0.337     1.235 r     -         
dff_arst                                                                                     Net        -        -       1.170     -           1098      
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0]                     SLE        ALn      In      -         2.405 r     -         
=========================================================================================================================================================
Total path delay (propagation time + setup) of 2.405 is 0.555(23.1%) logic and 1.850(76.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.294
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.294

    - Propagation time:                      2.405
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.111

    Number of logic level(s):                1
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.sync_out[0] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                          Pin      Pin               Arrival     No. of    
Name                                                                                         Type       Name     Dir     Delay     Time        Fan Out(s)
---------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep             SLE        Q        Out     0.218     0.218 r     -         
dff_15_rep                                                                                   Net        -        -       0.680     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep_RNITC8F     CLKINT     A        In      -         0.898 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15_rep_RNITC8F     CLKINT     Y        Out     0.337     1.235 r     -         
dff_arst                                                                                     Net        -        -       1.170     -           1098      
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.sync_out[0]                      SLE        ALn      In      -         2.405 r     -         
=========================================================================================================================================================
Total path delay (propagation time + setup) of 2.405 is 0.555(23.1%) logic and 1.850(76.9%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      0.294
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.294

    - Propagation time:                      2.154
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.860

    Number of logic level(s):                2
    Starting point:                          DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_frame_valid_dly2 / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0] / D
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                            Pin      Pin               Arrival     No. of    
Name                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_frame_valid_dly2            SLE      Q        Out     0.218     0.218 r     -         
s_frame_valid_dly2                                                               Net      -        -       0.547     -           3         
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_cam_fault_dly2_RNI5Q931     CFG3     C        In      -         0.765 r     -         
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_cam_fault_dly2_RNI5Q931     CFG3     Y        Out     0.148     0.913 r     -         
fifo_reset_o_1_i                                                                 Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.AND2_0                                      AND2     B        In      -         1.861 r     -         
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.AND2_0                                      AND2     Y        Out     0.169     2.030 r     -         
AND2_0_Y                                                                         Net      -        -       0.124     -           2         
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.synchronizer_circuit_1.s_data_in[0]         SLE      D        In      -         2.154 r     -         
===========================================================================================================================================
Total path delay (propagation time + setup) of 2.154 is 0.535(24.9%) logic and 1.619(75.1%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      0.294
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         -0.509

    - Propagation time:                      1.295
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.803

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0 / B_DOUT[0]
    Ending point:                            DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0 / B_DIN[0]
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin B_CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin B_CLK

Instance / Net                                                                                                                                                               Pin           Pin               Arrival     No. of    
Name                                                                                                                                                             Type        Name          Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0                                                                                    RAM1K20     B_DOUT[0]     Out     0.483     0.483 f     -         
write_top_0_data_o[0]                                                                                                                                            Net         -             -       0.812     -           1         
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     RAM1K20     B_DIN[0]      In      -         1.295 f     -         
===================================================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.098 is 1.285(61.3%) logic and 0.812(38.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      0.294
    - Setup time:                            0.803
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         -0.509

    - Propagation time:                      1.295
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -1.803

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0 / B_DOUT[1]
    Ending point:                            DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0 / B_DIN[1]
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin B_CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin B_CLK

Instance / Net                                                                                                                                                               Pin           Pin               Arrival     No. of    
Name                                                                                                                                                             Type        Name          Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.video_fifo_0.ram2port_inst.io1l_io1l_0_0                                                                                    RAM1K20     B_DOUT[1]     Out     0.483     0.483 f     -         
write_top_0_data_o[1]                                                                                                                                            Net         -             -       0.812     -           1         
DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk24\.UI_ram_wrapper_1.L3_syncnonpipe.genblk1\.fi_te_fi_te_0_LSRAM_top_R0C0     RAM1K20     B_DIN[1]      In      -         1.295 f     -         
===================================================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.098 is 1.285(61.3%) logic and 0.812(38.7%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV
====================================



Starting Points with Worst Slack
********************************

                                                                                                                                                                    Starting                                                                                                                               Arrival           
Instance                                                                                                                                                            Reference                                                                                         Type     Pin     Net                 Time        Slack 
                                                                                                                                                                    Clock                                                                                                                                                    
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done                           DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       bit_align_done      0.218       -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.bit_align_done                           DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       bit_align_done      0.218       -2.602
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.bit_align_done                           DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       bit_align_done      0.218       -2.521
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.CORERXIODBITALIGN_C0_0.u_CoreRxIODBitAlign.bit_align_done                           DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       bit_align_done      0.218       -2.454
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C2_0.CORERESET_PF_C2_0.dff_15_rep                                                                                    DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       dff_15_rep          0.218       -2.170
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1\.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.genblk2\.frame_valid_out           DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       frame_valid_out     0.218       -0.101
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1\.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.byte2pix_fifo.wraddr_rr[0]     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       wraddr_rr[0]        0.218       -0.101
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1\.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.byte2pix_fifo.wraddr_rr[1]     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       wraddr_rr[1]        0.218       -0.101
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1\.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.byte2pix_fifo.wraddr_rr[2]     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       wraddr_rr[2]        0.218       -0.101
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1\.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.byte2pix_fifo.wraddr_rr[3]     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      Q       wraddr_rr[3]        0.218       -0.101
=============================================================================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                Starting                                                                                                                                       Required           
Instance                                                                        Reference                                                                                         Type     Pin     Net                         Time         Slack 
                                                                                Clock                                                                                                                                                             
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_0     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_1     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_2     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_3     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_4     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_5     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_6     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_7     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_8     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_9     DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV     SLE      ALn     un1_INTERNAL_RST_arst_i     0.235        -2.634
==================================================================================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      0.235
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.235

    - Propagation time:                      2.869
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.633

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done / Q
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_0 / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done       SLE      Q        Out     0.218     0.218 r     -         
bit_align_done                                                                                                                                  Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     A        In      -         0.336 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     Y        Out     0.051     0.387 r     -         
CORERXIODBITALIGN_C3_0_BIT_ALGN_DONE                                                                                                            Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     D        In      -         1.335 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     Y        Out     0.282     1.617 r     -         
PF_IOD_GENERIC_RX_C0_0_training_done_o                                                                                                          Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     A        In      -         1.735 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     Y        Out     0.051     1.786 r     -         
un1_INTERNAL_RST_arst_i                                                                                                                         Net      -        -       1.083     -           34        
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_0                                                                     SLE      ALn      In      -         2.869 r     -         
==========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.869 is 0.602(21.0%) logic and 2.267(79.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.235
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.235

    - Propagation time:                      2.869
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.633

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done / Q
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_14 / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done       SLE      Q        Out     0.218     0.218 r     -         
bit_align_done                                                                                                                                  Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     A        In      -         0.336 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     Y        Out     0.051     0.387 r     -         
CORERXIODBITALIGN_C3_0_BIT_ALGN_DONE                                                                                                            Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     D        In      -         1.335 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     Y        Out     0.282     1.617 r     -         
PF_IOD_GENERIC_RX_C0_0_training_done_o                                                                                                          Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     A        In      -         1.735 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     Y        Out     0.051     1.786 r     -         
un1_INTERNAL_RST_arst_i                                                                                                                         Net      -        -       1.083     -           34        
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_14                                                                    SLE      ALn      In      -         2.869 r     -         
==========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.869 is 0.602(21.0%) logic and 2.267(79.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      0.235
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.235

    - Propagation time:                      2.869
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.633

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done / Q
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15 / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done       SLE      Q        Out     0.218     0.218 r     -         
bit_align_done                                                                                                                                  Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     A        In      -         0.336 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     Y        Out     0.051     0.387 r     -         
CORERXIODBITALIGN_C3_0_BIT_ALGN_DONE                                                                                                            Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     D        In      -         1.335 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     Y        Out     0.282     1.617 r     -         
PF_IOD_GENERIC_RX_C0_0_training_done_o                                                                                                          Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     A        In      -         1.735 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     Y        Out     0.051     1.786 r     -         
un1_INTERNAL_RST_arst_i                                                                                                                         Net      -        -       1.083     -           34        
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_15                                                                    SLE      ALn      In      -         2.869 r     -         
==========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.869 is 0.602(21.0%) logic and 2.267(79.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      0.235
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.235

    - Propagation time:                      2.869
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.633

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done / Q
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_1 / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done       SLE      Q        Out     0.218     0.218 r     -         
bit_align_done                                                                                                                                  Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     A        In      -         0.336 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     Y        Out     0.051     0.387 r     -         
CORERXIODBITALIGN_C3_0_BIT_ALGN_DONE                                                                                                            Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     D        In      -         1.335 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     Y        Out     0.282     1.617 r     -         
PF_IOD_GENERIC_RX_C0_0_training_done_o                                                                                                          Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     A        In      -         1.735 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     Y        Out     0.051     1.786 r     -         
un1_INTERNAL_RST_arst_i                                                                                                                         Net      -        -       1.083     -           34        
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_1                                                                     SLE      ALn      In      -         2.869 r     -         
==========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.869 is 0.602(21.0%) logic and 2.267(79.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      0.235
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.235

    - Propagation time:                      2.869
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -2.633

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done / Q
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_2 / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV [rising] (rise=0.000 fall=8.000 period=16.000) on pin CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.941 period=5.882) on pin CLK

Instance / Net                                                                                                                                           Pin      Pin               Arrival     No. of    
Name                                                                                                                                            Type     Name     Dir     Delay     Time        Fan Out(s)
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.bit_align_done       SLE      Q        Out     0.218     0.218 r     -         
bit_align_done                                                                                                                                  Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     A        In      -         0.336 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rx_BIT_ALGN_DONE     CFG2     Y        Out     0.051     0.387 r     -         
CORERXIODBITALIGN_C3_0_BIT_ALGN_DONE                                                                                                            Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     D        In      -         1.335 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.AND4_0                                                                                 AND4     Y        Out     0.282     1.617 r     -         
PF_IOD_GENERIC_RX_C0_0_training_done_o                                                                                                          Net      -        -       0.118     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     A        In      -         1.735 r     -         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.un1_D                                                                     CFG3     Y        Out     0.051     1.786 r     -         
un1_INTERNAL_RST_arst_i                                                                                                                         Net      -        -       1.083     -           34        
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff_2                                                                     SLE      ALn      In      -         2.869 r     -         
==========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 2.869 is 0.602(21.0%) logic and 2.267(79.0%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R
====================================



Starting Points with Worst Slack
********************************

                                                                                                                                             Starting                                                                                              Arrival           
Instance                                                                                                                                     Reference                                                    Type     Pin     Net                     Time        Slack 
                                                                                                                                             Clock                                                                                                                   
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[8]          0.218       -4.095
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[4]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[4]          0.218       -3.999
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[5]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[5]          0.218       -3.954
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_fast[7]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter_fast[7]     0.218       -3.691
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_fast[6]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter_fast[6]     0.218       -3.650
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[9]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[9]          0.218       -3.466
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[0]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[0]          0.201       -3.449
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[1]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[1]          0.218       -3.375
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[2]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[2]          0.201       -3.333
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[3]          DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      Q       s_v_counter[3]          0.218       -3.147
=====================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                             Starting                                                                                   Required           
Instance                                                     Reference                                                    Type     Pin     Net          Time         Slack 
                                                             Clock                                                                                                         
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[0]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[1]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[2]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[3]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[4]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[5]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[6]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[7]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[8]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[9]     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R     SLE      ALn     AND2_0_Y     0.004        -4.095
===========================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      4.099
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.095

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8] / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[0] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]              SLE      Q        Out     0.218     0.218 r     -         
s_v_counter[8]                                                                                                                                   Net      -        -       0.563     -           4         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     D        In      -         0.782 r     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     Y        Out     0.212     0.994 f     -         
N_234                                                                                                                                            Net      -        -       0.803     -           26        
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     A        In      -         1.797 f     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     Y        Out     0.047     1.844 r     -         
Display_Controller_Camera_FRAME_END_O_i                                                                                                          Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     B        In      -         2.792 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     Y        Out     0.169     2.961 r     -         
AND2_0_Y                                                                                                                                         Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wbin[0]                                                                                         SLE      ALn      In      -         4.099 r     -         
===========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.099 is 0.647(15.8%) logic and 3.453(84.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 2: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      4.099
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.095

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8] / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[0] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]              SLE      Q        Out     0.218     0.218 r     -         
s_v_counter[8]                                                                                                                                   Net      -        -       0.563     -           4         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     D        In      -         0.782 r     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     Y        Out     0.212     0.994 f     -         
N_234                                                                                                                                            Net      -        -       0.803     -           26        
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     A        In      -         1.797 f     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     Y        Out     0.047     1.844 r     -         
Display_Controller_Camera_FRAME_END_O_i                                                                                                          Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     B        In      -         2.792 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     Y        Out     0.169     2.961 r     -         
AND2_0_Y                                                                                                                                         Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[0]                                                                                         SLE      ALn      In      -         4.099 r     -         
===========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.099 is 0.647(15.8%) logic and 3.453(84.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 3: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      4.099
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.095

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8] / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[1] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]              SLE      Q        Out     0.218     0.218 r     -         
s_v_counter[8]                                                                                                                                   Net      -        -       0.563     -           4         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     D        In      -         0.782 r     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     Y        Out     0.212     0.994 f     -         
N_234                                                                                                                                            Net      -        -       0.803     -           26        
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     A        In      -         1.797 f     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     Y        Out     0.047     1.844 r     -         
Display_Controller_Camera_FRAME_END_O_i                                                                                                          Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     B        In      -         2.792 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     Y        Out     0.169     2.961 r     -         
AND2_0_Y                                                                                                                                         Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[1]                                                                                         SLE      ALn      In      -         4.099 r     -         
===========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.099 is 0.647(15.8%) logic and 3.453(84.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 4: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      4.099
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.095

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8] / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[2] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]              SLE      Q        Out     0.218     0.218 r     -         
s_v_counter[8]                                                                                                                                   Net      -        -       0.563     -           4         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     D        In      -         0.782 r     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     Y        Out     0.212     0.994 f     -         
N_234                                                                                                                                            Net      -        -       0.803     -           26        
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     A        In      -         1.797 f     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     Y        Out     0.047     1.844 r     -         
Display_Controller_Camera_FRAME_END_O_i                                                                                                          Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     B        In      -         2.792 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     Y        Out     0.169     2.961 r     -         
AND2_0_Y                                                                                                                                         Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[2]                                                                                         SLE      ALn      In      -         4.099 r     -         
===========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.099 is 0.647(15.8%) logic and 3.453(84.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value


Path information for path number 5: 
      Requested Period:                      0.004
    - Setup time:                            0.000
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         0.004

    - Propagation time:                      4.099
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -4.095

    Number of logic level(s):                3
    Starting point:                          DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8] / Q
    Ending point:                            DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[3] / ALn
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin CLK
    The end   point is clocked by            CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK

Instance / Net                                                                                                                                            Pin      Pin               Arrival     No. of    
Name                                                                                                                                             Type     Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter[8]              SLE      Q        Out     0.218     0.218 r     -         
s_v_counter[8]                                                                                                                                   Net      -        -       0.563     -           4         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     D        In      -         0.782 r     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNINAJR[4]      CFG4     Y        Out     0.212     0.994 f     -         
N_234                                                                                                                                            Net      -        -       0.803     -           26        
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     A        In      -         1.797 f     -         
DDR4_RD_WR_inst_0.Display_Controller_Camera.Display_Controller_C0_0.DC_Native_FORMAT\.Display_Controller_Native_INST.s_v_counter_RNI53112[3]     CFG4     Y        Out     0.047     1.844 r     -         
Display_Controller_Camera_FRAME_END_O_i                                                                                                          Net      -        -       0.948     -           1         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     B        In      -         2.792 r     -         
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.AND2_0                                                                                                       AND2     Y        Out     0.169     2.961 r     -         
AND2_0_Y                                                                                                                                         Net      -        -       1.138     -           141       
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.video_fifo_0.wptr[3]                                                                                         SLE      ALn      In      -         4.099 r     -         
===========================================================================================================================================================================================================
Total path delay (propagation time + setup) of 4.099 is 0.647(15.8%) logic and 3.453(84.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R
====================================



Starting Points with Worst Slack
********************************

                                                                                                                                                           Starting                                                                                                            Arrival          
Instance                                                                                                                                                   Reference                                                    Type        Pin           Net                          Time        Slack
                                                                                                                                                           Clock                                                                                                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[8]     HDMI_TX_C0_0_TMDS_B_O[8]     3.023       8.247
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[3]     HDMI_TX_C0_0_TMDS_B_O[3]     3.023       8.268
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[0]     HDMI_TX_C0_0_TMDS_B_O[0]     3.023       8.285
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[1]     HDMI_TX_C0_0_TMDS_B_O[1]     3.023       8.296
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[6]     HDMI_TX_C0_0_TMDS_B_O[6]     3.023       8.298
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[5]     HDMI_TX_C0_0_TMDS_B_O[5]     3.023       8.308
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[4]     HDMI_TX_C0_0_TMDS_B_O[4]     3.023       8.309
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[9]     HDMI_TX_C0_0_TMDS_B_O[9]     3.023       8.320
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[2]     HDMI_TX_C0_0_TMDS_B_O[2]     3.023       8.323
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     RAM1K20     A_DOUT[7]     HDMI_TX_C0_0_TMDS_B_O[7]     3.023       8.327
================================================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                    Starting                                                                                                              Required          
Instance                                            Reference                                                    Type         Pin            Net                          Time         Slack
                                                    Clock                                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[8]     HDMI_TX_C0_0_TMDS_B_O[8]     12.218       8.247
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[3]     HDMI_TX_C0_0_TMDS_B_O[3]     12.239       8.268
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[0]     HDMI_TX_C0_0_TMDS_B_O[0]     12.256       8.285
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[1]     HDMI_TX_C0_0_TMDS_B_O[1]     12.267       8.296
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[6]     HDMI_TX_C0_0_TMDS_B_O[6]     12.269       8.298
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[5]     HDMI_TX_C0_0_TMDS_B_O[5]     12.279       8.308
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[4]     HDMI_TX_C0_0_TMDS_B_O[4]     12.280       8.309
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[9]     HDMI_TX_C0_0_TMDS_B_O[9]     12.291       8.320
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[2]     HDMI_TX_C0_0_TMDS_B_O[2]     12.294       8.323
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R     XCVR_PMA     TX_DATA[7]     HDMI_TX_C0_0_TMDS_B_O[7]     12.298       8.327
============================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      13.468
    - Setup time:                            1.250
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.218

    - Propagation time:                      3.971
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 8.247

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0 / A_DOUT[8]
    Ending point:                            DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1 / TX_DATA[8]
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin A_CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin TX_FWF_CLK

Instance / Net                                                                                                                                                          Pin            Pin               Arrival     No. of    
Name                                                                                                                                                       Type         Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_b.ram2port_hdmi_tx_inst.ram_ram_0_0     RAM1K20      A_DOUT[8]      Out     3.023     3.023 r     -         
HDMI_TX_C0_0_TMDS_B_O[8]                                                                                                                                   Net          -              -       0.948     -           1         
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE1                                                                                                            XCVR_PMA     TX_DATA[8]     In      -         3.971 r     -         
===============================================================================================================================================================================================================================
Total path delay (propagation time + setup) of 5.221 is 4.273(81.8%) logic and 0.948(18.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R
====================================



Starting Points with Worst Slack
********************************

                                                                                                                                                           Starting                                                                                                            Arrival          
Instance                                                                                                                                                   Reference                                                    Type        Pin           Net                          Time        Slack
                                                                                                                                                           Clock                                                                                                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[8]     HDMI_TX_C0_0_TMDS_G_O[8]     3.023       8.247
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[3]     HDMI_TX_C0_0_TMDS_G_O[3]     3.023       8.268
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[0]     HDMI_TX_C0_0_TMDS_G_O[0]     3.023       8.285
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[1]     HDMI_TX_C0_0_TMDS_G_O[1]     3.023       8.296
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[6]     HDMI_TX_C0_0_TMDS_G_O[6]     3.023       8.298
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[5]     HDMI_TX_C0_0_TMDS_G_O[5]     3.023       8.308
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[4]     HDMI_TX_C0_0_TMDS_G_O[4]     3.023       8.309
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[9]     HDMI_TX_C0_0_TMDS_G_O[9]     3.023       8.320
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[2]     HDMI_TX_C0_0_TMDS_G_O[2]     3.023       8.323
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     RAM1K20     A_DOUT[7]     HDMI_TX_C0_0_TMDS_G_O[7]     3.023       8.327
================================================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                    Starting                                                                                                              Required          
Instance                                            Reference                                                    Type         Pin            Net                          Time         Slack
                                                    Clock                                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[8]     HDMI_TX_C0_0_TMDS_G_O[8]     12.218       8.247
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[3]     HDMI_TX_C0_0_TMDS_G_O[3]     12.239       8.268
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[0]     HDMI_TX_C0_0_TMDS_G_O[0]     12.256       8.285
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[1]     HDMI_TX_C0_0_TMDS_G_O[1]     12.267       8.296
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[6]     HDMI_TX_C0_0_TMDS_G_O[6]     12.269       8.298
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[5]     HDMI_TX_C0_0_TMDS_G_O[5]     12.279       8.308
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[4]     HDMI_TX_C0_0_TMDS_G_O[4]     12.280       8.309
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[9]     HDMI_TX_C0_0_TMDS_G_O[9]     12.291       8.320
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[2]     HDMI_TX_C0_0_TMDS_G_O[2]     12.294       8.323
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R     XCVR_PMA     TX_DATA[7]     HDMI_TX_C0_0_TMDS_G_O[7]     12.298       8.327
============================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      13.468
    - Setup time:                            1.250
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.218

    - Propagation time:                      3.971
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 8.247

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0 / A_DOUT[8]
    Ending point:                            DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2 / TX_DATA[8]
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin A_CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin TX_FWF_CLK

Instance / Net                                                                                                                                                          Pin            Pin               Arrival     No. of    
Name                                                                                                                                                       Type         Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_g.ram2port_hdmi_tx_inst.ram_ram_0_0     RAM1K20      A_DOUT[8]      Out     3.023     3.023 r     -         
HDMI_TX_C0_0_TMDS_G_O[8]                                                                                                                                   Net          -              -       0.948     -           1         
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE2                                                                                                            XCVR_PMA     TX_DATA[8]     In      -         3.971 r     -         
===============================================================================================================================================================================================================================
Total path delay (propagation time + setup) of 5.221 is 4.273(81.8%) logic and 0.948(18.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R
====================================



Starting Points with Worst Slack
********************************

                                                                                                                                                           Starting                                                                                                            Arrival          
Instance                                                                                                                                                   Reference                                                    Type        Pin           Net                          Time        Slack
                                                                                                                                                           Clock                                                                                                                                
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[8]     HDMI_TX_C0_0_TMDS_R_O[8]     3.023       8.247
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[3]     HDMI_TX_C0_0_TMDS_R_O[3]     3.023       8.268
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[0]     HDMI_TX_C0_0_TMDS_R_O[0]     3.023       8.285
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[1]     HDMI_TX_C0_0_TMDS_R_O[1]     3.023       8.296
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[6]     HDMI_TX_C0_0_TMDS_R_O[6]     3.023       8.298
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[5]     HDMI_TX_C0_0_TMDS_R_O[5]     3.023       8.308
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[4]     HDMI_TX_C0_0_TMDS_R_O[4]     3.023       8.309
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[9]     HDMI_TX_C0_0_TMDS_R_O[9]     3.023       8.320
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[2]     HDMI_TX_C0_0_TMDS_R_O[2]     3.023       8.323
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     RAM1K20     A_DOUT[7]     HDMI_TX_C0_0_TMDS_R_O[7]     3.023       8.327
================================================================================================================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                    Starting                                                                                                              Required          
Instance                                            Reference                                                    Type         Pin            Net                          Time         Slack
                                                    Clock                                                                                                                                   
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[8]     HDMI_TX_C0_0_TMDS_R_O[8]     12.218       8.247
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[3]     HDMI_TX_C0_0_TMDS_R_O[3]     12.239       8.268
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[0]     HDMI_TX_C0_0_TMDS_R_O[0]     12.256       8.285
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[1]     HDMI_TX_C0_0_TMDS_R_O[1]     12.267       8.296
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[6]     HDMI_TX_C0_0_TMDS_R_O[6]     12.269       8.298
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[5]     HDMI_TX_C0_0_TMDS_R_O[5]     12.279       8.308
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[4]     HDMI_TX_C0_0_TMDS_R_O[4]     12.280       8.309
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[9]     HDMI_TX_C0_0_TMDS_R_O[9]     12.291       8.320
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[2]     HDMI_TX_C0_0_TMDS_R_O[2]     12.294       8.323
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3     DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R     XCVR_PMA     TX_DATA[7]     HDMI_TX_C0_0_TMDS_R_O[7]     12.298       8.327
============================================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      13.468
    - Setup time:                            1.250
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         12.218

    - Propagation time:                      3.971
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 8.247

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0 / A_DOUT[8]
    Ending point:                            DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3 / TX_DATA[8]
    The start point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin A_CLK
    The end   point is clocked by            DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R [rising] (rise=0.000 fall=8.080 period=13.468) on pin TX_FWF_CLK

Instance / Net                                                                                                                                                          Pin            Pin               Arrival     No. of    
Name                                                                                                                                                       Type         Name           Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT\.HDMI_TX_Native_INST.tx_fifo_top_inst.video_fifo_r.ram2port_hdmi_tx_inst.ram_ram_0_0     RAM1K20      A_DOUT[8]      Out     3.023     3.023 r     -         
HDMI_TX_C0_0_TMDS_R_O[8]                                                                                                                                   Net          -              -       0.948     -           1         
DDR4_RD_WR_inst_0.PF_XCVR_ERM_C0_0.I_XCVR.LANE3                                                                                                            XCVR_PMA     TX_DATA[8]     In      -         3.971 r     -         
===============================================================================================================================================================================================================================
Total path delay (propagation time + setup) of 5.221 is 4.273(81.8%) logic and 0.948(18.2%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value




====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                                                                                                    Starting                                                                          Arrival          
Instance                                                                                            Reference     Type                Pin               Net                           Time        Slack
                                                                                                    Clock                                                                                              
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_0     System        INBUF_DIFF_MIPI     Y                 Y_I_INBUF_DIFF_MIPI_0_net     0.000       1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_1     System        INBUF_DIFF_MIPI     Y                 Y_I_INBUF_DIFF_MIPI_1_net     0.000       1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_2     System        INBUF_DIFF_MIPI     Y                 Y_I_INBUF_DIFF_MIPI_2_net     0.000       1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_3     System        INBUF_DIFF_MIPI     Y                 Y_I_INBUF_DIFF_MIPI_3_net     0.000       1.768
CLOCKS_AND_RESETS_inst_0.INIT_MONITOR_0.INIT_MONITOR_0.I_INIT                                       System        INIT                UIC_INIT_DONE     DEVICE_INIT_DONE              0.000       1.870
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_1_rs              System        SLE                 Q                 un1_reset_i_1_rs              0.218       2.565
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_21_rs             System        SLE                 Q                 un1_reset_i_21_rs             0.218       3.397
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_19_rs             System        SLE                 Q                 un1_reset_i_19_rs             0.218       3.405
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_9_rs              System        SLE                 Q                 un1_reset_i_9_rs              0.218       3.413
DDR4_RD_WR_inst_0.DDR_Read_LPDDR4_0.DDR_read_controller_FHD_HDMI_RX_0.un1_reset_i_16_rs             System        SLE                 Q                 un1_reset_i_16_rs             0.218       3.421
=======================================================================================================================================================================================================


Ending Points with Worst Slack
******************************

                                                                                        Starting                                                      Required          
Instance                                                                                Reference     Type     Pin      Net                           Time         Slack
                                                                                        Clock                                                                           
------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_0     System        IOD      RX_P     Y_I_INBUF_DIFF_MIPI_0_net     2.716        1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_1     System        IOD      RX_P     Y_I_INBUF_DIFF_MIPI_1_net     2.716        1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_2     System        IOD      RX_P     Y_I_INBUF_DIFF_MIPI_2_net     2.716        1.768
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_3     System        IOD      RX_P     Y_I_INBUF_DIFF_MIPI_3_net     2.716        1.768
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_0                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_1                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_2                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_3                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_4                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff_5                   System        SLE      ALn      un1_INTERNAL_RST_arst_i       4.980        1.870
========================================================================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.000
    - Setup time:                            1.284
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         2.716

    - Propagation time:                      0.948
    - Clock delay at starting point:         0.000 (ideal)
    - Estimated clock delay at start point:  -0.000
    = Slack (non-critical) :                 1.768

    Number of logic level(s):                0
    Starting point:                          DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_0 / Y
    Ending point:                            DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_0 / RX_P
    The start point is clocked by            System [rising]
    The end   point is clocked by            CAM1_RX_CLK_P [rising] (rise=0.000 fall=2.000 period=4.000) on pin RX_DQS_90[0]

Instance / Net                                                                                                          Pin      Pin               Arrival     No. of    
Name                                                                                                Type                Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_INBUF_DIFF_MIPI_0     INBUF_DIFF_MIPI     Y        Out     0.000     0.000 r     -         
Y_I_INBUF_DIFF_MIPI_0_net                                                                           Net                 -        -       0.948     -           1         
DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_IOD_RX.I_IOD_0                 IOD                 RX_P     In      -         0.948 r     -         
=========================================================================================================================================================================
Total path delay (propagation time + setup) of 2.232 is 1.284(57.5%) logic and 0.948(42.5%) route.
Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value



##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
@W:MT447 : synthesis.fdc(50) | Timing constraint (to [get_pins { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL*.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
None

Finished final timing analysis (Real Time elapsed 0h:01m:34s; CPU Time elapsed 0h:00m:30s; Memory used current: 276MB peak: 337MB)


Finished timing report (Real Time elapsed 0h:01m:34s; CPU Time elapsed 0h:00m:30s; Memory used current: 276MB peak: 337MB)

---------------------------------------
Resource Usage Report for SEV_PFSoC_OpenVX 

Mapping to part: mpfs250tfcg1152-1
Cell usage:
AND2            6 uses
AND3            1 use
AND4            1 use
BANKCTRL_GPIO   2 uses
BANKCTRL_HSIO   1 use
CLKINT          12 uses
DFN1            1 use
HS_IO_CLK       3 uses
ICB_CLKDIV      1 use
ICB_CLKDIVDELAY  2 uses
INBUF_DIFF_MIPI  4 uses
INIT            1 use
INV             2 uses
IOD             5 uses
LANECTRL        1 use
MSS             1 use
MX2             1 use
OSC_RC2MHZ      1 use
PLL             3 uses
RCLKINT         4 uses
TX_PLL          1 use
XCVR_PMA        4 uses
XCVR_REF_CLK    1 use
CFG1           81 uses
CFG2           1809 uses
CFG3           3047 uses
CFG4           4436 uses

Carry cells:
ARI1            1860 uses - used for arithmetic functions
ARI1            2633 uses - used for Wide-Mux implementation
Total ARI1      4493 uses


Sequential Cells: 
SLE            12289 uses

DSP Blocks:   17 of 784 (2%)
 MACC_PA:        10 MultAdds
 MACC_PA:         5 Mults
 MACC_PA:         2 MultSubs

I/O ports: 132
I/O primitives: 105
BIBUF          52 uses
BIBUF_DIFF     4 uses
INBUF          6 uses
INBUF_DIFF     3 uses
OUTBUF         38 uses
OUTBUF_DIFF    2 uses


Global Clock Buffers: 16

RAM/ROM usage summary
Total Block RAMs (RAM1K20) : 147 of 812 (18%)
Total Block RAMs (RAM64x12) : 6 of 2352 (0%)

Total LUTs:    13866

Extra resources required for RAM and MACC_PA interface logic during P&R:

RAM64X12 Interface Logic : SLEs = 72; LUTs = 72;
RAM1K20  Interface Logic : SLEs = 5292; LUTs = 5292;
MACC_PA     Interface Logic : SLEs = 612; LUTs = 612;
MACC_PA_BC_ROM     Interface Logic : SLEs = 0; LUTs = 0;

Total number of SLEs after P&R:  12289 + 72 + 5292 + 612 = 18265;
Total number of LUTs after P&R:  13866 + 72 + 5292 + 612 = 19842;

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:01m:35s; CPU Time elapsed 0h:00m:31s; Memory used current: 89MB peak: 337MB)

Process took 0h:01m:35s realtime, 0h:00m:31s cputime
# Mon Nov 21 15:28:02 2022

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