@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.
@W: FX1183 :"d:\delme\sev_pfsoc_openvx\component\work\corereset_pf_c3\corereset_pf_c3_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_50MHz.CORERESET_PF_C3_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: FX1183 :"d:\delme\sev_pfsoc_openvx\component\work\corereset_pf_c4\corereset_pf_c4_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance CLOCKS_AND_RESETS_inst_0.CORERESET_CLK_200MHz.CORERESET_PF_C4_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: BN114 :"d:\delme\sev_pfsoc_openvx\component\work\pf_osc_c0\pf_osc_c0_0\pf_osc_c0_pf_osc_c0_0_pf_osc.v":15:8:15:15|Removing instance gnd_inst (in view: work.PF_OSC_C0_PF_OSC_C0_0_PF_OSC(verilog)) because it does not drive other instances.
@W: BN114 :"d:\delme\sev_pfsoc_openvx\component\work\pf_xcvr_ref_clk_c0\pf_xcvr_ref_clk_c0_0\pf_xcvr_ref_clk_c0_pf_xcvr_ref_clk_c0_0_pf_xcvr_ref_clk.v":26:8:26:15|Removing instance vcc_inst (in view: work.PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK(verilog)) because it does not drive other instances.
@W: BN114 :"d:\delme\sev_pfsoc_openvx\component\work\pf_xcvr_ref_clk_c0\pf_xcvr_ref_clk_c0_0\pf_xcvr_ref_clk_c0_pf_xcvr_ref_clk_c0_0_pf_xcvr_ref_clk.v":27:8:27:15|Removing instance gnd_inst (in view: work.PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK(verilog)) because it does not drive other instances.
@W: FX1183 :"d:\delme\sev_pfsoc_openvx\component\work\corereset_pf_c0\corereset_pf_c0_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance DDR4_RD_WR_inst_0.CORERESET_PF_148p5MHz.CORERESET_PF_C0_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: BN132 :"d:\delme\sev_pfsoc_openvx\hdl\data_packer_lpddr4.vhd":205:4:205:5|Removing sequential instance DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_dv_fe_ctr_en because it is equivalent to instance DDR4_RD_WR_inst_0.DDR_Write_LPDDR4_0.data_packer_0.s_ddr_start. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX1183 :"d:\delme\sev_pfsoc_openvx\component\work\corereset_pf_c1\corereset_pf_c1_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERESET_PF_C1_0.CORERESET_PF_C1_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: FX1183 :"d:\delme\sev_pfsoc_openvx\component\work\corereset_pf_c2\corereset_pf_c2_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CORERESET_PF_C2_0.CORERESET_PF_C2_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: BN114 :"d:\delme\sev_pfsoc_openvx\component\work\pf_iod_generic_rx_c0\pf_iod_clk_training\pf_iod_generic_rx_c0_pf_iod_clk_training_pf_iod.v":32:8:32:15|Removing instance vcc_inst (in view: work.PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD(verilog)) because it does not drive other instances.
@W: BN114 :"d:\delme\sev_pfsoc_openvx\component\work\pf_iod_generic_rx_c0\pf_iod_rx\pf_iod_generic_rx_c0_pf_iod_rx_pf_iod.v":262:8:262:15|Removing instance vcc_inst (in view: work.PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD(verilog)) because it does not drive other instances.
@W: FX1172 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\hdmi_tx\4.4.0\hdl\hdmi_tx.vhd":756:4:756:5|User-specified initial value defined for instance DDR4_RD_WR_inst_0.HDMI_TX_C0_0.HDMI_TX_C0_0.HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST.TMDS_B_generate.1.tmds_b.dc_bias[3:0] is being ignored due to limitations in architecture. 
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ASIZE[2:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.ASIZE_reg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.max_length_comb_pre[8:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ASIZE[2:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.max_length_comb_pre[8:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c0\corerxiodbitalign_c0_0\rtl\vlog\core\corerxiodbitalign.v":1099:3:1099:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.CORERXIODBITALIGN_C0_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":1099:3:1099:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":1099:3:1099:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":1099:3:1099:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":660:3:660:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.PF_IOD_GENERIC_RX_C0_TR_0.genblk1.U_ICB_BCLKSCLKALIGN.internal_rst_en_2 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":652:3:652:8|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.PF_IOD_GENERIC_RX_C0_TR_0.genblk1.U_ICB_BCLKSCLKALIGN.internal_rst_en_1 is reduced to a combinational gate by constant propagation.
@W: BN117 :"d:\delme\sev_pfsoc_openvx\component\work\rgbtoycbcr_c0\rgbtoycbcr_c0.vhd":127:0:127:14|Instance RGBtoYCbCr_C0_0 of partition view:work.RGBtoYCbCr_8_8_2_0_1(rtl) has no references to its outputs; instance not removed. 
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req1_dly is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req2_dly is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.write_top_0.request_scheduler_0.s_req3_dly is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req1_dly is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req2_dly is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\hdl\request_scheduler.vhd":121:4:121:5|Sequential instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.read_top_0.request_scheduler_0.s_req3_dly is reduced to a combinational gate by constant propagation.
@W: BN117 :"d:\delme\sev_pfsoc_openvx\component\work\ycbcrtorgb_c0\ycbcrtorgb_c0.vhd":137:0:137:14|Instance YCbCrtoRGB_C0_0 of partition view:work.YCbCrtoRGB_8_8_2_0_1(rtl) has no references to its outputs; instance not removed. 
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.unaligned_fixed_len_iter_pre[0] is reduced to a combinational gate by constant propagation.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.mask_addr_pre_1[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ABURST_out[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ASIZE_out[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_out[31:0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[31:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.MASTER_ABURST_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.MASTER_ASIZE_reg[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.max_length[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.length[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.unaligned_fixed_len_iter_pre[0] is reduced to a combinational gate by constant propagation.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.mask_addr_pre_1[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ABURST_out[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_ASIZE_out[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[31:9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_out[31:9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.MASTER_ABURST_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.max_length[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.length[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.MASTER_ASIZE_reg[2:1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.ASIZE_reg[1:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":377:3:377:8|Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WUSER[0] is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":915:3:915:8|Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.fixed_burst_f1 is reduced to a combinational gate by constant propagation.
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":907:3:907:8|Sequential instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.writeWidthConv.widthConvwr.fixed_burst_det_reg is reduced to a combinational gate by constant propagation.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: MF511 |Found issues with constraints. Please check constraint checker report "D:\Delme\SEV_PFSoC_OpenVX\synthesis\SEV_PFSoC_OpenVX_cck.rpt" .
