@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":21:13:21:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":61:13:61:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":88:13:88:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":118:13:118:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":168:13:168:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":213:13:213:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":232:13:232:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":281:13:281:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":335:13:335:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":657:13:657:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":761:13:761:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":795:13:795:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1059:13:1059:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1369:13:1369:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1396:13:1396:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1441:13:1441:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1474:13:1474:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1492:13:1492:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1518:13:1518:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1559:13:1559:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1581:13:1581:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1599:13:1599:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1616:13:1616:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1635:13:1635:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1652:13:1652:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1681:13:1681:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1712:13:1712:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1802:13:1802:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2026:13:2026:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2187:13:2187:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2203:13:2203:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2219:13:2219:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2235:13:2235:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2267:13:2267:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2648:13:2648:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3661:13:3661:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3732:13:3732:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3861:13:3861:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3879:13:3879:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3896:13:3896:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3911:13:3911:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3926:13:3926:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3953:13:3953:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4065:13:4065:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4096:13:4096:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4142:13:4142:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4252:13:4252:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4436:13:4436:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4477:13:4477:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4503:13:4503:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4520:13:4520:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4597:13:4597:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":5361:13:5361:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6171:13:6171:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6280:13:6280:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6318:13:6318:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6391:13:6391:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":7280:13:7280:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":8337:13:8337:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":9296:13:9296:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10032:13:10032:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10747:13:10747:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10781:13:10781:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10817:13:10817:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10864:13:10864:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10898:13:10898:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":11764:13:11764:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12807:13:12807:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12819:15:12819:27|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12830:13:12830:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12843:13:12843:25|User defined pragma syn_black_box detected
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v":288:10:288:29|Net almostfulli_deassert is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v":293:10:293:30|Net almostemptyi_deassert is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHBL_Ctrl.v":297:9:297:26|Net axi_read_not_ready is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":457:10:457:18|Net addr_beat is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":461:10:461:13|Net mask is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":498:10:498:14|Net FIXED is not declared.
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v":798:13:798:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":21:13:21:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":61:13:61:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":88:13:88:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":118:13:118:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":168:13:168:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":213:13:213:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":232:13:232:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":281:13:281:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":335:13:335:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":657:13:657:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":761:13:761:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":795:13:795:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1059:13:1059:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1369:13:1369:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1396:13:1396:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1441:13:1441:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1474:13:1474:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1492:13:1492:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1518:13:1518:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1559:13:1559:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1581:13:1581:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1599:13:1599:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1616:13:1616:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1635:13:1635:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1652:13:1652:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1681:13:1681:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1712:13:1712:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":1802:13:1802:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2026:13:2026:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2187:13:2187:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2203:13:2203:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2219:13:2219:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2235:13:2235:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2267:13:2267:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":2648:13:2648:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3661:13:3661:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3732:13:3732:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3861:13:3861:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3879:13:3879:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3896:13:3896:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3911:13:3911:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3926:13:3926:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":3953:13:3953:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4065:13:4065:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4096:13:4096:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4142:13:4142:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4252:13:4252:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4436:13:4436:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4477:13:4477:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4503:13:4503:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4520:13:4520:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":4597:13:4597:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":5361:13:5361:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6171:13:6171:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6280:13:6280:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6318:13:6318:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":6391:13:6391:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":7280:13:7280:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":8337:13:8337:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":9296:13:9296:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10032:13:10032:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10747:13:10747:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10781:13:10781:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10817:13:10817:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10864:13:10864:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":10898:13:10898:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":11764:13:11764:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12807:13:12807:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12819:15:12819:27|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12830:13:12830:25|User defined pragma syn_black_box detected
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\polarfire_syn_comps.v":12843:13:12843:25|User defined pragma syn_black_box detected
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v":288:10:288:29|Net almostfulli_deassert is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync.v":293:10:293:30|Net almostemptyi_deassert is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\AHBL_Ctrl.v":297:9:297:26|Net axi_read_not_ready is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":457:10:457:18|Net addr_beat is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":461:10:461:13|Net mask is not declared.
@W: CG1337 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_UpConv_AChannel.v":498:10:498:14|Net FIXED is not declared.
@W: CG100 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\MSS_SEV\MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v":798:13:798:25|User defined pragma syn_black_box detected
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":44:53:44:58|Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":44:53:44:58|Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":44:53:44:58|Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":44:53:44:58|Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":44:53:44:58|Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":55:12:55:25|Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_GPIO_7 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":63:12:63:25|Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_HSIO_8 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\INIT_MONITOR\INIT_MONITOR_0\INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v":71:12:71:25|Type of parameter CALIB_STATUS_SIMULATION_DELAY on the instance I_BCTRL_GPIO_9 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C0\PF_CCC_C0_0\PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v":37:27:37:36|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C1\PF_CCC_C1_0\PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v":37:12:37:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register overflow. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register overflow1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register rdaddr_r_bin[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register wraddr_sync_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register wraddr_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register rdaddr_sync_rr_bin[7:0]. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1706:27:1706:35|Removing wire L4_DATA_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1707:27:1707:35|Removing wire L5_DATA_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1708:27:1708:35|Removing wire L6_DATA_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1709:27:1709:35|Removing wire L7_DATA_O, as there is no assignment to it.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1786:15:1786:29|Object L4_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1787:18:1787:32|Object L5_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1788:18:1788:32|Object L6_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1789:18:1789:32|Object L7_data_in_reg0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1794:17:1794:31|Object L4_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1795:18:1795:32|Object L5_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1796:18:1796:32|Object L6_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1797:18:1797:32|Object L7_data_in_reg1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1802:16:1802:30|Object L4_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1803:18:1803:32|Object L5_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1804:18:1804:32|Object L6_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1805:18:1805:32|Object L7_data_in_reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1810:15:1810:29|Object L4_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1811:18:1811:32|Object L5_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1812:18:1812:32|Object L6_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1813:18:1813:32|Object L7_data_in_reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1818:16:1818:30|Object L4_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1819:18:1819:32|Object L5_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1820:18:1820:32|Object L6_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1821:18:1821:32|Object L7_data_in_reg4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1826:15:1826:29|Object L4_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1827:18:1827:32|Object L5_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1828:18:1828:32|Object L6_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1829:18:1829:32|Object L7_data_in_reg5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1834:15:1834:29|Object L4_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1835:18:1835:32|Object L5_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1836:18:1836:32|Object L6_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1837:18:1837:32|Object L7_data_in_reg6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1842:15:1842:27|Object L4_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1843:18:1843:30|Object L5_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1844:18:1844:30|Object L6_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1845:18:1845:30|Object L7_bit_adjust is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1850:15:1850:25|Object L4_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1851:18:1851:28|Object L5_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1852:18:1852:28|Object L6_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1853:18:1853:28|Object L7_data_out is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1858:15:1858:27|Removing wire L4_data_out_r, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1859:18:1859:30|Removing wire L5_data_out_r, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1860:18:1860:30|Removing wire L6_data_out_r, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1861:18:1861:30|Removing wire L7_data_out_r, as there is no assignment to it.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1866:17:1866:30|Object L4_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1867:18:1867:31|Object L5_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1868:18:1868:31|Object L6_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1869:18:1869:31|Object L7_sync_detect is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:18:1874:24|Object q_in4_0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:27:1874:33|Object q_in4_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:36:1874:42|Object q_in4_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:45:1874:51|Object q_in4_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:54:1874:60|Object q_in4_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:63:1874:69|Object q_in4_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:72:1874:78|Object q_in4_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1874:81:1874:87|Object q_in4_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:18:1875:24|Object q_in5_0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:27:1875:33|Object q_in5_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:36:1875:42|Object q_in5_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:45:1875:51|Object q_in5_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:54:1875:60|Object q_in5_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:63:1875:69|Object q_in5_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:72:1875:78|Object q_in5_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1875:81:1875:87|Object q_in5_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:18:1876:24|Object q_in6_0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:27:1876:33|Object q_in6_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:36:1876:42|Object q_in6_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:45:1876:51|Object q_in6_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:54:1876:60|Object q_in6_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:63:1876:69|Object q_in6_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:72:1876:78|Object q_in6_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1876:81:1876:87|Object q_in6_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:18:1877:24|Object q_in7_0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:27:1877:33|Object q_in7_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:36:1877:42|Object q_in7_2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:45:1877:51|Object q_in7_3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:54:1877:60|Object q_in7_4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:63:1877:69|Object q_in7_5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:72:1877:78|Object q_in7_6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1877:81:1877:87|Object q_in7_7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1879:47:1879:51|Object sync4 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1879:54:1879:58|Object sync5 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1879:61:1879:65|Object sync6 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1879:68:1879:72|Object sync7 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1881:19:1881:27|Object sync4_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1881:30:1881:38|Object sync5_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1881:41:1881:49|Object sync6_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1881:52:1881:60|Object sync7_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1706:27:1706:35|*Output L4_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1707:27:1707:35|*Output L5_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1708:27:1708:35|*Output L6_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1709:27:1709:35|*Output L7_DATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4231:7:4231:12|Pruning unused register genblk12.q_in3_4[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4231:7:4231:12|Pruning unused register genblk12.q_in3_5[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4231:7:4231:12|Pruning unused register genblk12.q_in3_6[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4231:7:4231:12|Pruning unused register genblk12.q_in3_7[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4201:7:4201:12|Pruning unused register genblk11.q_in2_4[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4201:7:4201:12|Pruning unused register genblk11.q_in2_5[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4201:7:4201:12|Pruning unused register genblk11.q_in2_6[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4201:7:4201:12|Pruning unused register genblk11.q_in2_7[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4171:7:4171:12|Pruning unused register genblk10.q_in1_4[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4171:7:4171:12|Pruning unused register genblk10.q_in1_5[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4171:7:4171:12|Pruning unused register genblk10.q_in1_6[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4171:7:4171:12|Pruning unused register genblk10.q_in1_7[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4141:8:4141:13|Pruning unused register genblk9.q_in0_4[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4141:8:4141:13|Pruning unused register genblk9.q_in0_5[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4141:8:4141:13|Pruning unused register genblk9.q_in0_6[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4141:8:4141:13|Pruning unused register genblk9.q_in0_7[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2801:2:2801:7|Pruning unused register genblk1.state_7[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2801:2:2801:7|Pruning unused register genblk1.sync_start7. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2740:2:2740:7|Pruning unused register genblk1.state_6[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2740:2:2740:7|Pruning unused register genblk1.sync_start6. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2679:2:2679:7|Pruning unused register genblk1.state_5[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2679:2:2679:7|Pruning unused register genblk1.sync_start5. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2618:2:2618:7|Pruning unused register genblk1.state_4[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":2618:2:2618:7|Pruning unused register genblk1.sync_start4. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused register L4_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused register L5_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused register L6_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused register L7_LP_DATA_N_reg[15:0]. Make sure that there are no unused intermediate registers.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4445:2:4445:7|Pruning unused bits 10 to 5 of q_sync_detect_all_lanes[10:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused bits 15 to 8 of L0_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused bits 15 to 8 of L1_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused bits 15 to 8 of L2_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1914:0:1914:5|Pruning unused bits 15 to 8 of L3_LP_DATA_N_reg[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register overflow. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register overflow1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register rdaddr_r_bin[11:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6543:2:6543:7|Pruning unused register wraddr_sync_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register wraddr_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6450:2:6450:7|Pruning unused register rdaddr_sync_rr_bin[11:0]. Make sure that there are no unused intermediate registers.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4729:36:4729:39|Object reg2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4730:36:4730:39|Object reg3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4737:44:4737:49|Object rd_cnt is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4742:44:4742:63|Object pix_distribute_2lane is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4743:44:4743:56|Object pix_cnt_2lane is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4746:44:4746:63|Object pix_distribute_8lane is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6066:2:6066:7|Pruning unused register byte_data_arranged_2[39:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6066:2:6066:7|Pruning unused register byte_data_arranged_3[39:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6066:2:6066:7|Pruning unused register byte_data_arranged_4[39:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6066:2:6066:7|Pruning unused register byte_data_arranged_5[39:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4825:3:4825:8|Pruning unused register genblk2.reg1[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4752:2:4752:7|Pruning unused register byte_en1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4752:2:4752:7|Pruning unused register byte_en2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":4752:2:4752:7|Pruning unused register b2p_fv_reg. Make sure that there are no unused intermediate registers.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6033:2:6033:7|Pruning unused bits 8 to 3 of read_en_reg[8:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":465:54:465:68|Object serial_data_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.frame_start_out. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.frame_end_out. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.line_start_out. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.fn_1[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.fn_0[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.fn_end_1[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.fn_end_0[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.wc1[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.wc2[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning unused register genblk2.line_end_out. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":720:2:720:7|Pruning unused register shift_reg[15:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":651:2:651:7|Pruning unused register data_in_reverse_L7[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":634:2:634:7|Pruning unused register data_in_reverse_L6[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":617:2:617:7|Pruning unused register data_in_reverse_L5[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":600:2:600:7|Pruning unused register data_in_reverse_L4[7:0]. Make sure that there are no unused intermediate registers.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1514:2:1514:7|All reachable assignments to bit 6 of data_type_o[7:0] assign 0, register removed by optimization.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1514:2:1514:7|All reachable assignments to bit 7 of data_type_o[7:0] assign 0, register removed by optimization.
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L0_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L1_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L2_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L3_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L4_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L5_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L6_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":76:9:76:29|Input L7_LP_DATA_I on instance mipicsi2rxdecoderPF_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":51:46:51:52|Removing wire TDATA_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":52:46:52:52|Removing wire TSTRB_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":53:46:53:52|Removing wire TKEEP_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":54:38:54:45|Removing wire TVALID_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":55:38:55:44|Removing wire TLAST_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":56:40:56:46|Removing wire TUSER_O, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":62:44:62:51|Removing wire axi_data, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":63:35:63:41|Removing wire sof_axi, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":64:35:64:49|Removing wire frame_valid_axi, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":65:35:65:48|Removing wire line_valid_axi, as there is no assignment to it.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":51:46:51:52|*Output TDATA_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":52:46:52:52|*Output TSTRB_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":53:46:53:52|*Output TKEEP_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":54:38:54:45|*Output TVALID_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":55:38:55:44|*Output TLAST_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":56:40:56:46|*Output TUSER_O has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_CCC_C2\PF_CCC_C2_0\PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v":37:12:37:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":177:8:177:15|Removing wire re_train, as there is no assignment to it.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":1031:3:1031:8|All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C0\CORERXIODBITALIGN_C0_0\rtl\vlog\core\CoreRxIODBitAlign_top.v":68:8:68:16|Removing wire HS_RESETN, as there is no assignment to it.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":177:8:177:15|Removing wire re_train, as there is no assignment to it.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":1031:3:1031:8|All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C1\CORERXIODBITALIGN_C1_0\rtl\vlog\core\CoreRxIODBitAlign_top.v":68:8:68:16|Removing wire HS_RESETN, as there is no assignment to it.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":177:8:177:15|Removing wire re_train, as there is no assignment to it.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":1031:3:1031:8|All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\rtl\vlog\core\CoreRxIODBitAlign_top.v":68:8:68:16|Removing wire HS_RESETN, as there is no assignment to it.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":245:34:245:47|Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":177:8:177:15|Removing wire re_train, as there is no assignment to it.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Pruning unused bits 1 to 0 of skip_trng_reg[2:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final_upd[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL208 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":1031:3:1031:8|All reachable assignments to bit 0 of retrain_reg[2:0] assign 0, register removed by optimization.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|Feedback mux created for signal skip_trng_reg[2:2]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":982:3:982:8|All reachable assignments to skip_trng_reg[2] assign 0, register removed by optimization
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Optimizing register bit bitalign_hold_state[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Optimizing register bit internal_rst_en_2 to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":269:3:269:8|Pruning unused register bitalign_hold_state[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign.v":1107:3:1107:8|Pruning unused register internal_rst_en_2. Make sure that there are no unused intermediate registers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\CORERXIODBITALIGN_C3\CORERXIODBITALIGN_C3_0\rtl\vlog\core\CoreRxIODBitAlign_top.v":68:8:68:16|Removing wire HS_RESETN, as there is no assignment to it.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":180:44:180:57|Index into variable early_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":180:44:180:57|Index into variable late_flags_lsb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":180:44:180:57|Index into variable early_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":180:44:180:57|Index into variable late_flags_msb could be out of range ; a simulation mismatch is possible.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":959:3:959:8|Removing unused bit 8 of tapcnt_final[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":761:3:761:8|Removing unused bit 8 of sig_tapcnt_final_2[8:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREBCLKSCLKALIGN\2.0.111\rtl\vlog\core\ICB_BclkSclkAlign.v":737:3:737:8|Removing unused bit 8 of sig_tapcnt_final_1[8:0]. Either assign all bits or reduce the width of the signal.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":82:11:82:31|Removing wire PLL_VCOPHSEL_SCLK_SEL, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":83:11:83:31|Removing wire PLL_VCOPHSEL_BCLK_SEL, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":84:11:84:33|Removing wire PLL_VCOPHSEL_BCLK90_SEL, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":85:11:85:31|Removing wire PLL_VCOPHSEL_MCLK_SEL, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":86:11:86:21|Removing wire PLL_LOADPHS, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":87:11:87:24|Removing wire PLL_PHS_ROTATE, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":88:11:88:27|Removing wire PLL_PHS_DIRECTION, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":99:17:99:38|Removing wire BCLKSCLK_BCLK_VCOPHSEL, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":124:9:124:31|Removing wire PLL_BCLKSCLK_TRAIN_DONE, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":150:10:150:27|Removing wire PLL_CLK_ALGN_PAUSE, as there is no assignment to it.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":82:11:82:31|*Output PLL_VCOPHSEL_SCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":83:11:83:31|*Output PLL_VCOPHSEL_BCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":84:11:84:33|*Output PLL_VCOPHSEL_BCLK90_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":85:11:85:31|*Output PLL_VCOPHSEL_MCLK_SEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":86:11:86:21|*Output PLL_LOADPHS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":87:11:87:24|*Output PLL_PHS_ROTATE has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":88:11:88:27|*Output PLL_PHS_DIRECTION has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0_TR\PF_IOD_GENERIC_RX_C0_TR_0\rtl\vlog\core\CoreBclkSclkAlign.v":99:17:99:38|*Output BCLKSCLK_BCLK_VCOPHSEL has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_CLK_TRAINING\PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v":60:23:60:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_CLK_TRAINING\PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v":60:32:60:32|Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v":152:41:152:41|Input RX_N on instance I_IOD_2 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v":196:41:196:41|Input RX_N on instance I_IOD_3 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v":240:41:240:41|Input RX_N on instance I_IOD_1 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_IOD_RX\PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v":295:41:295:41|Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":20:5:20:15|Object pause_reg_0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":20:18:20:28|Object pause_reg_1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_IOD_GENERIC_RX_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":20:31:20:35|Object pause is declared but not assigned. Either assign a value or remove the declaration.
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v":318:12:318:16|Type of parameter INTERFACE_LEVEL on the instance LANE3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v":611:12:611:16|Type of parameter INTERFACE_LEVEL on the instance LANE2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v":905:12:905:16|Type of parameter INTERFACE_LEVEL on the instance LANE1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\PF_XCVR_ERM_C0\I_XCVR\PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v":1201:12:1201:16|Type of parameter INTERFACE_LEVEL on the instance LANE0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":461:16:461:39|Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":158:29:158:37|Removing wire neg_reset, as there is no assignment to it.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":365:4:365:9|Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":349:3:349:8|Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":349:3:349:8|Pruning unused register full_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":349:3:349:8|Pruning unused register re_p_d1. Make sure that there are no unused intermediate registers.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":453:9:453:14|All reachable assignments to genblk7.wack_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":453:9:453:14|All reachable assignments to genblk7.overflow_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":365:4:365:9|All reachable assignments to underflow_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":203:3:203:8|All reachable assignments to wrcnt[8:0] assign 0, register removed by optimization.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":87:27:87:32|Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":93:27:93:33|Removing wire aresetn, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":99:27:99:32|Removing wire empty1, as there is no assignment to it.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":260:3:260:8|Pruning unused register we_p_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":170:3:170:8|Pruning unused register fifo_empty_pulse_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":162:4:162:9|Pruning unused register re_p_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":147:3:147:8|Pruning unused register fifo_empty_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":147:3:147:8|Pruning unused register update_dout_r. Make sure that there are no unused intermediate registers.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":57:26:57:37|*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":58:26:58:37|*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":59:26:59:36|*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":60:26:60:36|*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":150:37:150:46|Removing wire SB_CORRECT, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":151:37:151:45|Removing wire DB_DETECT, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":188:36:188:46|Removing wire pf_MEMRADDR, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":194:36:194:39|Removing wire pf_Q, as there is no assignment to it.
@W: CG184 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":212:36:212:45|Removing wire DVLD_async, as it has the load but no drivers.
@W: CG184 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":214:36:214:44|Removing wire DVLD_sync, as it has the load but no drivers.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":217:36:217:42|Removing wire pf_dvld, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":222:36:222:47|Removing wire A_SB_CORRECT, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":223:36:223:46|Removing wire A_DB_DETECT, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":224:36:224:47|Removing wire B_SB_CORRECT, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":225:36:225:46|Removing wire B_DB_DETECT, as there is no assignment to it.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":226:36:226:44|Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":240:36:240:41|Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":255:8:255:19|Removing wire reset_sync_r, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":256:8:256:19|Removing wire reset_sync_w, as there is no assignment to it.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":150:37:150:46|*Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":151:37:151:45|*Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":965:3:965:8|Pruning unused register RDATA_ext_r1[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":955:3:955:8|Pruning unused register RDATA_ext_r[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register REN_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register REN_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register RE_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register RE_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register re_pulse_d1. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register re_pulse_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":893:3:893:8|Pruning unused register re_pulse_d3. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":881:3:881:8|Pruning unused register RDATA_r2[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":871:3:871:8|Pruning unused register RDATA_r1[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":861:3:861:8|Pruning unused register RDATA_r_pre[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":851:3:851:8|Pruning unused register fwft_Q_r[511:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":379:3:379:8|Pruning unused register DVLD_async_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":379:3:379:8|Pruning unused register DVLD_sync_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":379:3:379:8|Pruning unused register DVLD_scntr_ecc. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":367:3:367:8|Pruning unused register AEMPTY1_r. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":367:3:367:8|Pruning unused register AEMPTY1_r1. Make sure that there are no unused intermediate registers.
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":461:16:461:39|Type of parameter READ_DEPTH on the instance fifo_corefifo_sync_scntr is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":365:4:365:9|Pruning unused register aempty_r_fwft. Make sure that there are no unused intermediate registers.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":349:3:349:8|Pruning unused register dvld_r2. Make sure that there are no unused intermediate registers.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":453:9:453:14|All reachable assignments to genblk7.wack_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":453:9:453:14|All reachable assignments to genblk7.overflow_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":365:4:365:9|All reachable assignments to underflow_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":365:4:365:9|All reachable assignments to dvld_r assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_sync_scntr.v":203:3:203:8|All reachable assignments to wrcnt[3:0] assign 0, register removed by optimization.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_corefifo_fwft.v":87:27:87:32|Object wr_p_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":57:26:57:37|*Output A_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":58:26:58:37|*Output B_SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":59:26:59:36|*Output A_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\axi_lbus_ram_wrapper.v":60:26:60:36|*Output B_DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":226:36:226:44|Object reg_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":240:36:240:41|Object reg_RD is declared but not assigned. Either assign a value or remove the declaration.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":150:37:150:46|*Output SB_CORRECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_axi_fifo.v":151:37:151:45|*Output DB_DETECT has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element bready and merging rready. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awsize[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awprot[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awlock[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awid[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awcache[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element awcache and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal awburst[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arsize[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arsize and merging awsize. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arprot[2:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arprot and merging awprot. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arlock[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arlock and merging awlock. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arid[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arid and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arcache[3:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arcache and merging awid. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL113 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Feedback mux created for signal arburst[1:0]. To avoid the feedback mux, assign values explicitly under all conditions of conditional assignment statements.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arburst and merging awburst. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|Sharing sequential element arburst and merging awburst. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL251 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to arsize[2:1] assign 1, register removed by optimization
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awburst[1] assign 0, register removed by optimization
@W: CL251 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awburst[0] assign 1, register removed by optimization
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awid[3:0] assign 0, register removed by optimization
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awlock[1:0] assign 0, register removed by optimization
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awprot[2:0] assign 0, register removed by optimization
@W: CL251 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awsize[2:1] assign 1, register removed by optimization
@W: CL250 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\ddr_rw_arbiter_lpddr4.v":400:0:400:5|All reachable assignments to awsize[0] assign 0, register removed by optimization
@W: CG1283 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Ignoring localparam ADDR_WIDTH_INT on the instance and using locally defined value
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE0_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE1_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE2_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE3_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE4_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE5_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE6_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE7_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE8_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE9_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE10_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE11_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE12_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE13_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE14_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE15_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE16_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE17_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE18_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE19_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE20_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE21_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE22_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE23_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE24_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE25_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE26_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE27_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE28_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE29_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE30_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE31_START_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE0_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE1_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE2_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE3_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE4_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE5_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE6_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE7_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE8_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE9_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE10_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE11_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE12_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE13_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE14_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE15_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE16_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE17_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE18_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE19_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE20_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE21_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE22_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE23_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE24_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE25_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE26_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE27_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE28_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE29_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE30_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE31_START_ADDR_UPPER on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE0_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE1_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE2_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE3_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE4_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE5_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE6_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE7_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE8_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE9_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE10_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE11_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE12_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE13_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE14_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE15_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE16_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE17_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG168 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\DMA_MASTER\DMA_MASTER.v":4559:0:4559:11|Type of parameter SLAVE18_END_ADDR on the instance DMA_MASTER_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":229:55:229:70|Removing wire currRDataTransID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":230:34:230:46|Removing wire openRTransDec, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":232:55:232:70|Removing wire currWDataTransID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":233:34:233:46|Removing wire openWTransDec, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":235:7:235:14|Removing wire sysReset, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":237:19:237:28|Removing wire dataFifoWr, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":238:46:238:52|Removing wire srcPort, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":239:36:239:43|Removing wire destPort, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":240:34:240:43|Removing wire wrFifoFull, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":242:19:242:30|Removing wire rdDataFifoWr, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":243:46:243:54|Removing wire rdSrcPort, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":244:36:244:45|Removing wire rdDestPort, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":245:34:245:43|Removing wire rdFifoFull, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":250:52:250:60|Removing wire DERR_ARID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":251:44:251:53|Removing wire DERR_ARLEN, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":252:41:252:52|Removing wire DERR_ARVALID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":253:41:253:52|Removing wire DERR_ARREADY, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":255:45:255:52|Removing wire DERR_RID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":256:35:256:44|Removing wire DERR_RDATA, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":257:43:257:52|Removing wire DERR_RRESP, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":258:40:258:49|Removing wire DERR_RLAST, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":259:39:259:48|Removing wire DERR_RUSER, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":260:40:260:50|Removing wire DERR_RVALID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":261:40:261:50|Removing wire DERR_RREADY, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":263:53:263:61|Removing wire DERR_AWID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":264:44:264:53|Removing wire DERR_AWLEN, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":265:41:265:52|Removing wire DERR_AWVALID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":266:41:266:52|Removing wire DERR_AWREADY, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":268:61:268:68|Removing wire DERR_WID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":269:35:269:44|Removing wire DERR_WDATA, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":270:46:270:55|Removing wire DERR_WSTRB, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":271:40:271:49|Removing wire DERR_WLAST, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":272:39:272:48|Removing wire DERR_WUSER, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":273:40:273:50|Removing wire DERR_WVALID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":274:39:274:49|Removing wire DERR_WREADY, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":276:45:276:52|Removing wire DERR_BID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":277:43:277:52|Removing wire DERR_BRESP, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":278:39:278:48|Removing wire DERR_BUSER, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":279:41:279:51|Removing wire DERR_BVALID, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":280:32:280:42|Removing wire DERR_BREADY, as there is no assignment to it.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":318:7:318:7|Object i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v":142:20:142:41|Object WVLID_FIXED_BURST_CTRL is declared but not assigned. Either assign a value or remove the declaration.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v":396:3:396:8|All reachable assignments to cnt_plus_1_eq_0 assign 0, register removed by optimization.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v":627:3:627:8|All reachable assignments to SLAVE_AID[3:0] assign 0, register removed by optimization.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Optimizing register bit ASIZE_pre[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Pruning register bit 2 of ASIZE_pre[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":161:22:161:40|Removing wire brespFifoEmpty_temp, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":165:15:165:25|Removing wire brespFifowe, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":178:12:178:41|Removing wire tot_len_M_to_boundary_conv_pre, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":179:11:179:33|Removing wire to_boundary_conv_M1_pre, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":183:9:183:38|Removing wire tot_len_GT_max_length_comb_pre, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":184:12:184:40|Removing wire tot_len_M_max_length_comb_pre, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":185:11:185:25|Removing wire tot_axi_len_pre, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":192:5:192:22|Removing wire MASTER_AWVALID_reg, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":193:5:193:26|Removing wire from_ctrl_MASTER_READY, as there is no assignment to it.
@W: CG360 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":194:5:194:26|Removing wire to_ctrl_MASTER_AWVALID, as there is no assignment to it.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_writeWidthConv.v":318:7:318:14|Object id_range is declared but not assigned. Either assign a value or remove the declaration.
@W: CL207 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v":627:3:627:8|All reachable assignments to SLAVE_AID[3:0] assign 0, register removed by optimization.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Optimizing register bit ASIZE_pre[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Pruning register bit 2 of ASIZE_pre[2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG133 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_readWidthConv.v":181:7:181:7|Object i is declared but not assigned. Either assign a value or remove the declaration.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":112:2:112:16|*Output MASTER1_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":126:2:126:16|*Output MASTER2_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":140:2:140:16|*Output MASTER3_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":154:2:154:16|*Output MASTER4_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":168:2:168:16|*Output MASTER5_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":182:2:182:16|*Output MASTER6_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":196:2:196:16|*Output MASTER7_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":210:2:210:16|*Output MASTER8_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":224:2:224:16|*Output MASTER9_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":238:2:238:17|*Output MASTER10_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":252:2:252:17|*Output MASTER11_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":266:2:266:17|*Output MASTER12_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":280:2:280:17|*Output MASTER13_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":294:2:294:17|*Output MASTER14_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":308:2:308:17|*Output MASTER15_AWREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":326:2:326:15|*Output MASTER1_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":334:2:334:15|*Output MASTER2_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":342:2:342:15|*Output MASTER3_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":350:2:350:15|*Output MASTER4_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":358:2:358:15|*Output MASTER5_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":366:2:366:15|*Output MASTER6_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":374:2:374:15|*Output MASTER7_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":382:2:382:15|*Output MASTER8_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":390:2:390:15|*Output MASTER9_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":398:2:398:16|*Output MASTER10_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":406:2:406:16|*Output MASTER11_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":414:2:414:16|*Output MASTER12_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":422:2:422:16|*Output MASTER13_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":430:2:430:16|*Output MASTER14_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":438:2:438:16|*Output MASTER15_WREADY has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":447:2:447:12|*Output MASTER1_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":448:2:448:14|*Output MASTER1_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":449:2:449:14|*Output MASTER1_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":450:2:450:15|*Output MASTER1_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":453:2:453:12|*Output MASTER2_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":454:2:454:14|*Output MASTER2_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":455:2:455:14|*Output MASTER2_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":456:2:456:15|*Output MASTER2_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":459:2:459:12|*Output MASTER3_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":460:2:460:14|*Output MASTER3_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":461:2:461:14|*Output MASTER3_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":462:2:462:15|*Output MASTER3_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":465:2:465:12|*Output MASTER4_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":466:2:466:14|*Output MASTER4_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":467:2:467:14|*Output MASTER4_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":468:2:468:15|*Output MASTER4_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":471:2:471:12|*Output MASTER5_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":472:2:472:14|*Output MASTER5_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":473:2:473:14|*Output MASTER5_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":474:2:474:15|*Output MASTER5_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":477:2:477:12|*Output MASTER6_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":478:2:478:14|*Output MASTER6_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":479:2:479:14|*Output MASTER6_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":480:2:480:15|*Output MASTER6_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":483:2:483:12|*Output MASTER7_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":484:2:484:14|*Output MASTER7_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":485:2:485:14|*Output MASTER7_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":486:2:486:15|*Output MASTER7_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":489:2:489:12|*Output MASTER8_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":490:2:490:14|*Output MASTER8_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":491:2:491:14|*Output MASTER8_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":492:2:492:15|*Output MASTER8_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":495:2:495:12|*Output MASTER9_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":496:2:496:14|*Output MASTER9_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":497:2:497:14|*Output MASTER9_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":498:2:498:15|*Output MASTER9_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":501:2:501:13|*Output MASTER10_BID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":502:2:502:15|*Output MASTER10_BRESP has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":503:2:503:15|*Output MASTER10_BUSER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\CoreAxi4Interconnect.v":504:2:504:16|*Output MASTER10_BVALID has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvrd.v":83:41:83:57|Input port bits 39 to 30 of rdCmdFifoReadData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvrd.v":83:41:83:57|Input port bits 22 to 8 of rdCmdFifoReadData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Pruning register bits 5 to 4 of mask_addr_pre[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v":87:32:87:43|Input port bits 31 to 6 of MASTER_AADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_preCalcCmdFifoWrCtrl.v":126:2:126:7|Pruning register bits 5 to 4 of mask_addr_pre[5:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_CmdFifoWriteCtrl.v":87:32:87:43|Input port bits 31 to 6 of MASTER_AADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v":71:41:71:55|Input port bits 39 to 30 of wrCmdFifoRdData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4Convertors\DWC_DownConv_widthConvwr.v":71:41:71:55|Input port bits 10 to 8 of wrCmdFifoRdData[40:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":166:61:166:69|Input port bit 4 of SLAVE_BID[4:0] is unused
@W: CL247 :"D:\Delme\SEV_PFSoC_OpenVX\component\Actel\DirectCore\COREAXI4INTERCONNECT\2.8.103\rtl\vlog\core\Axi4CrossBar\Axi4CrossBar.v":188:63:188:71|Input port bit 4 of SLAVE_RID[4:0] is unused
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Optimizing register bit genblk2.pixel_count[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Optimizing register bit genblk2.pixel_count[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1125:10:1125:15|Pruning register bits 1 to 0 of genblk2.pixel_count[15:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL177 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":6309:2:6309:7|Sharing sequential element pixel_valid and merging line_valid_o. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1986:4:1986:9|Optimizing register bit genblk1.word_counter[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1986:4:1986:9|Optimizing register bit genblk1.word_counter[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\mipicsi2rxdecoderPF\4.4.0\RTL\mipicsi2rxdecoderPF.v":1986:4:1986:9|Pruning register bits 1 to 0 of genblk1.word_counter[16:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CD729 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\HDMI_TX_C0\HDMI_TX_C0.vhd":130:0:130:11|Component declaration has 3 generics but entity declares only 2 generics
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":135:9:135:20|Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":136:9:136:19|Signal s_vsync_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":137:9:137:19|Signal s_hsync_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Signal s_data_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1128:9:1128:9|Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1129:9:1129:9|Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1381:4:1381:5|Removing unused bit 6 of wdata_count_2(6 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1277:4:1277:5|Removing unused bit 6 of rdata_count_2(6 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1228:4:1228:5|Pruning register bit 6 of rptr(6 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":1328:4:1328:5|Pruning register bit 6 of wptr(6 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 0 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 1 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 2 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 3 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 4 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 5 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 6 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 7 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 8 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 9 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 10 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 11 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 12 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 13 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 14 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 15 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 16 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 17 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 18 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 19 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 20 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 21 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 22 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":138:9:138:16|Bit 23 of signal s_data_o is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\HDMI_TX\4.4.0\HDL\HDMI_TX.vhd":51:4:51:11|Signal TREADY_O is floating; a simulation mismatch is possible.
@W: CD729 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\Display_Controller_C0\Display_Controller_C0.vhd":138:0:138:22|Component declaration has 4 generics but entity declares only 3 generics
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":155:7:155:19|Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":156:7:156:18|Signal s_vsync_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":157:7:157:18|Signal s_hsync_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":158:7:158:22|Signal s_frame_end_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD796 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":159:7:159:20|Bit 0 of signal s_trigger_mstr is undriven. Possible simulation mismatch as initial value or default value is ignored. To avoid simulation mismatches, explicitly drive this bit. 
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":160:7:160:15|Signal s_ext_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":161:7:161:20|Signal s_vactive_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":86:4:86:11|Signal TVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":83:1:83:7|Signal TLAST_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":81:4:81:10|Bit 0 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":81:4:81:10|Bit 1 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":81:4:81:10|Bit 2 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":81:4:81:10|Bit 3 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":80:1:80:7|Bit 0 of signal TKEEP_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":80:1:80:7|Bit 1 of signal TKEEP_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":80:1:80:7|Bit 2 of signal TKEEP_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":78:1:78:7|Bit 0 of signal TSTRB_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":78:1:78:7|Bit 1 of signal TSTRB_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":78:1:78:7|Bit 2 of signal TSTRB_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 0 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 1 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 2 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 3 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 4 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 5 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 6 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":76:1:76:7|Bit 7 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":55:1:55:8|Signal TREADY_O is floating; a simulation mismatch is possible.
@W: CD729 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\Image_Enhancement_C0\Image_Enhancement_C0.vhd":214:0:214:21|Component declaration has 5 generics but entity declares only 4 generics
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":338:7:338:11|Signal s_eof is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":339:7:339:18|Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":340:7:340:19|Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":341:7:341:15|Signal s_data_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":342:7:342:17|Signal s_data_i_4k is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":343:7:343:16|Signal s_data_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":344:7:344:19|Signal s_data_4k_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":345:7:345:24|Signal s_r_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":346:7:346:24|Signal s_g_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":347:7:347:24|Signal s_b_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":348:7:348:24|Signal s_c_constant_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":187:1:187:7|Signal TKEEP_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":185:1:185:7|Signal TSTRB_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":183:4:183:11|Signal TVALID_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":180:1:180:7|Bit 0 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":180:1:180:7|Bit 1 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":180:1:180:7|Bit 2 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":180:1:180:7|Bit 3 of signal TUSER_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":178:1:178:7|Signal TLAST_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 0 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 1 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 2 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 3 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 4 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 5 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 6 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 7 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 8 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 9 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 10 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 11 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 12 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 13 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 14 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 15 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 16 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 17 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 18 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 19 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 20 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 21 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 22 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":176:4:176:10|Bit 23 of signal TDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":141:1:141:9|Bit 0 of signal AXI_BID_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":141:1:141:9|Bit 1 of signal AXI_BID_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":139:1:139:11|Signal AXI_RLAST_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":137:1:137:9|Bit 0 of signal AXI_RID_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":137:1:137:9|Bit 1 of signal AXI_RID_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":135:1:135:11|Signal AXI_RUSER_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":131:1:131:11|Signal AXI_BUSER_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":109:1:109:11|Bit 0 of signal AXI_RRESP_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":109:1:109:11|Bit 1 of signal AXI_RRESP_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":105:1:105:12|Signal AXI_RVALID_O is floating; a simulation mismatch is possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 0 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 1 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 2 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 3 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 4 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 5 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 6 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 7 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 8 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 9 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 10 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 11 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 12 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 13 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 14 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 15 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 16 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 17 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 18 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 19 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 20 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 21 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 22 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL252 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":103:1:103:11|Bit 23 of signal AXI_RDATA_O is floating -- simulation mismatch possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":95:1:95:13|Signal AXI_ARREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":87:1:87:12|Signal AXI_BVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":83:1:83:12|Signal AXI_WREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":71:1:71:13|Signal AXI_AWREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Image_Enhancement\4.3.0\Encrypted\Image_Enhancement.vhd":56:1:56:8|Signal TREADY_O is floating; a simulation mismatch is possible.
@W: CD729 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\Gamma_Correction_C0\Gamma_Correction_C0.vhd":128:0:128:20|Component declaration has 4 generics but entity declares only 3 generics
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":182:7:182:18|Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":183:7:183:19|Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":184:7:184:11|Signal s_eof is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":185:7:185:14|Signal s_data_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":186:7:186:14|Signal s_red_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":187:7:187:16|Signal s_green_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":188:7:188:15|Signal s_blue_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":189:7:189:15|Signal s_red_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":190:7:190:17|Signal s_green_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":191:7:191:16|Signal s_blue_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":193:7:193:17|Signal s_data_4p_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":194:7:194:17|Signal s_red_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":195:7:195:19|Signal s_green_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":196:7:196:18|Signal s_blue_4p_in is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":197:7:197:18|Signal s_red_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":198:7:198:20|Signal s_green_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":199:7:199:19|Signal s_blue_4p_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":88:4:88:11|Signal TVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":85:4:85:10|Signal TLAST_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":83:4:83:10|Signal TKEEP_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":81:1:81:7|Signal TSTRB_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Gamma_Correction\4.2.0\Encrypted\Gamma_Correction.vhd":53:1:53:8|Signal TREADY_O is floating; a simulation mismatch is possible.
@W: CD729 :"D:\Delme\SEV_PFSoC_OpenVX\component\work\Bayer_Interpolation_C0\Bayer_Interpolation_C0.vhd":229:0:229:23|Component declaration has 6 generics but entity declares only 5 generics
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":321:9:321:17|Signal s_eof_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":322:9:322:18|Signal s_eof_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":323:9:323:28|Signal s_bayer_format_axi4l is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":324:9:324:18|Signal s_data_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":325:9:325:20|Signal s_dvalid_slv is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":326:9:326:21|Signal s_dvalid_mstr is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":327:9:327:21|Signal s_bayer_red_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":328:9:328:23|Signal s_bayer_green_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":329:9:329:22|Signal s_bayer_blue_o is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":333:9:333:17|Signal s_red_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":334:9:334:19|Signal s_green_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":335:9:335:18|Signal s_blue_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":337:9:337:20|Signal s_data_o_axi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":1410:4:1410:5|Pruning unused bits 12 to 8 of s_b_11(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":1410:4:1410:5|Pruning unused bits 12 to 8 of s_g_11(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":1410:4:1410:5|Pruning unused bits 12 to 8 of s_r_16(12 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":191:4:191:11|Signal TVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":189:4:189:10|Signal TLAST_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":187:4:187:10|Signal TKEEP_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":185:4:185:10|Signal TSTRB_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":146:4:146:14|Signal AXI_RLAST_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":142:4:142:14|Signal AXI_RUSER_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":138:4:138:14|Signal AXI_BUSER_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":112:4:112:15|Signal AXI_RVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":102:4:102:16|Signal AXI_ARREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":94:4:94:15|Signal AXI_BVALID_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":90:4:90:15|Signal AXI_WREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":78:4:78:16|Signal AXI_AWREADY_O is floating; a simulation mismatch is possible.
@W: CL240 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Bayer_Interpolation\4.2.0\RTL\Bayer_Interpolation.vhd":57:4:57:11|Signal TREADY_O is floating; a simulation mismatch is possible.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\apb3_interface.vhd":96:9:96:19|Signal s_signature is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":121:9:121:9|Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":122:9:122:9|Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":374:4:374:5|Removing unused bit 9 of wdata_count_2(9 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":270:4:270:5|Removing unused bit 9 of rdata_count_2(9 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":221:4:221:5|Pruning register bit 9 of rptr(9 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":321:4:321:5|Pruning register bit 9 of wptr(9 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG296 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\synchronizer_circuit.vhd":38:2:38:8|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\synchronizer_circuit.vhd":40:7:40:13|Referenced variable reset_n is not in sensitivity list.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(10) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(11) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(12) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_count_max(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Pruning register bits 15 to 10 of s_count_max(15 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":121:9:121:9|Signal i is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":122:9:122:9|Signal j is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":374:4:374:5|Removing unused bit 12 of wdata_count_2(12 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL265 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":270:4:270:5|Removing unused bit 12 of rdata_count_2(12 downto 0). Either assign all bits or reduce the width of the signal.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":221:4:221:5|Pruning register bit 12 of rptr(12 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\video_fifo.vhd":321:4:321:5|Pruning register bit 12 of wptr(12 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CG296 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd":169:2:169:8|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd":174:48:174:60|Referenced variable frame_index_i is not in sensitivity list.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd":137:4:137:5|Pruning register bit 0 of s_pan_h_dly(11 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd":137:4:137:5|Pruning register bit 0 of s_pan_h(11 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(496) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(497) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(498) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(499) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(500) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(501) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(502) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(503) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(504) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(505) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(506) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(507) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(508) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(509) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(510) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL111 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":169:4:169:5|All reachable assignments to s_data_pack(511) are '0'; removing register. To preserve a constant register, use the syn_preserve attribute.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\data_unpacker_FHD_RX_0.vhd":44:4:44:14|Input port bits 4 to 0 of horz_resl_i(15 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_read_controller_FHD_HDMI_RX.vhd":55:4:55:10|Input port bit 0 of h_pan_i(11 downto 0) is unused 
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(0) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(1) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(2) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(3) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(4) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(5) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(6) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(7) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Optimizing register bit s_line_counter(8) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\DDR_write_controller_lpddr4.vhd":187:4:187:5|Pruning register bits 8 to 0 of s_line_counter(22 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\apb3_interface.vhd":42:4:42:10|Input port bits 31 to 12 of paddr_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\apb3_interface.vhd":43:4:43:11|Input port bits 31 to 20 of pwdata_i(31 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\intensity_average.vhd":29:4:29:6|Input port bit 0 of r_i(7 downto 0) is unused 
@W: CL246 :"D:\Delme\SEV_PFSoC_OpenVX\hdl\intensity_average.vhd":31:4:31:6|Input port bits 1 to 0 of b_i(7 downto 0) are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":509:2:509:3|Optimizing register bit s_h_counter(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":637:2:637:3|Optimizing register bit s_h_counterx(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":637:2:637:3|Pruning register bit 15 of s_h_counterx(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Pruning register bit 15 of s_v_counter(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":509:2:509:3|Pruning register bit 15 of s_h_counter(15 downto 0). If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":637:2:637:3|Pruning register bits 14 to 11 of s_h_counterx(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":509:2:509:3|Pruning register bits 14 to 11 of s_h_counter(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(10) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(11) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(12) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(13) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Optimizing register bit s_v_counter(14) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":549:2:549:3|Pruning register bits 14 to 10 of s_v_counter(14 downto 0). If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":692:2:692:3|Optimizing register bit s_v_counterx(15) to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"D:\Delme\SEV_PFSoC_OpenVX\component\Microsemi\SolutionCore\Display_Controller\4.5.0\RTL\Display_Controller.vhd":692:2:692:3|Pruning unused register s_v_counterx(15). Make sure that there are no unused intermediate registers.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_5s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances: slvdwc. Apply syn_hier to module using name v:caxi4interconnect_SlvDataWidthConverter_Z23_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances: slvProtConv. Apply syn_hier to module using name v:caxi4interconnect_SlvProtocolConverter_Z24_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\slaveconvertor.v":24:7:24:38|syn_hier attribute not currently supported on instances: slvCDC. Apply syn_hier to module using name v:caxi4interconnect_SlvClockDomainCrossing_Z25_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances: rgsl. Apply syn_hier to module using name v:caxi4interconnect_RegisterSlice_1_1_1_1_1_4s_32s_64s_0s_1s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances: genblk2\.mstrProtConv. Apply syn_hier to module using name v:caxi4interconnect_MstrProtocolConverter_4s_0s_32s_512s_0_1s_4s.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances: mstrDWC. Apply syn_hier to module using name v:caxi4interconnect_MstrDataWidthConv_Z19_layer0.
@W: BN108 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|syn_hier attribute not currently supported on instances: mstrCDC. Apply syn_hier to module using name v:caxi4interconnect_MstrClockDomainCrossing_Z21_layer0.

