#--  Synopsys, Inc.
#--  Version S-2021.09M-SP1
#--  Project file D:\Delme\SEV_PFSoC_OpenVX\synthesis\run_options.txt
#--  Written on Mon Nov 21 15:24:40 2022


#project files
add_file -verilog "../component/polarfire_syn_comps.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C3/CORERESET_PF_C3_0/core/corereset_pf.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C3/CORERESET_PF_C3.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C4/CORERESET_PF_C4_0/core/corereset_pf.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C4/CORERESET_PF_C4.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/INIT_MONITOR/INIT_MONITOR_0/INIT_MONITOR_INIT_MONITOR_0_PFSOC_INIT_MONITOR.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/INIT_MONITOR/INIT_MONITOR.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C0/PF_CCC_C0_0/PF_CCC_C0_PF_CCC_C0_0_PF_CCC.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C0/PF_CCC_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C1/PF_CCC_C1_0/PF_CCC_C1_PF_CCC_C1_0_PF_CCC.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C1/PF_CCC_C1.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CLK_DIV_C0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_PF_CLK_DIV_C0_0_PF_CLK_DIV.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CLK_DIV_C0/PF_CLK_DIV_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_OSC_C0/PF_OSC_C0_0/PF_OSC_C0_PF_OSC_C0_0_PF_OSC.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_OSC_C0/PF_OSC_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_TX_PLL_C0/PF_TX_PLL_C0_0/PF_TX_PLL_C0_PF_TX_PLL_C0_0_PF_TX_PLL.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_TX_PLL_C0/PF_TX_PLL_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_XCVR_REF_CLK_C0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_PF_XCVR_REF_CLK_C0_0_PF_XCVR_REF_CLK.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_XCVR_REF_CLK_C0/PF_XCVR_REF_CLK_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CLOCKS_AND_RESETS/CLOCKS_AND_RESETS.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C0/CORERESET_PF_C0_0/core/corereset_pf.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C0/CORERESET_PF_C0.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/DDR_read_controller_FHD_HDMI_RX.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/register_config.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/data_unpacker_FHD_RX_0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/ram2port.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/video_fifo.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/DDR_Read_LPDDR4/DDR_Read_LPDDR4.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/DDR_write_controller_lpddr4.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/data_packer_lpddr4.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/synchronizer_circuit.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/DDR_Write_LPDDR4/DDR_Write_LPDDR4.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/Display_Controller/4.5.0/RTL/Display_Controller.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/Display_Controller_C0/Display_Controller_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/HDMI_TX/4.4.0/HDL/HDMI_TX.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/HDMI_TX_C0/HDMI_TX_C0.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C1/CORERESET_PF_C1_0/core/corereset_pf.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C1/CORERESET_PF_C1.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C0/CORERXIODBITALIGN_C0_0/rtl/vlog/core/CoreRxIODBitAlign.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C0/CORERXIODBITALIGN_C0_0/rtl/vlog/core/CoreRxIODBitAlign_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C0/CORERXIODBITALIGN_C0.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C1/CORERXIODBITALIGN_C1_0/rtl/vlog/core/CoreRxIODBitAlign.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C1/CORERXIODBITALIGN_C1_0/rtl/vlog/core/CoreRxIODBitAlign_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C1/CORERXIODBITALIGN_C1.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/core/CoreRxIODBitAlign.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/core/CoreRxIODBitAlign_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C3/CORERXIODBITALIGN_C3_0/rtl/vlog/core/CoreRxIODBitAlign.v"
add_file -verilog -lib CORERXIODBITALIGN_LIB "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C3/CORERXIODBITALIGN_C3_0/rtl/vlog/core/CoreRxIODBitAlign_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C3/CORERXIODBITALIGN_C3.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_CLK_DIV_FIFO/PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_CLK_DIV_RXCLK/PF_IOD_GENERIC_RX_C0_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_IOD_CLK_TRAINING/PF_IOD_GENERIC_RX_C0_PF_IOD_CLK_TRAINING_PF_IOD.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_IOD_RX/PF_IOD_GENERIC_RX_C0_PF_IOD_RX_PF_IOD.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_LANECTRL_0/PF_IOD_GENERIC_RX_C0_PF_LANECTRL_0_PF_LANECTRL.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREBCLKSCLKALIGN/2.0.111/rtl/vlog/core/PLL_BclkSclkAlign.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREBCLKSCLKALIGN/2.0.111/rtl/vlog/core/ICB_BclkSclkAlign.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0_TR/PF_IOD_GENERIC_RX_C0_TR_0/rtl/vlog/core/CoreBclkSclkAlign.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0_TR/PF_IOD_GENERIC_RX_C0_TR.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_IOD_GENERIC_RX_C0/PF_IOD_GENERIC_RX_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CAM_IOD_TIP_TOP/CAM_IOD_TIP_TOP.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C2/CORERESET_PF_C2_0/core/corereset_pf.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERESET_PF_C2/CORERESET_PF_C2.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C2/PF_CCC_C2_0/PF_CCC_C2_PF_CCC_C2_0_PF_CCC.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_CCC_C2/PF_CCC_C2.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/mipicsi2rxdecoderPF/4.4.0/RTL/mipicsi2rxdecoderPF.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/mipicsi2rxdecoderPF_C0/mipicsi2rxdecoderPF_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/IMX334_IF_TOP/IMX334_IF_TOP.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_XCVR_ERM_C0/I_XCVR/PF_XCVR_ERM_C0_I_XCVR_PF_XCVR.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/PF_XCVR_ERM_C0/PF_XCVR_ERM_C0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_NstagesSync.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_grayToBinConv.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_async.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_resetSync.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_sync.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_fwft.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_corefifo_sync_scntr.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_LSRAM_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/axi_lbus_ram_wrapper.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/video_axi_fifo.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/hdl/ddr_rw_arbiter_lpddr4.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/read_demux.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/read_mux.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/request_scheduler.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/read_top/read_top.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/write_demux.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/write_mux.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/write_top/write_top.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/Video_arbiter_top_LPDDR4/Video_arbiter_top_LPDDR4.v"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/YCbCrtoRGB/4.4.0/Encrypted/YCbCrtoRGB.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/YCbCrtoRGB_C0/YCbCrtoRGB_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/Bayer_Interpolation/4.2.0/RTL/Bayer_Interpolation.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/Bayer_Interpolation_C0/Bayer_Interpolation_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/Gamma_Correction/4.2.0/Encrypted/Gamma_Correction.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/Gamma_Correction_C0/Gamma_Correction_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/Image_Enhancement/4.3.0/Encrypted/Image_Enhancement.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/Image_Enhancement_C0/Image_Enhancement_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/Microsemi/SolutionCore/RGBtoYCbCr/4.4.0/Encrypted/RGBtoYCbCr.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/component/work/RGBtoYCbCr_C0/RGBtoYCbCr_C0.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/apb3_interface.vhd"
add_file -vhdl -lib work "D:/Delme/SEV_PFSoC_OpenVX/hdl/intensity_average.vhd"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/video_processing/video_processing.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/DDR4_RD_WR/DDR4_RD_WR.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/ResetSycnc.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/MasterAddressDecoder.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/DependenceChecker.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/BitScan0.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/TransactionController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/MasterControl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/RoundRobinArb.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/TargetMuxController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/AddressController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/Revision.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/DERR_Slave.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/DualPort_FF_SyncWr_SyncRd.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/DualPort_Ram_SyncWr_SyncRd.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/RdFifoDualPort.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/ReadDataMux.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/RequestQual.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/ReadDataController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/RDataController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/SlaveDataMuxController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/RespController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/FifoDualPort.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/WriteDataMux.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/WDataController.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4CrossBar/Axi4CrossBar.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/AHBL_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/AXI4_Read_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/AXI4_Write_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/AHB_SM.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/MstrAHBtoAXI4Converter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/Bin2Gray.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/CDC_grayCodeCounter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/CDC_rdCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/CDC_wrCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/RAM_BLOCK.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/CDC_FIFO.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/MstrClockDomainCrossing.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_AChannel.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_brespCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/FIFO_CTRL.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/FIFO.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_BChannel.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_RChannel_SlvRid_Arb.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_RChan_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/Hold_Reg_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_preCalcRChan_Ctrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/FIFO_downsizing.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_RChannel.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_WChan_Hold_Reg.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_WChan_ReadDataFifoCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_Wchan_WriteDataFifoCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/FIFO_upsizing.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_WChannel.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_UpConv_preCalcAChannel.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/UpConverter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_Hold_Reg_Rd.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_widthConvrd.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/byte2bit.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_CmdFifoWriteCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_preCalcCmdFifoWrCtrl.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_readWidthConv.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_Hold_Reg_Wr.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_widthConvwr.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DWC_DownConv_writeWidthConv.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/DownConverter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/MstrDataWidthConv.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/MstrProtocolConverter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/RegSliceFull.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/RegisterSlice.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/MasterConvertor.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvClockDomainCrossing.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvDataWidthConverter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvAxi4ProtConvRead.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvAxi4ProtConvWrite.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvAxi4ProtocolConv.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvAxi4ProtConvAXI4ID.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlvProtocolConverter.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/Axi4Convertors/SlaveConvertor.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/Actel/DirectCore/COREAXI4INTERCONNECT/2.8.103/rtl/vlog/core/CoreAxi4Interconnect.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/DMA_MASTER/DMA_MASTER.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/FIC_BRIDGE/FIC_BRIDGE.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/MSS_SEV/MSS_BYP_NOBYP_BYP_BYP_BYP_syn_comps.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/MSS_SEV/MSS_SEV.v"
add_file -verilog "D:/Delme/SEV_PFSoC_OpenVX/component/work/SEV_PFSoC_OpenVX/SEV_PFSoC_OpenVX.v"
add_file -fpga_constraint "D:/Delme/SEV_PFSoC_OpenVX/designer/SEV_PFSoC_OpenVX/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFireSoC
set_option -part MPFS250T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "SEV_PFSoC_OpenVX"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -resolve_multiple_driver 1
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_structural_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66

# Microchip PolarFireSoC
set_option -automatic_compile_point 1
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -report_preserve_cdc 1
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0
set_option -pack_uram_addr_reg 1

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

# Compiler Options
set_option -vhdl2008 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./SEV_PFSoC_OpenVX.vm"
impl -active "synthesis"
