@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1677:7:1677:20|Found compile point of type hard on View view:work.embsync_detect_Z1_layer0(verilog) 
@N: MF105 |Performing bottom-up mapping of Compile point view:work.embsync_detect_Z1_layer0(verilog) 
@N: MF106 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1677:7:1677:20|Mapping Compile point view:work.embsync_detect_Z1_layer0(verilog) because 
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_3 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_3 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_4 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_4 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_5 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_5 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_6 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_6 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_7 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_7 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1709:27:1709:35|Tristate driver L7_DATA_O_8 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L7_DATA_O_8 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1708:27:1708:35|Tristate driver L6_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L6_DATA_O_1 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1708:27:1708:35|Tristate driver L6_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) on net L6_DATA_O_2 (in view: work.embsync_detect_Z1_layer0(verilog)) has its enable tied to GND.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1986:4:1986:9|There are no possible illegal states for state machine genblk1\.state_enb[3:0] (in view: work.embsync_detect_Z1_layer0(verilog)); safe FSM implementation is not required.
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1986:4:1986:9|Found counter in view:work.embsync_detect_Z1_layer0(verilog) instance genblk1\.word_counter[16:2] 
@N: MT615 |Found clock CAM1_RX_CLK_P with period 4.00ns 
@N: MT615 |Found clock DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV with period 16.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
