
#####  START OF RAM REPORT FOR COMPILE POINT: caxi4interconnect_MasterConvertor_Z22_layer0  #####

#####  LSRAM REPORT  #####

INSTANTIATED     RTL_INSTANCE     PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE     DEPTH_X_WIDTH(A/B)     LOW-POWER_MODE     ECC     A_DOUT_PIPE_REG(EN/ARST/SRST)     B_DOUT_PIPE_REG(EN/ARST/SRST)     WRITE_MODE(A/B)     COMMENTS
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
==============================================================================================================================================================================================================================================

#####  URAM REPORT  #####

INSTANTIATED     RTL_INSTANCE                                                                                                                                                                    PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE                                                                                                                                                                    DEPTH_X_WIDTH     LOW-POWER_MODE     ECC     R_ADDR_REG(EN/ARST/SRST)     R_DATA_PIPE_REG(EN/ARST/SRST)     COMMENTS                                                         
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO               FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifo.genblk1\[0\]\.ram.mem[40:0]                RAM                DEFAULT            FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifo.genblk1\[0\]\.ram.mem_mem_0_0                 64X12             0                  0       0(0/0/0)                     0(0/0/0)                          RAM instance meets the required threshold for mapping using URAM.
                                                                                                                                                                                                                                       FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifo.genblk1\[0\]\.ram.mem_mem_0_1                 64X12             0                  0       0(0/0/0)                     0(0/0/0)                                                                                           
                                                                                                                                                                                                                                       FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifo.genblk1\[0\]\.ram.mem_mem_0_2                 64X12             0                  0       0(0/0/0)                     0(0/0/0)                                                                                           
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
NO               FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.genblk1\.BrespCmdFifo.genblk1\[0\]\.ram.mem[4:0]     RAM                DEFAULT            FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop\[0\]\.mstrconv.mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.genblk1\.BrespCmdFifo.genblk1\[0\]\.ram.mem_mem_0_0     64X12             0                  0       0(0/0/0)                     0(0/0/0)                          RAM instance meets the required threshold for mapping using URAM.
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================

#####  REG/LOGIC REPORT  #####

RTL_INSTANCE     PRIMITIVE_TYPE     USER_ATTRIBUTE     COMMENTS
---------------------------------------------------------------
===============================================================

#####  END OF RAM REPORT FOR COMPILE POINT: caxi4interconnect_MasterConvertor_Z22_layer0  #####

