@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_readwidthconv.v":20:7:20:50|Found compile point of type hard on View view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|Found compile point of type hard on View view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) 
@N: MF105 |Performing bottom-up mapping of Compile point view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) 
@N: MF106 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|Mapping Compile point view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) because 
@N: MO225 :"d:\delme\sev_pfsoc_openvx\hdl\ddr_rw_arbiter_lpddr4.v":303:0:303:5|There are no possible illegal states for state machine DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.SEV_PFSoC_OpenVX(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)); safe FSM implementation is not required.
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":428:3:428:8|Found counter in view:work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog) instance sizeCnt_reg[5:0] 
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":884:3:884:8|Removing sequential instance slave_wrdone (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: MF179 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":937:24:937:51|Found 9 by 9 bit equality operator ('==') cnt_match (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog))
@N: MF179 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":938:45:938:73|Found 9 by 9 bit equality operator ('==') un4_cnt_match_next (in view: work.caxi4interconnect_DWC_DownConv_widthConvwr_512s_64s_1s_41s_64s_8s_4s(verilog))
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance wrCmdFifoWriteCtrl.SizeMax_reg[3] (in view: work.caxi4interconnect_DWC_DownConv_writeWidthConv_Z20_layer0(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[34] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.CmdFifoWrData[29] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.wrCmdFifoWriteCtrl.fixed_flag (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) because it does not drive other instances.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Replicating instance rgsl.genblk4\.wrs.currState[0] (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 11 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":952:26:952:130|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY_2 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 515 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":396:3:396:8|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WVALID (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 8 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":396:3:396:8|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.SLAVE_WLAST (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.SEV_PFSoC_OpenVX(verilog)) with 514 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":952:26:952:130|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY_2 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":396:3:396:8|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.cnt_eq_0 (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 11 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep2 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep1 (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.SEV_PFSoC_OpenVX(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance DDR4_RD_WR_inst_0.Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_fast (in view: work.SEV_PFSoC_OpenVX(verilog)) with 127 loads 3 times to improve timing.
@N: MT615 |Found clock REF_CLK_PAD_P with period 6.73ns 
@N: MT615 |Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 with period 20.00ns 
@N: MT615 |Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 with period 5.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
