@W: BN114 :|Removing instance CP_fanout_cell_work_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s_verilog_inst (in view: work.SEV_PFSoC_OpenVX(verilog)) because it does not drive other instances.
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[2] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[1] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":620:3:620:8|Register bit genblk1\.widthConvrd.fixed_burst_sizecnt[0] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[4] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[3] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Register bit DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[5] (in view view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeMax_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.length_comb_pre[8] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.ASIZE_pre_1[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.sizeCnt_comb_pre[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX107 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\ram_block.v":65:7:65:12|RAM genblk1\[0\]\.ram.mem[23:0] (in view: work.caxi4interconnect_FIFO_64s_41s_41s_63s_128s_64s_6s_128s_63s_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.mask_addr_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SLAVE_ABURST[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[12] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[4] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.sizeCnt_reg[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.SizeMax_reg[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[1] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.ASIZE_reg[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[39] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[38] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[37] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[6] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[2] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[3] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[10] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[11] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.rdCmdFifoWriteCtrl.CmdFifoWrData[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[11] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it is equivalent to instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[12] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it is equivalent to instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)). To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[5] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.genblk1.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[9] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[0] because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.MstConvertor_loop[0].mstrconv.mstrDWC.genblk1.DownConverter_inst.readWidthConv.DWC_DownConv_preCalcCmdFifoWrCtrl_inst.MASTER_AADDR_mux_pre[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":18:0:18:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":19:0:19:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":20:0:20:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":21:0:21:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":22:0:22:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.reset_dly_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":23:0:23:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.rx_trng_done }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":24:0:24:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":25:0:25:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":26:0:26:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":27:0:27:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":28:0:28:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":29:0:29:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":30:0:30:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.reset_dly_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":31:0:31:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.rx_trng_done }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":32:0:32:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":33:0:33:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":34:0:34:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":35:0:35:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":36:0:36:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":37:0:37:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":38:0:38:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.reset_dly_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":39:0:39:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.rx_trng_done }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":40:0:40:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":41:0:41:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":42:0:42:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":43:0:43:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.mv_up_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":44:0:44:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":45:0:45:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.mv_dn_fg }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":46:0:46:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.reset_dly_fg }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":47:0:47:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.rx_trng_done }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":48:0:48:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":49:0:49:0|Timing constraint (to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.timeout_cnt[*] }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":50:0:50:0|Timing constraint (to [get_pins { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL*.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the '-to' objects specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":51:0:51:0|Timing constraint (through [get_nets { FIC_BRIDGE_0.DMA_MASTER_0.ARESETN* }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":52:0:52:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":54:0:54:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":56:0:56:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":58:0:58:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":60:0:60:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":62:0:62:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":64:0:64:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":66:0:66:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":68:0:68:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":70:0:70:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":72:0:72:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":74:0:74:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":76:0:76:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":78:0:78:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":80:0:80:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":82:0:82:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":84:0:84:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":86:0:86:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":88:0:88:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_late_diff[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":90:0:90:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_start[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":92:0:92:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_nxt[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":94:0:94:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":96:0:96:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":98:0:98:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":100:0:100:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":102:0:102:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":104:0:104:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":106:0:106:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":108:0:108:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":110:0:110:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":112:0:112:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":114:0:114:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":116:0:116:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":118:0:118:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":120:0:120:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":122:0:122:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":124:0:124:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":126:0:126:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":128:0:128:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":130:0:130:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":132:0:132:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":134:0:134:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":136:0:136:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":138:0:138:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":140:0:140:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":142:0:142:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":144:0:144:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":146:0:146:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":148:0:148:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_late_diff[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":150:0:150:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_start[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":152:0:152:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_nxt[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":154:0:154:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":156:0:156:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":158:0:158:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":160:0:160:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":162:0:162:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":164:0:164:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":166:0:166:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":168:0:168:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":170:0:170:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":172:0:172:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":174:0:174:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":176:0:176:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":178:0:178:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":180:0:180:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":182:0:182:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":184:0:184:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":186:0:186:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":188:0:188:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":190:0:190:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":192:0:192:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":194:0:194:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":196:0:196:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":198:0:198:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":200:0:200:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":202:0:202:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":204:0:204:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":206:0:206:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":208:0:208:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_late_diff[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":210:0:210:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_start[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":212:0:212:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_nxt[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":214:0:214:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":216:0:216:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":218:0:218:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":220:0:220:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":222:0:222:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":224:0:224:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":226:0:226:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":228:0:228:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":230:0:230:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":232:0:232:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":234:0:234:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":236:0:236:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":238:0:238:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":240:0:240:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":242:0:242:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":244:0:244:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":246:0:246:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":248:0:248:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":250:0:250:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":252:0:252:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_cur_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":254:0:254:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_last_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":256:0:256:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":258:0:258:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":260:0:260:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":262:0:262:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end1[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":264:0:264:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_st2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":266:0:266:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.no_early_no_late_val_end2[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":268:0:268:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_late_diff[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":270:0:270:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_start[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":272:0:272:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.noearly_nolate_diff_nxt[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":274:0:274:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":276:0:276:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":278:0:278:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":280:0:280:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":282:0:282:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.bitalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":284:0:284:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":286:0:286:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":288:0:288:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":290:0:290:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.*.u_CoreRxIODBitAlign.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":292:0:292:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":294:0:294:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":296:0:296:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":298:0:298:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":300:0:300:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":302:0:302:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":304:0:304:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_not_found_lsb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":306:0:306:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_not_found_msb_d }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":308:0:308:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_init_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":310:0:310:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_nxt_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":312:0:312:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_start_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":314:0:314:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_end_set }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":316:0:316:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_init_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":318:0:318:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_nxt_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":320:0:320:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_start_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":322:0:322:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_end_val[*] }]) (multi path 3) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":324:0:324:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":326:0:326:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":328:0:328:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":330:0:330:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":332:0:332:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":334:0:334:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":336:0:336:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_flags_lsb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":338:0:338:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.late_flags_msb[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":340:0:340:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_init_val[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":342:0:342:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_nxt_val[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":344:0:344:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_start_val[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":346:0:346:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_end_val[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":348:0:348:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_init_set }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":350:0:350:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_nxt_set }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":352:0:352:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_start_set }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":354:0:354:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.early_late_end_set }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":356:0:356:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":358:0:358:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":360:0:360:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.cnt[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":362:0:362:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.tapcnt_offset[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":364:0:364:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.tapcnt_final[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":366:0:366:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.wait_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":368:0:368:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.tap_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":370:0:370:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.emflag_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":372:0:372:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.timeout_cnt[*] }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":374:0:374:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.RX_CLK_ALIGN_MOVE }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":376:0:376:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.RX_CLK_ALIGN_LOAD }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":378:0:378:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.RX_RESET_LANE }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":380:0:380:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.RX_CLK_ALIGN_CLR_FLGS }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":382:0:382:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.rx_trng_done }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":384:0:384:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.calc_done }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":386:0:386:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.rx_err }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
@W: MT446 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":388:0:388:0|Timing constraint (from [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clkalign_curr_state[*] }] to [get_cells { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.COREBCLKSCLKALIGN_0.*.genblk1.U_ICB_BCLKSCLKALIGN.clk_align_done }]) (multi path 2) was not applied to the design because none of the '-from' objects specified by the constraint exist in the design 
