@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_readwidthconv.v":20:7:20:50|Found compile point of type hard on View view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) 
@N: MF105 |Performing bottom-up mapping of Compile point view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) 
@N: MF106 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_readwidthconv.v":20:7:20:50|Mapping Compile point view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) because 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":408:3:408:8|Found counter in view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance genblk1\.widthConvrd.sizeCnt_reg[5:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\fifo_ctrl.v":98:0:98:5|Found counter in view:work.caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance rdptr[5:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\fifo_ctrl.v":98:0:98:5|Found counter in view:work.caxi4interconnect_FIFO_CTRL_64s_63s_128s_6s_64s_0s_caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) instance wrptr[5:0] 
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance rdCmdFifoWriteCtrl.SizeMax_reg[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance rdCmdFifoWriteCtrl.CmdFifoWrData[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance rdCmdFifoWriteCtrl.CmdFifoWrData[29] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Removing sequential instance rdCmdFifoWriteCtrl.fixed_flag (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Removing sequential instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[7] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: BN362 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_precalccmdfifowrctrl.v":126:2:126:7|Removing sequential instance DWC_DownConv_preCalcCmdFifoWrCtrl_inst.tot_len_pre[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) because it does not drive other instances.
@N: FX271 :|Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_4_0_a3_xx_mm[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 45 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":426:3:426:8|Replicating instance genblk1\.widthConvrd.cnt_EQ_zero (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 26 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[2] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 8 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[6] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[5] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[4] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[8] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 7 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.mask_slvSize[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 14 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[10] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[7] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[9] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[12] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.len_latched[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":582:34:582:62|Replicating instance genblk1\.widthConvrd.m3 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 46 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.SLAVE_ALEN[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 8 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 24 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_cmdfifowritectrl.v":522:3:522:8|Replicating instance rdCmdFifoWriteCtrl.SLAVE_ALEN[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 6 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":569:25:569:73|Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_2_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 138 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":569:25:569:73|Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_3_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 136 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":408:3:408:8|Replicating instance genblk1\.widthConvrd.current_addr_reg[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.DWC_DownConv_hold_data_out[23] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 5 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[2] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 18 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_hold_reg_rd.v":80:2:80:7|Replicating instance genblk1\.caxi4interconnect_DWC_DownConv_Hold_Reg_Rd.slaveSize_one_hot_hold[1] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 17 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":569:25:569:73|Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 146 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":569:25:569:73|Replicating instance genblk1\.widthConvrd.un1_mask_slvSize_1_0_a3[0] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 62 loads 3 times to improve timing.
@N: FX271 :|Replicating instance rdCmdFifoWriteCtrl.m29_0_0 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 42 loads 2 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":581:34:581:62|Replicating instance genblk1\.widthConvrd.m32_4_03_2_0 (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 69 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvrd.v":605:30:605:98|Replicating instance genblk1\.widthConvrd.MASTER_RDATA_next_3_i_o2_1[3] (in view: work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog)) with 40 loads 3 times to improve timing.
@N: MT615 |Found clock REF_CLK_PAD_P with period 6.73ns 
@N: MT615 |Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 with period 20.00ns 
@N: MT615 |Found clock CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 with period 5.00ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
