
#####  START OF DSP REPORT FOR COMPILE POINT: embsync_detect_Z1_layer0  #####

SNo     Instantiated     Instance_Name     User_Attribute     MACC_Structure     MACC_Name     Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: embsync_detect_Z1_layer0  #####


#####  START OF DSP REPORT FOR COMPILE POINT: caxi4interconnect_MasterConvertor_Z22_layer0  #####

SNo     Instantiated     Instance_Name     User_Attribute     MACC_Structure     MACC_Name     Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: caxi4interconnect_MasterConvertor_Z22_layer0  #####


#####  START OF DSP REPORT FOR COMPILE POINT: caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s  #####

SNo     Instantiated     Instance_Name     User_Attribute     MACC_Structure     MACC_Name     Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s  #####


#####  START OF DSP REPORT FOR COMPILE POINT: IMX334_IF_TOP  #####

SNo     Instantiated     Instance_Name     User_Attribute     MACC_Structure     MACC_Name     Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: IMX334_IF_TOP  #####


#####  START OF DSP REPORT FOR COMPILE POINT: SEV_PFSoC_OpenVX  #####

SNo     Instantiated     Instance_Name     User_Attribute     MACC_Structure     MACC_Name     Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
=================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: SEV_PFSoC_OpenVX  #####


#####  START OF DSP REPORT FOR COMPILE POINT: DDR4_RD_WR  #####

SNo     Instantiated     Instance_Name                                                                                                                                                                 User_Attribute     MACC_Structure     MACC_Name                                                                                                                                                               Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1       NO               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.s_b_d2_1[25:0]                                                              Default            MultSub            DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cb_i_1_muladd_0[27:3]                                             MACC_PA            0        1(1/1/0)                1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
2       NO               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cr_i[27:5]                                                              Default            MultAdd            DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cr_i_muladd_0[27:5]                                               MACC_PA            0        0(0/0/0)                1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
        NO               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cb_i[27:6]                                                              Default            MultAdd            DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cb_i_muladd_0[27:6]                                               MACC_PA            0        1(1/1/0)                1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
3       NO               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cr_i_1[27:4]                                                            Default            Mult               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_cr_i_1_mulonly_0[27:4]                                            MACC_PA            0        0(0/0/0)                1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
4       NO               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_y_i[27:5]                                                               Default            Mult               DDR4_RD_WR_inst_0.YCbCrtoRGB_C0_0.YCbCrtoRGB_C0_0.Y2R_Native422_Format\.YCbCr422toRGB_Native_INST.un1_y_i_mulonly_0[27:5]                                               MACC_PA            0        1(1/1/0)                1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
5       NO               DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un7_s_term1_b\.un7_s_term1_b[44:24]     Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un1_b_const_i_muladd_0[35:18]     MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
6       NO               DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un7_s_term1_g\.un7_s_term1_g[44:24]     Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un1_g_const_i_muladd_0[35:18]     MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
7       NO               DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un9_s_term1_r\.un9_s_term1_r[44:24]     Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.Image_Enhancement_C0_0.Image_Enhancement_C0_0.IE_1p_Native_FORMAT\.Image_Enhancement_Native_INST.un1_r_const_i_muladd_0[35:18]     MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
8       NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i[26:3]                                        Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i_muladd_0[23:0]                         MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
        NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i[26:6]                                         Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i_muladd_0[20:0]                          MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
9       NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i_1[26:4]                                      Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i_1_muladd_0[26:4]                       MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
        NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i_1[26:6]                                       Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i_1_muladd_0[20:0]                        MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
10      NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i_2[26:4]                                      Default            MultAdd            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_green_i_2_muladd_0[22:0]                       MACC_PA            0        0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
        NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i_2[26:4]                                       Default            MultSub            DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_blue_i_2_muladd_0[22:0]                        MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
11      NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i[26:4]                                          Default            Mult               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i_mulonly_0[26:4]                          MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
12      NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i_1[26:8]                                        Default            Mult               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i_1_mulonly_0[22:0]                        MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
13      NO               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i_2[26:6]                                        Default            Mult               DDR4_RD_WR_inst_0.video_processing_0.RGBtoYCbCr_C0_0.RGBtoYCbCr_C0_0.R2Y422_Native_Format\.RGBtoYCbCr422_Native_INST.un1_red_i_2_mulonly_0[21:0]                        MACC_PA            0        1(1/1/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                0(0/0/0)                  0(0/0/0)            
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT FOR COMPILE POINT: DDR4_RD_WR  #####

