@W: BN114 :|Removing instance CP_fanout_cell_DDR4_RD_WR_verilog_inst (in view: work.DDR4_RD_WR_rtl_ilm(verilog)) because it does not drive other instances.
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk5.brs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.mReady because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.currState[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk4.wrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk2.arrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk1.awrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Removing instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.sValid because it is equivalent to instance FIC_BRIDGE_0.DMA_MASTER_0.DMA_MASTER_0.SlvConvertor_loop[0].slvcnv.rgsl.genblk3.rrs.currState[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
