@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1677:7:1677:20|Found compile point of type hard on View view:work.embsync_detect_Z1_layer0(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\work\imx334_if_top\imx334_if_top.v":9:7:9:19|Found compile point of type hard on View view:work.IMX334_IF_TOP(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\work\ddr4_rd_wr\ddr4_rd_wr.v":9:7:9:16|Found compile point of type hard on View view:work.DDR4_RD_WR(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_readwidthconv.v":20:7:20:50|Found compile point of type hard on View view:work.caxi4interconnect_DWC_DownConv_readWidthConv_64s_64s_41s_512s_32s_4s_1s_0_1s(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\masterconvertor.v":23:7:23:39|Found compile point of type hard on View view:work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog) 
@N: MF105 |Performing bottom-up mapping of Top level view:work.SEV_PFSoC_OpenVX(verilog) 
@N: MF106 :"d:\delme\sev_pfsoc_openvx\component\work\sev_pfsoc_openvx\sev_pfsoc_openvx.v":9:7:9:22|Mapping Top level view:work.SEV_PFSoC_OpenVX(verilog) because 
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2737:2:2737:15|Tristate driver SLAVE31_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE31_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2729:2:2729:15|Tristate driver SLAVE30_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE30_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2721:2:2721:15|Tristate driver SLAVE29_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE29_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2713:2:2713:15|Tristate driver SLAVE28_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE28_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2705:2:2705:15|Tristate driver SLAVE27_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE27_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2697:2:2697:15|Tristate driver SLAVE26_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE26_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2689:2:2689:15|Tristate driver SLAVE25_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE25_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2681:2:2681:15|Tristate driver SLAVE24_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE24_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2673:2:2673:15|Tristate driver SLAVE23_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE23_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\coreaxi4interconnect.v":2665:2:2665:15|Tristate driver SLAVE22_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) on net SLAVE22_RREADY (in view: work.COREAXI4INTERCONNECT_Z18_layer0(verilog)) has its enable tied to GND.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\hdl\ddr_rw_arbiter_lpddr4.v":303:0:303:5|There are no possible illegal states for state machine Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.local_wbus_state[3:0] (in view: work.DDR4_RD_WR(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk5\.brs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk4\.wrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk3\.rrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk2\.arrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|There are no possible illegal states for state machine rgsl.genblk1\.awrs.currState[3:0] (in view: work.caxi4interconnect_SlaveConvertor_Z26_layer0(verilog)); safe FSM implementation is not required.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":952:26:952:130|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 515 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\regslicefull.v":185:1:185:6|Replicating instance rgsl.genblk4\.wrs.mReady (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 4 loads 1 time to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":129:26:129:68|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0 (in view: work.DDR4_RD_WR(verilog)) with 513 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.DDR4_RD_WR(verilog)) with 512 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\coreaxi4interconnect\2.8.103\rtl\vlog\core\axi4convertors\dwc_downconv_widthconvwr.v":952:26:952:130|Replicating instance mstrDWC.genblk1\.DownConverter_inst.writeWidthConv.widthConvwr.MASTER_WREADY (in view: work.caxi4interconnect_MasterConvertor_Z22_layer0(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":129:26:129:68|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_rep1 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":129:26:129:68|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_rep2 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":129:26:129:68|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0 (in view: work.DDR4_RD_WR(verilog)) with 129 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_fast (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep1 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":130:27:130:79|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_dout_rep2 (in view: work.DDR4_RD_WR(verilog)) with 128 loads 3 times to improve timing.
@N: FX271 :"d:\delme\sev_pfsoc_openvx\hdl\axi_lbus_corefifo_fwft.v":129:26:129:68|Replicating instance Video_arbiter_top_LPDDR4_0.ddr_rw_arbiter_0.v_wr_data_fifo.genblk19\.u_corefifo_fwft.update_middle_0_fast (in view: work.DDR4_RD_WR(verilog)) with 126 loads 3 times to improve timing.
@N: FP130 |Promoting Net DDR4_RD_WR_inst_0.synchronizer_circuit_0.dff_arst_i on CLKINT  I_12970 
