@W: BN114 :|Removing instance CP_fanout_cell_embsync_detect_Z1_layer0_verilog_inst (in view: work.embsync_detect_Z1_layer0_rtl_ilm(verilog)) because it does not drive other instances.
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: FX185 |Ignoring the attribute act_wide_mul_size=1 because it is less than the size of multiplier supported by architecture(18).
@W: MO129 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":6133:12:6133:17|Sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.CSI2_RXDecoder_0.mipicsi2rxdecoderPF_C0_0.genblk1.mipicsi2rxdecoderPF_0.mipi_csi2_rxdecoder_0.b2p.genblk7.pix_distribute_4lane[2] is reduced to a combinational gate by constant propagation.
@W: FX107 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":6641:2:6641:7|RAM dcram.ram_block[31:0] (in view: work.mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C3_0.CORERXIODBITALIGN_C3_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C2_0.CORERXIODBITALIGN_C2_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Removing sequential instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C1_0.CORERXIODBITALIGN_C1_0.u_CoreRxIODBitAlign.rst_cnt[9:0] because it is equivalent to instance DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.CORERXIODBITALIGN_C0_0.CORERXIODBITALIGN_C0_0.u_CoreRxIODBitAlign.rst_cnt[9:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MT246 :"d:\delme\sev_pfsoc_openvx\component\work\init_monitor\init_monitor_0\init_monitor_init_monitor_0_pfsoc_init_monitor.v":44:53:44:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT246 :"d:\delme\sev_pfsoc_openvx\component\work\pf_iod_generic_rx_c0\pf_iod_rx\pf_iod_generic_rx_c0_pf_iod_rx_pf_iod.v":311:20:311:38|Blackbox INBUF_DIFF_MIPI is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT116 |Paths from clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV:r) to clock (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0:r) are overconstrained because the required time of 0.24 ns is too small.  
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":50:0:50:0|Timing constraint (to [get_pins { DDR4_RD_WR_inst_0.IMX334_IF_TOP_0.PF_IOD_GENERIC_RX_C0_0.PF_IOD_0.PF_LANECTRL_0.I_LANECTRL*.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"d:/delme/sev_pfsoc_openvx/designer/sev_pfsoc_openvx/synthesis.fdc":51:0:51:0|Timing constraint (through [get_nets { FIC_BRIDGE_0.DMA_MASTER_0.ARESETN* }]) (false path) was not applied to the design because none of the '-through' objects specified by the constraint exist in the design 
