@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1677:7:1677:20|Found compile point of type hard on View view:work.embsync_detect_Z1_layer0(verilog) 
@N: MF104 :"d:\delme\sev_pfsoc_openvx\component\work\imx334_if_top\imx334_if_top.v":9:7:9:19|Found compile point of type hard on View view:work.IMX334_IF_TOP(verilog) 
@N: MF105 |Performing bottom-up mapping of Compile point view:work.IMX334_IF_TOP(verilog) 
@N: MF106 :"d:\delme\sev_pfsoc_openvx\component\work\imx334_if_top\imx334_if_top.v":9:7:9:19|Mapping Compile point view:work.IMX334_IF_TOP(verilog) because 
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":56:40:56:46|Tristate driver TUSER_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":56:40:56:46|Tristate driver TUSER_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":56:40:56:46|Tristate driver TUSER_O_3 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_3 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":56:40:56:46|Tristate driver TUSER_O_4 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TUSER_O_4 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":55:38:55:44|Tristate driver TLAST_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TLAST_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":54:38:54:45|Tristate driver TVALID_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TVALID_O (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":53:46:53:52|Tristate driver TKEEP_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TKEEP_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":52:46:52:52|Tristate driver TSTRB_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TSTRB_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":51:46:51:52|Tristate driver TDATA_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TDATA_O_1 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO111 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":51:46:51:52|Tristate driver TDATA_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) on net TDATA_O_2 (in view: work.mipicsi2rxdecoderPF_10s_4s_1s_0s_12s_0s(verilog)) has its enable tied to GND.
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":1125:10:1125:15|Found counter in view:work.mipi_csi2_rxdecoder_Z3_layer0(verilog) instance genblk2\.pixel_count[15:2] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":5888:2:5888:7|Found counter in view:work.byte2pixel_conversion_Z2_layer0(verilog) instance wait_count[5:0] 
@N: MF179 :"d:\delme\sev_pfsoc_openvx\component\microsemi\solutioncore\mipicsi2rxdecoderpf\4.4.0\rtl\mipicsi2rxdecoderpf.v":6589:22:6589:48|Found 12 by 12 bit equality operator ('==') rdempty (in view: work.mipi_csi2_rx_cdcfifo_4294967292s_40s_1_3(verilog))
@N: MO230 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c0\corerxiodbitalign_c0_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance tap_cnt[7:0]  
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c0\corerxiodbitalign_c0_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance emflag_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c0\corerxiodbitalign_c0_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance timeout_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c0\corerxiodbitalign_c0_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C0_CORERXIODBITALIGN_C0_0_CORERXIODBITALIGN_TRNG_Z4_layer0(verilog) instance rst_cnt[9:0] 
@N: MO230 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance tap_cnt[7:0]  
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance emflag_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance timeout_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c1\corerxiodbitalign_c1_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C1_CORERXIODBITALIGN_C1_0_CORERXIODBITALIGN_TRNG_Z5_layer0(verilog) instance rst_cnt[9:0] 
@N: MO230 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance tap_cnt[7:0]  
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance emflag_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance timeout_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c2\corerxiodbitalign_c2_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C2_CORERXIODBITALIGN_C2_0_CORERXIODBITALIGN_TRNG_Z6_layer0(verilog) instance rst_cnt[9:0] 
@N: MO230 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found up-down counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance tap_cnt[7:0]  
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance emflag_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":269:3:269:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance timeout_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\work\corerxiodbitalign_c3\corerxiodbitalign_c3_0\rtl\vlog\core\corerxiodbitalign.v":991:3:991:8|Found counter in view:CORERXIODBITALIGN_LIB.CORERXIODBITALIGN_C3_CORERXIODBITALIGN_C3_0_CORERXIODBITALIGN_TRNG_Z7_layer0(verilog) instance rst_cnt[9:0] 
@N: MO225 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":214:3:214:8|There are no possible illegal states for state machine clkalign_curr_state[63:0] (in view: work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog)); safe FSM implementation is not required.
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":991:3:991:8|Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance tapcnt_offset[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":947:3:947:8|Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance tap_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":907:3:907:8|Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance timeout_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":1007:3:1007:8|Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance emflag_cnt[7:0] 
@N: MO231 :"d:\delme\sev_pfsoc_openvx\component\actel\directcore\corebclksclkalign\2.0.111\rtl\vlog\core\icb_bclksclkalign.v":1191:3:1191:8|Found counter in view:work.ICB_BCLKSCLKALIGN_Z9_layer0(verilog) instance rst_cnt[9:0] 
@N: MT615 |Found clock CAM1_RX_CLK_P with period 4.00ns 
@N: MT615 |Found clock DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV with period 16.00ns 
@N: MT615 |Found clock DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 with period 5.88ns 
@N: MT320 |This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report.
@N: MT322 |Clock constraints include only register-to-register paths associated with each individual clock.
