Jitter Estimation Report
========================

Date           : Mon Nov 21 15:30:02 2022
Libero version : 2022.2.0.10
Design         : SEV_PFSoC_OpenVX
Family         : PolarFireSoC
Die            : MPFS250T_ES
Speed grade    : -1
Data state     : Production


System Jitter Calculation
-------------------------

Worst aggressor based on load:    CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0
System jitter (worst aggressor):  0.007 ns


Jitter Calculation per Clock Domain
-----------------------------------

Clock: CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0

 (1) System jitter (worst aggressor):              0.007 ns
 (2) PLL jitter:                                   0.135 ns

     Resulting clock jitter (max of (1) and (2)):  0.135 ns


Clock: CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0

 (1) System jitter (worst aggressor):              0.007 ns
 (2) PLL jitter:                                   0.135 ns

     Resulting clock jitter (max of (1) and (2)):  0.135 ns


Clock: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV

 (1) System jitter (worst aggressor):              0.007 ns
 (2) Master Clock jitter:                          0.007 ns

     Resulting clock jitter (max of (1) and (2)):  0.007 ns


Clock: CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK

 (1) System jitter (worst aggressor):              0.007 ns
 (2) RC Oscillator jitter:                        10.000 ns

     Resulting clock jitter (max of (1) and (2)): 10.000 ns


Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R

     Regional jitter:                              0.000 ns

     Resulting clock jitter:                       0.000 ns


Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R

     Regional jitter:                              0.000 ns

     Resulting clock jitter:                       0.000 ns


Clock: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0

 (1) System jitter (worst aggressor):              0.007 ns
 (2) PLL jitter:                                   0.135 ns

     Resulting clock jitter (max of (1) and (2)):  0.135 ns


Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R

     Regional jitter:                              0.002 ns

     Resulting clock jitter:                       0.002 ns


Clock: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R

     Regional jitter:                              0.000 ns

     Resulting clock jitter:                       0.000 ns


Clock: CAM1_RX_CLK_P

     System jitter (worst aggressor):              0.007 ns
     Resulting clock jitter:                       0.007 ns


Clock: REF_CLK_PAD_P

 (1) System jitter (worst aggressor):              0.007 ns
 (2) Input jitter:                                 0.000 ns

     Resulting clock jitter (max of (1) and (2)):  0.007 ns


