ANALYSIS_BOTTLENECK_COST_TYPE,Path Count
ANALYSIS_BREAK_AT_ASYNC,1
ANALYSIS_CLOCKLIST_SORT_CRITERIA,NAME
ANALYSIS_ENABLE_INTERDOMAINS,1
ANALYSIS_ENHANCED_MIN_TIMING,0
ANALYSIS_EXPAND_CLOCK_NETWORK,1
ANALYSIS_INCLUDE_ASYNC_SETS,1
ANALYSIS_LIMIT_PATHS,1
ANALYSIS_MAX_BOTTLENECK_INSTANCES,10
ANALYSIS_MAX_OPCOND,slow_lv_ht
ANALYSIS_MAX_PARALLEL_PATHS,1
ANALYSIS_MAX_PATHS,20
ANALYSIS_MAX_SLACK,0
ANALYSIS_MIN_OPCOND,fast_hv_lt
ANALYSIS_MIN_SLACK,0
ANALYSIS_USE_LOOPBACK,0
ANALYSIS_USE_MAX_SLACK,0
ANALYSIS_USE_MIN_SLACK,0
ANALYSIS_USE_SLACK_THRESHOLD,0
BOTTLENECK_REPORT_ANALYSIS_TYPE,1
BOTTLENECK_REPORT_MAX_PARALLEL_PATHS,1
BOTTLENECK_REPORT_MAX_PATHS,100
BOTTLENECK_REPORT_SLACK_THRESHOLD,0
IS_VIOLATION_REPORT,0
MULTI_CORNER_REPORT_FLAG,0
PATH_TRACING_ALGORITHM,1
REPORT_ANALYSIS_TYPE,1
REPORT_CLOCK_DOMAINS,CAM1_RX_CLK_P CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C2_0/CORERXIODBITALIGN_C2_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C3_0/CORERXIODBITALIGN_C3_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_MOVE:Q DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R REF_CLK_PAD_P 
REPORT_FORMAT,TEXT
REPORT_MAX_EXPANDED_PATHS,1
REPORT_MAX_PARALLEL_PATHS,1
REPORT_MAX_PATHS,5
REPORT_SHOW_CLOCK_DOMAINS,1
REPORT_SHOW_INOUT_SETS,1
REPORT_SHOW_PATHS,1
REPORT_SHOW_SUMMARY,1
REPORT_SHOW_USER_SETS,0
REPORT_SLACK_THRESHOLD,0
REPORT_USE_CLOCK_DOMAINS,0
REPORT_USE_SLACK_THRESHOLD,0
STATS_REPORT_NUMBER_DETAILS,100
STATS_REPORT_SLACKS,0
VIOLATION_REPORT_ANALYSIS_TYPE,1
VIOLATION_REPORT_LIMIT_PATHS,1
VIOLATION_REPORT_MAX_EXPANDED_PATHS,0
VIOLATION_REPORT_MAX_PARALLEL_PATHS,1
VIOLATION_REPORT_MAX_PATHS,20
VIOLATION_REPORT_SLACK_THRESHOLD,0
VIOLATION_REPORT_USE_SLACK_THRESHOLD,1
