"CAM1_RX_CLK_P",4,"CAM1_RX_CLK_P","CAM1_RX_CLK_P"
"CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0",20,"CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0","CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0"
"CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0",5,"CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0","CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0"
"CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK",500,"CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2:CLK","CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2:CLK"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C2_0/CORERXIODBITALIGN_C2_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C2_0/CORERXIODBITALIGN_C2_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C2_0/CORERXIODBITALIGN_C2_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C3_0/CORERXIODBITALIGN_C3_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C3_0/CORERXIODBITALIGN_C3_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C3_0/CORERXIODBITALIGN_C3_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_MOVE:Q",,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_MOVE:Q","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_MOVE:Q"
"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV",16,"DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV","DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV"
"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R",13.468,"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R","DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R"
"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R",13.468,"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_CLK_R","DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_CLK_R"
"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R",13.468,"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_CLK_R","DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_CLK_R"
"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R",13.468,"DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_CLK_R","DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_CLK_R"
"REF_CLK_PAD_P",6.734,"REF_CLK_PAD_P","REF_CLK_PAD_P"
