SmartTime Version 2022.2.0.10
Microchip Technology Inc. - Microchip Libero Software Release v2022.2 (Version 2022.2.0.10)
Date: Mon Nov 21 15:57:25 2022
| Design | SEV_PFSoC_OpenVX |
| Family | PolarFireSoC |
| Die | MPFS250T_ES |
| Package | FCG1152 |
| Temperature Range | 0 - 100 C |
| Voltage Range | 0.97 - 1.03 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | slow_lv_lt,fast_hv_lt,slow_lv_ht |
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| CAM1_RX_CLK_P | 4.000 | 250.000 | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 | 20.000 | 50.000 | 9.051 | slow_lv_lt |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | 5.000 | 200.000 | 0.912 | slow_lv_ht |
| CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2/CLK | 500.000 | 2.000 | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 | 5.882 | 170.010 | 0.762 | slow_lv_lt |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q | N/A | N/A | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q | N/A | N/A | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C2_0/CORERXIODBITALIGN_C2_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q | N/A | N/A | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C3_0/CORERXIODBITALIGN_C3_0/u_CoreRxIODBitAlign/rx_BIT_ALGN_MOVE:Q | N/A | N/A | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_MOVE:Q | N/A | N/A | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | 16.000 | 62.500 | 6.214 | slow_lv_ht |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R | 13.468 | 74.250 | 7.526 | slow_lv_ht |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R | 13.468 | 74.250 | 9.672 | slow_lv_lt |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R | 13.468 | 74.250 | 9.332 | slow_lv_lt |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R | 13.468 | 74.250 | 9.756 | slow_lv_lt |
| REF_CLK_PAD_P | 6.734 | 148.500 |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
Info: The maximum frequency of this clock domain is limited by the period of pin DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_RXCLK/I_CDD:A
No Path
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin MSS/I_MSS:FIC_3_PCLK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[6]:CLK | MSS/I_MSS:FIC_3_APB_M_PRDATA[6] | 0.965 | 9.051 | 10.434 | 19.485 | -0.138 | 1.628 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[0]:CLK | MSS/I_MSS:FIC_3_APB_M_PRDATA[0] | 0.889 | 9.086 | 10.357 | 19.443 | -0.096 | 1.558 | slow_lv_lt |
| Path 3 | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[5]:CLK | MSS/I_MSS:FIC_3_APB_M_PRDATA[5] | 0.993 | 9.087 | 10.461 | 19.548 | -0.201 | 1.556 | slow_lv_lt |
| Path 4 | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[7]:CLK | MSS/I_MSS:FIC_3_APB_M_PRDATA[7] | 0.959 | 9.095 | 10.428 | 19.523 | -0.176 | 1.540 | slow_lv_lt |
| Path 5 | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[10]:CLK | MSS/I_MSS:FIC_3_APB_M_PRDATA[10] | 1.077 | 9.103 | 10.546 | 19.649 | -0.302 | 1.524 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[6]:CLK | ||||||||
| To: MSS/I_MSS:FIC_3_APB_M_PRDATA[6] | ||||||||
| data required time | 19.485 | |||||||
| data arrival time | - | 10.434 | ||||||
| slack | 9.051 | |||||||
| Data arrival time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 7.433 | 7.433 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 | + | 0.357 | 7.790 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.161 | 7.951 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_NET | + | 0.357 | 8.308 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.178 | 8.486 | 3 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_Y | + | 0.414 | 8.900 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3:Y | cell | ADLIB:RGB | + | 0.060 | 8.960 | 56 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[6]:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3_rgb_net_1 | + | 0.509 | 9.469 | r | ||
| DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/prdata_o[6]:Q | cell | ADLIB:SLE | + | 0.218 | 9.687 | 1 | r | |
| MSS/I_MSS:FIC_3_APB_M_PRDATA[6] | net | MSS_FIC_3_APB_INITIATOR_PRDATA[6] | + | 0.747 | 10.434 | r | ||
| data arrival time | 10.434 | |||||||
| Data required time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 | Clock Constraint | 10.000 | 10.000 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 10.000 | f | |||
| Clock generation | + | 5.869 | 15.869 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 | + | 0.339 | 16.208 | f | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.153 | 16.361 | 2 | f | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_NET | + | 0.312 | 16.673 | f | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.152 | 16.825 | 3 | f | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB4:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_Y | + | 0.377 | 17.202 | f | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB4:Y | cell | ADLIB:RGB | + | 0.056 | 17.258 | 0 | r | |
| MSS/I_MSS:FIC_3_PCLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 | + | 0.561 | 17.819 | f | ||
| clock reconvergence pessimism | + | 1.663 | 19.482 | |||||
| clock jitter | - | 0.135 | 19.347 | |||||
| MSS/I_MSS:FIC_3_APB_M_PRDATA[6] | Library setup time | ADLIB:MSS | - | -0.138 | 19.485 | |||
| data required time | 19.485 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o_fast[0]:ALn | 3.040 | 16.487 | 12.932 | 29.419 | 0.196 | 3.378 | 0.142 | slow_lv_ht |
| Path 2 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o[1]:ALn | 2.817 | 16.697 | 12.709 | 29.406 | 0.209 | 3.168 | 0.142 | slow_lv_ht |
| Path 3 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/rconst_o[7]:ALn | 2.688 | 16.837 | 12.580 | 29.417 | 0.196 | 3.028 | 0.144 | slow_lv_ht |
| Path 4 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/rconst_o[6]:ALn | 2.688 | 16.837 | 12.580 | 29.417 | 0.196 | 3.028 | 0.144 | slow_lv_ht |
| Path 5 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/ddr_wr1_addr_o[6]:ALn | 2.688 | 16.837 | 12.580 | 29.417 | 0.196 | 3.028 | 0.144 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o_fast[0]:ALn | ||||||||
| data required time | 29.419 | |||||||
| data arrival time | - | 12.932 | ||||||
| slack | 16.487 | |||||||
| Data arrival time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 7.762 | 7.762 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 | + | 0.356 | 8.118 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.164 | 8.282 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_GB0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_NET | + | 0.382 | 8.664 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.171 | 8.835 | 3 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB2:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_gbs_1 | + | 0.441 | 9.276 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.059 | 9.335 | 11 | f | |
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB2_rgb_net_1 | + | 0.557 | 9.892 | r | ||
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_50MHz/CORERESET_PF_C3_0/dff_15:Q | cell | ADLIB:SLE | + | 0.209 | 10.101 | 70 | r | |
| DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o_fast[0]:ALn | net | CLOCKS_AND_RESETS_inst_0_CORERESET_CLK_50MHz_CORERESET_PF_C3_0_dff | + | 2.831 | 12.932 | r | ||
| data arrival time | 12.932 | |||||||
| Data required time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0/OUT0 | Clock Constraint | 20.000 | 20.000 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 20.000 | r | |||
| Clock generation | + | 6.455 | 26.455 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 | + | 0.324 | 26.779 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.142 | 26.921 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0_NET | + | 0.348 | 27.269 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.156 | 27.425 | 3 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_Y | + | 0.403 | 27.828 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3:Y | cell | ADLIB:RGB | + | 0.052 | 27.880 | 56 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o_fast[0]:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_RGB1_RGB3_rgb_net_1 | + | 0.475 | 28.355 | r | ||
| clock reconvergence pessimism | + | 1.395 | 29.750 | |||||
| clock jitter | - | 0.135 | 29.615 | |||||
| DDR4_RD_WR_inst_0/video_processing_0/apb3_interface_0/bayer_o_fast[0]:ALn | Library recovery time | ADLIB:SLE | - | 0.196 | 29.419 | |||
| data required time | 29.419 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[241]:D | 3.642 | 0.912 | 16.905 | 17.817 | 0.000 | 3.953 | slow_lv_ht |
| Path 2 | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[255]:D | 3.625 | 0.925 | 16.888 | 17.813 | 0.000 | 3.940 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C9/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[360]:D | 3.619 | 0.935 | 16.882 | 17.817 | 0.000 | 3.930 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[269]:D | 3.599 | 0.948 | 16.862 | 17.810 | 0.000 | 3.917 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/middle_dout[26]:D | 3.589 | 0.979 | 16.844 | 17.823 | 0.000 | 3.886 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:A_CLK | ||||||||
| To: DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[241]:D | ||||||||
| data required time | 17.817 | |||||||
| data arrival time | - | 16.905 | ||||||
| slack | 0.912 | |||||||
| Data arrival time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 11.115 | 11.115 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 | + | 0.163 | 11.278 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.167 | 11.445 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_NET | + | 0.372 | 11.817 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:Y | cell | ADLIB:GB | + | 0.170 | 11.987 | 5 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB10:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_Y | + | 0.449 | 12.436 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB10:Y | cell | ADLIB:RGB | + | 0.059 | 12.495 | 809 | f | |
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:A_CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB10_rgb_net_1 | + | 0.768 | 13.263 | r | ||
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk24.UI_ram_wrapper_1/L3_syncnonpipe/genblk1.fi_te_fi_te_0_LSRAM_top_R0C6/INST_RAM1K20_IP:B_DOUT[1] | cell | ADLIB:RAM1K20_IP | + | 2.319 | 15.582 | 2 | f | |
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/int_MEMRD_fwft_1[241]:B | net | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/RDATA_int[241] | + | 1.090 | 16.672 | f | ||
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/int_MEMRD_fwft_1[241]:Y | cell | ADLIB:CFG4 | + | 0.052 | 16.724 | 2 | f | |
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout_2[241]:C | net | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/int_MEMRD_fwft_1_Z[241] | + | 0.072 | 16.796 | f | ||
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout_2[241]:Y | cell | ADLIB:CFG3 | + | 0.085 | 16.881 | 1 | f | |
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[241]:D | net | DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout_2_Z[241] | + | 0.024 | 16.905 | f | ||
| data arrival time | 16.905 | |||||||
| Data required time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | Clock Constraint | 5.000 | 5.000 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 5.000 | r | |||
| Clock generation | + | 9.499 | 14.499 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 | + | 0.149 | 14.648 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.145 | 14.793 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_NET | + | 0.339 | 15.132 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:Y | cell | ADLIB:GB | + | 0.155 | 15.287 | 5 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB7:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_Y | + | 0.405 | 15.692 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB7:Y | cell | ADLIB:RGB | + | 0.052 | 15.744 | 1605 | f | |
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[241]:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB7_rgb_net_1 | + | 0.501 | 16.245 | r | ||
| clock reconvergence pessimism | + | 1.707 | 17.952 | |||||
| clock jitter | - | 0.135 | 17.817 | |||||
| DDR4_RD_WR_inst_0/Video_arbiter_top_LPDDR4_0/ddr_rw_arbiter_0/v_wr_data_fifo/genblk19.u_corefifo_fwft/dout[241]:D | Library setup time | ADLIB:SLE | - | 0.000 | 17.817 | |||
| data required time | 17.817 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15:CLK | VSC_8662_RESETN | 11.277 | 24.338 | 24.338 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15:CLK | ||||||||
| To: VSC_8662_RESETN | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 24.338 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 11.115 | 11.115 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 | + | 0.163 | 11.278 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.167 | 11.445 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_NET | + | 0.372 | 11.817 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.170 | 11.987 | 9 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB2:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_gbs_1 | + | 0.449 | 12.436 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.059 | 12.495 | 729 | f | |
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB2_rgb_net_1 | + | 0.566 | 13.061 | r | ||
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15:Q | cell | ADLIB:SLE | + | 0.190 | 13.251 | 40 | f | |
| VSC_8662_RESETN_obuf/U_IOTRI:D | net | CLOCKS_AND_RESETS_inst_0_CORERESET_CLK_200MHz_CORERESET_PF_C4_0_dff | + | 7.542 | 20.793 | f | ||
| VSC_8662_RESETN_obuf/U_IOTRI:DOUT | cell | ADLIB:IOTRI_OB_EB | + | 0.918 | 21.711 | 1 | f | |
| VSC_8662_RESETN_obuf/U_IOPAD:D | net | VSC_8662_RESETN_obuf/DOUT | + | 0.000 | 21.711 | f | ||
| VSC_8662_RESETN_obuf/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.627 | 24.338 | 0 | f | |
| VSC_8662_RESETN | net | VSC_8662_RESETN | + | 0.000 | 24.338 | f | ||
| data arrival time | 24.338 | |||||||
| Data required time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | N/C | N/C | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 9.499 | N/C | |||||
| VSC_8662_RESETN | N/C | f | ||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_10/INST_RAM1K20_IP:A_DOUT_ARST_N | 2.758 | 1.852 | 15.823 | 17.675 | 0.281 | 3.013 | -0.026 | slow_lv_ht |
| Path 2 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/Register_Config_1/Data_O[424]:ALn | 2.626 | 1.898 | 15.691 | 17.589 | 0.196 | 2.967 | 0.145 | slow_lv_ht |
| Path 3 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/Register_Config_1/Data_O[421]:ALn | 2.625 | 1.899 | 15.690 | 17.589 | 0.196 | 2.966 | 0.145 | slow_lv_ht |
| Path 4 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/Register_Config_1/Data_O[327]:ALn | 2.554 | 1.959 | 15.619 | 17.578 | 0.196 | 2.906 | 0.156 | slow_lv_ht |
| Path 5 | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/Register_Config_1/Data_O[375]:ALn | 2.489 | 2.034 | 15.554 | 17.588 | 0.196 | 2.831 | 0.146 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_10/INST_RAM1K20_IP:A_DOUT_ARST_N | ||||||||
| data required time | 17.675 | |||||||
| data arrival time | - | 15.823 | ||||||
| slack | 1.852 | |||||||
| Data arrival time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 11.115 | 11.115 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 | + | 0.163 | 11.278 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.167 | 11.445 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_NET | + | 0.372 | 11.817 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.170 | 11.987 | 9 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB5:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_gbs_1 | + | 0.448 | 12.435 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB5:Y | cell | ADLIB:RGB | + | 0.059 | 12.494 | 651 | f | |
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB5_rgb_net_1 | + | 0.571 | 13.065 | r | ||
| CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep:Q | cell | ADLIB:SLE | + | 0.201 | 13.266 | 2359 | r | |
| DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_10/INST_RAM1K20_IP:A_DOUT_ARST_N | net | CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_Z | + | 2.557 | 15.823 | r | ||
| data arrival time | 15.823 | |||||||
| Data required time calculation | ||||||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0/OUT0 | Clock Constraint | 5.000 | 5.000 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 5.000 | r | |||
| Clock generation | + | 9.499 | 14.499 | |||||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 | + | 0.149 | 14.648 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.145 | 14.793 | 2 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0_NET | + | 0.339 | 15.132 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0:Y | cell | ADLIB:GB | + | 0.155 | 15.287 | 5 | r | |
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB12:A | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_Y | + | 0.401 | 15.688 | r | ||
| CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB12:Y | cell | ADLIB:RGB | + | 0.052 | 15.740 | 3 | f | |
| DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_10/INST_RAM1K20_IP:A_CLK | net | CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_RGB1_RGB12_rgb_net_1 | + | 0.666 | 16.406 | r | ||
| clock reconvergence pessimism | + | 1.685 | 18.091 | |||||
| clock jitter | - | 0.135 | 17.956 | |||||
| DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_10/INST_RAM1K20_IP:A_DOUT_ARST_N | Library recovery time | ADLIB:RAM1K20_IP | - | 0.281 | 17.675 | |||
| data required time | 17.675 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD:A
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:CLK | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[35] | 3.442 | 0.762 | 10.683 | 11.445 | 1.540 | 4.985 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:CLK | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[33] | 3.409 | 0.770 | 10.650 | 11.420 | 1.565 | 4.977 | slow_lv_lt |
| Path 3 | DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[7]:CLK | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKr89rm87lxmGG16[22:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[35] | 3.414 | 0.783 | 10.658 | 11.441 | 1.540 | 4.964 | slow_lv_lt |
| Path 4 | DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:CLK | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[21] | 3.410 | 0.783 | 10.651 | 11.434 | 1.551 | 4.964 | slow_lv_lt |
| Path 5 | DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[7]:CLK | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKr89rm87lxmGG16[22:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[33] | 3.382 | 0.790 | 10.626 | 11.416 | 1.565 | 4.957 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[35] | ||||||||
| data required time | 11.445 | |||||||
| data arrival time | - | 10.683 | ||||||
| slack | 0.762 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 5.178 | 5.178 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 | + | 0.373 | 5.551 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.163 | 5.714 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_NET | + | 0.356 | 6.070 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:Y | cell | ADLIB:GB | + | 0.179 | 6.249 | 9 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y | + | 0.419 | 6.668 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.060 | 6.728 | 427 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2_rgb_net_1 | + | 0.513 | 7.241 | r | ||
| DDR4_RD_WR_inst_0/video_processing_0/Image_Enhancement_C0_0/Image_Enhancement_C0_0/MSC_i_3/IeydDCpehA[1]:Q | cell | ADLIB:SLE | + | 0.218 | 7.459 | 3 | r | |
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/IdqzHC4qy2hbxgncpLrej4uEdBvtv2dwq[26:4]/MACC_PHYS_INST/CFG_2:A | net | DDR4_RD_WR_inst_0/video_processing_0/DATA_O_net_0[9] | + | 0.590 | 8.049 | r | ||
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/IdqzHC4qy2hbxgncpLrej4uEdBvtv2dwq[26:4]/MACC_PHYS_INST/CFG_2:Y | cell | ADLIB:CFG4_IP_ABCD | + | 0.079 | 8.128 | 1 | r | |
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/IdqzHC4qy2hbxgncpLrej4uEdBvtv2dwq[26:4]/MACC_PHYS_INST/INST_MACC_IP:A[1] | net | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/IdqzHC4qy2hbxgncpLrej4uEdBvtv2dwq[26_4]/MACC_PHYS_INST/A_net[1] | + | 0.022 | 8.150 | r | ||
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/IdqzHC4qy2hbxgncpLrej4uEdBvtv2dwq[26:4]/MACC_PHYS_INST/INST_MACC_IP:CDOUT[35] | cell | ADLIB:MACC_IP | + | 2.520 | 10.670 | 1 | r | |
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[35] | net | DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/MSC_net_466 | + | 0.013 | 10.683 | r | ||
| data arrival time | 10.683 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 | Clock Constraint | 5.882 | 5.882 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 5.882 | r | |||
| Clock generation | + | 4.653 | 10.535 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 | + | 0.339 | 10.874 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.141 | 11.015 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_NET | + | 0.325 | 11.340 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:Y | cell | ADLIB:GB | + | 0.163 | 11.503 | 9 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y | + | 0.378 | 11.881 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB0:Y | cell | ADLIB:RGB | + | 0.053 | 11.934 | 345 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB0_rgb_net_1 | + | 0.554 | 12.488 | r | ||
| clock reconvergence pessimism | + | 0.632 | 13.120 | |||||
| clock jitter | - | 0.135 | 12.985 | |||||
| DDR4_RD_WR_inst_0/video_processing_0/RGBtoYCbCr_C0_0/MSC_i_0/MSC_i_1/I4eFkl7aJnpBIJaJKrdib33bpq6EyCq[20:0]/MACC_PHYS_INST/INST_MACC_IP:CDIN[35] | Library setup time | ADLIB:MACC_IP | - | 1.540 | 11.445 | |||
| data required time | 11.445 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM2_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | 2.519 | 3.021 | 9.976 | 12.997 | 0.257 | 2.726 | -0.050 | slow_lv_ht |
| Path 2 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM3_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | 2.519 | 3.023 | 9.976 | 12.999 | 0.257 | 2.724 | -0.052 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM1_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | 2.503 | 3.029 | 9.960 | 12.989 | 0.257 | 2.718 | -0.042 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/data_packer_0/s_data_pack[309]:ALn | 2.343 | 3.086 | 9.800 | 12.886 | 0.209 | 2.661 | 0.109 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | DDR4_RD_WR_inst_0/DDR_Write_LPDDR4_0/data_packer_0/s_data_pack[290]:ALn | 2.343 | 3.086 | 9.800 | 12.886 | 0.209 | 2.661 | 0.109 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM2_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | ||||||||
| data required time | 12.997 | |||||||
| data arrival time | - | 9.976 | ||||||
| slack | 3.021 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 5.304 | 5.304 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 | + | 0.370 | 5.674 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.166 | 5.840 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_NET | + | 0.382 | 6.222 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:Y | cell | ADLIB:GB | + | 0.172 | 6.394 | 9 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB7:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y | + | 0.432 | 6.826 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB7:Y | cell | ADLIB:RGB | + | 0.059 | 6.885 | 17 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB7_rgb_net_1 | + | 0.572 | 7.457 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:Q | cell | ADLIB:SLE | + | 0.201 | 7.658 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_Z | + | 0.907 | 8.565 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F:Y | cell | ADLIB:GB | + | 0.127 | 8.692 | 4 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_RGB1_RGB2:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_Y | + | 0.451 | 9.143 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.059 | 9.202 | 417 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM2_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_RGB1_RGB2_rgb_net_1 | + | 0.774 | 9.976 | r | ||
| data arrival time | 9.976 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0/OUT0 | Clock Constraint | 5.882 | 5.882 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 5.882 | r | |||
| Clock generation | + | 4.761 | 10.643 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 | + | 0.337 | 10.980 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.144 | 11.124 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0_NET | + | 0.348 | 11.472 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0:Y | cell | ADLIB:GB | + | 0.157 | 11.629 | 9 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y | + | 0.408 | 12.037 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.052 | 12.089 | 427 | f | |
| DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM2_INST/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_RGB1_RGB2_rgb_net_1 | + | 0.647 | 12.736 | r | ||
| clock reconvergence pessimism | + | 0.653 | 13.389 | |||||
| clock jitter | - | 0.135 | 13.254 | |||||
| DDR4_RD_WR_inst_0/video_processing_0/Bayer_Interpolation_C0_0/Bayer_Interpolation_C0_0/Bayer_Native_FORMAT.Bayer_Native_INST_0/bayer_interpolation_1pix.Bayer_Interpolation_1pix_inst/RAM2_INST/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT_ARST_N | Library recovery time | ADLIB:RAM1K20_IP | - | 0.257 | 12.997 | |||
| data required time | 12.997 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:DELAY_LINE_MOVE
No Path
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync_0:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync:D | 0.378 | 7.552 | 4.151 | 11.703 | 0.000 | 0.882 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk18.U0/dcram/ram_block_ram_block_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk1.word_cnt_detect[7]:SLn | 5.226 | 10.454 | 9.374 | 19.828 | 0.049 | 5.539 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk18.U0/dcram/ram_block_ram_block_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk1.word_cnt_detect[5]:SLn | 5.226 | 10.454 | 9.374 | 19.828 | 0.049 | 5.539 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk18.U0/dcram/ram_block_ram_block_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk1.word_cnt_detect[3]:SLn | 5.226 | 10.454 | 9.374 | 19.828 | 0.049 | 5.539 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk18.U0/dcram/ram_block_ram_block_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CSI2_RXDecoder_0/mipicsi2rxdecoderPF_C0_0/genblk1.mipicsi2rxdecoderPF_0/embsync_detect_0/genblk1.word_cnt_detect[1]:SLn | 5.225 | 10.455 | 9.373 | 19.828 | 0.049 | 5.538 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync_0:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync:D | ||||||||
| data required time | 11.703 | |||||||
| data arrival time | - | 4.151 | ||||||
| slack | 7.552 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.038 | 2.038 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO_CLK_DIV_OUT | + | 0.000 | 2.038 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.146 | 2.184 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_NET | + | 0.390 | 2.574 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:Y | cell | ADLIB:GB | + | 0.180 | 2.754 | 6 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y | + | 0.399 | 3.153 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:Y | cell | ADLIB:RGB | + | 0.060 | 3.213 | 1805 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync_0:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4_rgb_net_1 | + | 0.560 | 3.773 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync_0:Q | cell | ADLIB:SLE | + | 0.218 | 3.991 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync:D | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pause_sync_0_i | + | 0.160 | 4.151 | r | ||
| data arrival time | 4.151 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | Clock Constraint | 8.000 | 8.000 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV | Clock source | + | 0.000 | 8.000 | f | |||
| Clock generation | + | 1.784 | 9.784 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO_CLK_DIV_OUT | + | 0.000 | 9.784 | f | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.137 | 9.921 | 2 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_NET | + | 0.340 | 10.261 | f | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:Y | cell | ADLIB:GB | + | 0.153 | 10.414 | 6 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y | + | 0.366 | 10.780 | f | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:Y | cell | ADLIB:RGB | + | 0.056 | 10.836 | 1805 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4_rgb_net_1 | + | 0.489 | 11.325 | r | ||
| clock reconvergence pessimism | + | 0.385 | 11.710 | |||||
| clock jitter | - | 0.007 | 11.703 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL_PAUSE_SYNC/pipe_fall.pause_sync:D | Library setup time | ADLIB:SLE | - | 0.000 | 11.703 | |||
| data required time | 11.703 | |||||||
| Operating Conditions | slow_lv_lt |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CAM1_RXD_N[0] | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[6]:D | 6.572 | 6.572 | 0.000 | 3.063 | slow_lv_ht | ||
| Path 2 | CAM1_RXD_N[0] | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[5]:D | 6.539 | 6.539 | 0.000 | 3.030 | slow_lv_ht | ||
| Path 3 | CAM1_RXD_N[0] | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[7]:D | 6.518 | 6.518 | 0.000 | 3.009 | slow_lv_ht | ||
| Path 4 | CAM1_RXD_N[0] | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[4]:D | 6.491 | 6.491 | 0.000 | 2.982 | slow_lv_ht | ||
| Path 5 | CAM1_RXD_N[0] | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[3]:D | 6.289 | 6.289 | 0.000 | 2.780 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CAM1_RXD_N[0] | ||||||||
| To: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[6]:D | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 6.572 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| CAM1_RXD_N[0] | 0.000 | 0.000 | r | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_IOD_RX/I_INBUF_DIFF_MIPI_0/U_IOPADN:PAD | net | CAM1_RXD_N[0] | + | 0.000 | 0.000 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_IOD_RX/I_INBUF_DIFF_MIPI_0/U_IOPADN:Y | cell | ADLIB:IOPADN_IN | + | 0.663 | 0.663 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_IOD_RX/I_INBUF_DIFF_MIPI_0/U_ION:YIN | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_IOD_RX/I_INBUF_DIFF_MIPI_0/U2_N2P | + | 0.000 | 0.663 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_IOD_RX/I_INBUF_DIFF_MIPI_0/U_ION:Y | cell | ADLIB:IOIN_IB_E | + | 0.346 | 1.009 | 6 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/mipi_re_train:D | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0_L0_LP_DATA_N | + | 2.332 | 3.341 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/mipi_re_train:Y | cell | ADLIB:CFG4 | + | 0.051 | 3.392 | 8 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/bitalign_curr_state_0_sqmuxa_2_i_o2:C | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/mipi_re_train_Z | + | 0.444 | 3.836 | f | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/bitalign_curr_state_0_sqmuxa_2_i_o2:Y | cell | ADLIB:CFG3 | + | 0.071 | 3.907 | 5 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/un1_rx_BIT_ALGN_MOVE_0_sqmuxa_0_a3:B | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/N_474 | + | 0.388 | 4.295 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/un1_rx_BIT_ALGN_MOVE_0_sqmuxa_0_a3:Y | cell | ADLIB:CFG4 | + | 0.200 | 4.495 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/un1_rx_BIT_ALGN_MOVE_0_sqmuxa_0:B | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/N_614 | + | 0.126 | 4.621 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/un1_rx_BIT_ALGN_MOVE_0_sqmuxa_0:Y | cell | ADLIB:CFG4 | + | 0.053 | 4.674 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lcry:C | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/un1_rx_BIT_ALGN_MOVE_0_sqmuxa_0_Z | + | 0.356 | 5.030 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lcry:Y | cell | ADLIB:ARI1_CC | + | 0.090 | 5.120 | 8 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lxu[3]:C | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lcry_Y | + | 0.369 | 5.489 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lxu[3]:Y | cell | ADLIB:CFG4 | + | 0.247 | 5.736 | 1 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_cry[3]:B | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lxu_[3] | + | 0.327 | 6.063 | f | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_cry[3]:P | cell | ADLIB:ARI1_CC | + | 0.091 | 6.154 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lcry_cy_CC_0:P[5] | net | NET_CC_CONFIG2239 | + | 0.015 | 6.169 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_lcry_cy_CC_0:CC[8] | cell | ADLIB:CC_CONFIG | + | 0.315 | 6.484 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_cry[6]:CC | net | NET_CC_CONFIG2254 | + | 0.000 | 6.484 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_cry[6]:S | cell | ADLIB:ARI1_CC | + | 0.063 | 6.547 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[6]:D | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt_s[6] | + | 0.025 | 6.572 | r | ||
| data arrival time | 6.572 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | N/C | N/C | ||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 1.891 | N/C | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO_CLK_DIV_OUT | + | 0.000 | N/C | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.130 | N/C | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_NET | + | 0.381 | N/C | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:Y | cell | ADLIB:GB | + | 0.157 | N/C | 6 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y | + | 0.386 | N/C | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:Y | cell | ADLIB:RGB | + | 0.052 | N/C | 1805 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[6]:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4_rgb_net_1 | + | 0.512 | N/C | r | ||
| clock jitter | - | 0.007 | N/C | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C0_0/CORERXIODBITALIGN_C0_0/u_CoreRxIODBitAlign/tap_cnt[6]:D | Library setup time | ADLIB:SLE | - | 0.000 | N/C | |||
| Operating Conditions | slow_lv_ht |
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[6]:ALn | 9.452 | 6.214 | 13.430 | 19.644 | 0.209 | 9.779 | 0.118 | slow_lv_ht |
| Path 2 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[11]:ALn | 9.452 | 6.214 | 13.430 | 19.644 | 0.209 | 9.779 | 0.118 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_lsb[7]:ALn | 9.450 | 6.214 | 13.428 | 19.642 | 0.209 | 9.779 | 0.120 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_lsb[5]:ALn | 9.450 | 6.214 | 13.428 | 19.642 | 0.209 | 9.779 | 0.120 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/early_flags_lsb[69]:ALn | 9.447 | 6.214 | 13.425 | 19.639 | 0.209 | 9.779 | 0.123 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[6]:ALn | ||||||||
| data required time | 19.644 | |||||||
| data arrival time | - | 13.430 | ||||||
| slack | 6.214 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 2.144 | 2.144 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO_CLK_DIV_OUT | + | 0.000 | 2.144 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.150 | 2.294 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_NET | + | 0.419 | 2.713 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:Y | cell | ADLIB:GB | + | 0.173 | 2.886 | 6 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y | + | 0.426 | 3.312 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4:Y | cell | ADLIB:RGB | + | 0.059 | 3.371 | 1805 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB4_rgb_net_1 | + | 0.607 | 3.978 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/COREBCLKSCLKALIGN_0/PF_IOD_GENERIC_RX_C0_TR_0/genblk1.U_ICB_BCLKSCLKALIGN/RX_CLK_ALIGN_DONE:Q | cell | ADLIB:SLE | + | 0.201 | 4.179 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0:B | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CLK_TRAIN_DONE | + | 6.169 | 10.348 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0:Y | cell | ADLIB:CFG2 | + | 0.090 | 10.438 | 1 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_Y | + | 1.752 | 12.190 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7:Y | cell | ADLIB:GB | + | 0.130 | 12.320 | 4 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0_RGB1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0_Y | + | 0.424 | 12.744 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.059 | 12.803 | 609 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[6]:ALn | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_Y_arst | + | 0.627 | 13.430 | r | ||
| data arrival time | 13.430 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD/Y_DIV | Clock Constraint | 16.000 | 16.000 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO/I_CDD:Y_DIV | Clock source | + | 0.000 | 16.000 | r | |||
| Clock generation | + | 1.891 | 17.891 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_CLK_DIV_FIFO_CLK_DIV_OUT | + | 0.000 | 17.891 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.130 | 18.021 | 2 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0_NET | + | 0.381 | 18.402 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0:Y | cell | ADLIB:GB | + | 0.157 | 18.559 | 6 | r | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB2:A | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y | + | 0.382 | 18.941 | r | ||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB2:Y | cell | ADLIB:RGB | + | 0.052 | 18.993 | 1467 | f | |
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[6]:CLK | net | DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_RGB1_RGB2_rgb_net_1 | + | 0.534 | 19.527 | r | ||
| clock reconvergence pessimism | + | 0.333 | 19.860 | |||||
| clock jitter | - | 0.007 | 19.853 | |||||
| DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/CORERXIODBITALIGN_C1_0/CORERXIODBITALIGN_C1_0/u_CoreRxIODBitAlign/late_flags_msb[6]:ALn | Library recovery time | ADLIB:SLE | - | 0.209 | 19.644 | |||
| data required time | 19.644 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_81/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[390]:D | 4.844 | 8.276 | 6.466 | 14.742 | 0.000 | 5.190 | slow_lv_ht |
| Path 2 | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/rbin[7]:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_12/INST_RAM1K20_IP:A_ADDR[9] | 4.754 | 8.282 | 6.135 | 14.417 | 0.445 | 5.184 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_38/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[176]:D | 4.800 | 8.285 | 6.450 | 14.735 | 0.000 | 5.181 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/rbin[11]:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_12/INST_RAM1K20_IP:A_ADDR[13] | 4.561 | 8.323 | 5.951 | 14.274 | 0.588 | 5.143 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/rbin[11]:CLK | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_2/INST_RAM1K20_IP:A_ADDR[13] | 4.508 | 8.382 | 5.898 | 14.280 | 0.588 | 5.084 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_81/INST_RAM1K20_IP:A_CLK | ||||||||
| To: DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[390]:D | ||||||||
| data required time | 14.742 | |||||||
| data arrival time | - | 6.466 | ||||||
| slack | 8.276 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB3:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.807 | 0.807 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB3:Y | cell | ADLIB:RGB | + | 0.059 | 0.866 | 66 | f | |
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_81/INST_RAM1K20_IP:A_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB3_rgb_net_1 | + | 0.756 | 1.622 | r | ||
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0/ram2port_inst/io1l_io1l_0_81/INST_RAM1K20_IP:A_DOUT[1] | cell | ADLIB:RAM1K20_IP | + | 2.284 | 3.906 | 1 | f | |
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/DATA_ASSIGN.s_data_pack_5[390]:A | net | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/video_fifo_0_rdata_o[406] | + | 2.384 | 6.290 | f | ||
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/DATA_ASSIGN.s_data_pack_5[390]:Y | cell | ADLIB:CFG3 | + | 0.151 | 6.441 | 1 | f | |
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[390]:D | net | DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack_5[390] | + | 0.025 | 6.466 | f | ||
| data arrival time | 6.466 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R | Clock Constraint | 13.468 | 13.468 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 13.468 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB2:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.692 | 14.160 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB2:Y | cell | ADLIB:RGB | + | 0.052 | 14.212 | 404 | f | |
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[390]:CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB2_rgb_net_1 | + | 0.497 | 14.709 | r | ||
| clock reconvergence pessimism | + | 0.035 | 14.744 | |||||
| clock jitter | - | 0.002 | 14.742 | |||||
| DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/data_unpacker_FHD_RX_0/s_data_pack[390]:D | Library setup time | ADLIB:SLE | - | 0.000 | 14.742 | |||
| data required time | 14.742 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[4]:ALn | 5.480 | 7.526 | 6.981 | 14.507 | 0.196 | 5.940 | 0.264 | slow_lv_ht |
| Path 2 | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[3]:ALn | 5.480 | 7.526 | 6.981 | 14.507 | 0.196 | 5.940 | 0.264 | slow_lv_ht |
| Path 3 | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[2]:ALn | 5.480 | 7.526 | 6.981 | 14.507 | 0.196 | 5.940 | 0.264 | slow_lv_ht |
| Path 4 | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[1]:ALn | 5.480 | 7.526 | 6.981 | 14.507 | 0.196 | 5.940 | 0.264 | slow_lv_ht |
| Path 5 | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[0]:ALn | 5.480 | 7.526 | 6.981 | 14.507 | 0.196 | 5.940 | 0.264 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | ||||||||
| To: DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[4]:ALn | ||||||||
| data required time | 14.507 | |||||||
| data arrival time | - | 6.981 | ||||||
| slack | 7.526 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB7:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.868 | 0.868 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB7:Y | cell | ADLIB:RGB | + | 0.059 | 0.927 | 16 | f | |
| DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB7_rgb_net_1 | + | 0.574 | 1.501 | r | ||
| DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz/CORERESET_PF_C0_0/dff_15:Q | cell | ADLIB:SLE | + | 0.201 | 1.702 | 127 | r | |
| DDR4_RD_WR_inst_0/AND2_0:B | net | DDR4_RD_WR_inst_0/CORERESET_PF_148p5MHz_CORERESET_PF_C0_0_dff | + | 1.761 | 3.463 | r | ||
| DDR4_RD_WR_inst_0/AND2_0:Y | cell | ADLIB:CFG2 | + | 0.053 | 3.516 | 171 | r | |
| DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[4]:ALn | net | DDR4_RD_WR_inst_0/AND2_0_Y | + | 3.465 | 6.981 | r | ||
| data arrival time | 6.981 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0/TX_CLK_R | Clock Constraint | 13.468 | 13.468 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R | Clock source | + | 0.000 | 13.468 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB0:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_tx_rclkint_input_net | + | 0.646 | 14.114 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB0:Y | cell | ADLIB:RGB | + | 0.052 | 14.166 | 263 | f | |
| DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[4]:CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_TX_rclkint/U0_RGB0_rgb_net_1 | + | 0.504 | 14.670 | r | ||
| clock reconvergence pessimism | + | 0.035 | 14.705 | |||||
| clock jitter | - | 0.002 | 14.703 | |||||
| DDR4_RD_WR_inst_0/Display_Controller_Camera/Display_Controller_C0_0/DC_Native_FORMAT.Display_Controller_Native_INST/s_sync_counter[4]:ALn | Library recovery time | ADLIB:SLE | - | 0.196 | 14.507 | |||
| data required time | 14.507 | |||||||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[1] | 2.826 | 9.672 | 4.255 | 13.927 | 0.892 | 3.796 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[0] | 2.904 | 9.684 | 4.333 | 14.017 | 0.802 | 3.784 | slow_lv_lt |
| Path 3 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[2] | 2.788 | 9.702 | 4.217 | 13.919 | 0.900 | 3.766 | slow_lv_lt |
| Path 4 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[4] | 2.782 | 9.714 | 4.211 | 13.925 | 0.894 | 3.754 | slow_lv_lt |
| Path 5 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[3] | 2.733 | 9.759 | 4.162 | 13.921 | 0.898 | 3.709 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | ||||||||
| To: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[1] | ||||||||
| data required time | 13.927 | |||||||
| data arrival time | - | 4.255 | ||||||
| slack | 9.672 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_TX_rclkint:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_tx_rclkint_input_net | + | 0.669 | 0.669 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.060 | 0.729 | 31 | f | |
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0_LANE1_TX_CLK_R | + | 0.700 | 1.429 | r | ||
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_b/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT[1] | cell | ADLIB:RAM1K20_IP | + | 2.177 | 3.606 | 1 | r | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[1] | net | DDR4_RD_WR_inst_0/HDMI_TX_C0_0_TMDS_B_O[1] | + | 0.649 | 4.255 | r | ||
| data arrival time | 4.255 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1/TX_CLK_R | Clock Constraint | 13.468 | 13.468 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_CLK_R | Clock source | + | 0.000 | 13.468 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_TX_rclkint:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_tx_rclkint_input_net | + | 0.607 | 14.075 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.053 | 14.128 | 31 | f | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_FWF_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0_LANE1_TX_CLK_R | + | 0.612 | 14.740 | r | ||
| clock reconvergence pessimism | + | 0.079 | 14.819 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_DATA[1] | Library setup time | ADLIB:XCVR_PMA | - | 0.892 | 13.927 | |||
| data required time | 13.927 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[1] | 3.179 | 9.332 | 4.629 | 13.961 | 0.858 | 4.136 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[4] | 3.200 | 9.342 | 4.650 | 13.992 | 0.827 | 4.126 | slow_lv_lt |
| Path 3 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[0] | 3.196 | 9.345 | 4.646 | 13.991 | 0.828 | 4.123 | slow_lv_lt |
| Path 4 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[2] | 3.140 | 9.429 | 4.590 | 14.019 | 0.800 | 4.039 | slow_lv_lt |
| Path 5 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[3] | 3.103 | 9.435 | 4.553 | 13.988 | 0.831 | 4.033 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | ||||||||
| To: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[1] | ||||||||
| data required time | 13.961 | |||||||
| data arrival time | - | 4.629 | ||||||
| slack | 9.332 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_TX_rclkint:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_tx_rclkint_input_net | + | 0.681 | 0.681 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_TX_rclkint:Y | cell | ADLIB:RGB | + | 0.060 | 0.741 | 14 | f | |
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0_LANE2_TX_CLK_R | + | 0.709 | 1.450 | r | ||
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_g/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT[1] | cell | ADLIB:RAM1K20_IP | + | 2.177 | 3.627 | 1 | r | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[1] | net | DDR4_RD_WR_inst_0/HDMI_TX_C0_0_TMDS_G_O[1] | + | 1.002 | 4.629 | r | ||
| data arrival time | 4.629 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2/TX_CLK_R | Clock Constraint | 13.468 | 13.468 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_CLK_R | Clock source | + | 0.000 | 13.468 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_TX_rclkint/U0_RGB0:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_tx_rclkint_input_net | + | 0.617 | 14.085 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_TX_rclkint/U0_RGB0:Y | cell | ADLIB:RGB | + | 0.053 | 14.138 | 17 | f | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_FWF_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_TX_rclkint/U0_RGB0_rgb_net_1 | + | 0.647 | 14.785 | r | ||
| clock reconvergence pessimism | + | 0.034 | 14.819 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_DATA[1] | Library setup time | ADLIB:XCVR_PMA | - | 0.858 | 13.961 | |||
| data required time | 13.961 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
No Path
No Path
No Path
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[1] | 2.892 | 9.756 | 4.359 | 14.115 | 0.773 | 3.712 | slow_lv_lt |
| Path 2 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[0] | 2.832 | 9.764 | 4.299 | 14.063 | 0.825 | 3.704 | slow_lv_lt |
| Path 3 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[2] | 2.796 | 9.789 | 4.263 | 14.052 | 0.836 | 3.679 | slow_lv_lt |
| Path 4 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[6] | 2.726 | 9.828 | 4.193 | 14.021 | 0.867 | 3.640 | slow_lv_lt |
| Path 5 | DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[3] | 2.710 | 9.856 | 4.177 | 14.033 | 0.855 | 3.612 | slow_lv_lt |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | ||||||||
| To: DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[1] | ||||||||
| data required time | 14.115 | |||||||
| data arrival time | - | 4.359 | ||||||
| slack | 9.756 | |||||||
| Data arrival time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R | 0.000 | 0.000 | ||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_CLK_R | Clock source | + | 0.000 | 0.000 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_tx_rclkint_input_net | + | 0.707 | 0.707 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0:Y | cell | ADLIB:RGB | + | 0.060 | 0.767 | 29 | f | |
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0_rgb_net_1 | + | 0.700 | 1.467 | r | ||
| DDR4_RD_WR_inst_0/HDMI_TX_C0_0/HDMI_TX_C0_0/HDMI_TX_Native_FORMAT.HDMI_TX_Native_INST/tx_fifo_top_inst/video_fifo_r/ram2port_hdmi_tx_inst/ram_ram_0_0/INST_RAM1K20_IP:A_DOUT[1] | cell | ADLIB:RAM1K20_IP | + | 2.301 | 3.768 | 1 | f | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[1] | net | DDR4_RD_WR_inst_0/HDMI_TX_C0_0_TMDS_R_O[1] | + | 0.591 | 4.359 | f | ||
| data arrival time | 4.359 | |||||||
| Data required time calculation | ||||||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3/TX_CLK_R | Clock Constraint | 13.468 | 13.468 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_CLK_R | Clock source | + | 0.000 | 13.468 | r | |||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0:A | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_tx_rclkint_input_net | + | 0.641 | 14.109 | r | ||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0:Y | cell | ADLIB:RGB | + | 0.053 | 14.162 | 29 | f | |
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_FWF_CLK | net | DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_TX_rclkint/U0_RGB0_rgb_net_1 | + | 0.630 | 14.792 | r | ||
| clock reconvergence pessimism | + | 0.096 | 14.888 | |||||
| DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_DATA[1] | Library setup time | ADLIB:XCVR_PMA | - | 0.773 | 14.115 | |||
| data required time | 14.115 | |||||||
| Operating Conditions | slow_lv_lt |
No Path
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Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin CLOCKS_AND_RESETS_inst_0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_0/I_IO:PAD_P
No Path
No Path
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No Path
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No Path