
// Begin - Internal PLL (used in design) Reset Assertion

// PMA_CMN_TXPLL_CTRL_TXPLL_BWSEL( QUADPLL_GPSS2_I )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xE60010

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1110008


// End   - Internal PLL (used in design) Reset Assertion

// Begin - SOFT reset assertion...

//       - (GPSS2 Quad)...

// PMA_CMN_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1110000


// PCSCMN_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_2 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_2 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_1 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_1 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_3 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_3 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x103

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108000


// End   - SOFT reset assertion.

// Begin - Deserializer Reset Assertion

// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110104C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110404C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110204C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110804C


// End   - Deserializer Reset Assertion

// Begin - Serializer Reset Assertion

// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x6

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x6

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x6

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x6

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108078


// End   - Serializer Reset Assertion

// Begin - Disable Fabric Resets 

// PCS_LRST_OPT Reset Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10106C


// PCS_LRST_OPT Reset Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10406C


// PCS_LRST_OPT Reset Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10206C


// PCS_LRST_OPT Reset Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10806C


// End   - Disable Fabric Resets 

// Wait Instruction - 1 uSecs was not added.


// Begin - Bypass enable for output driver

// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x10000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110107C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x10000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110407C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x10000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110207C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x10000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110807C


// End   - Bypass enable for output driver
// 62 instructions related to PCIe / PLL but PCIE_INIT_DONE is not asserted.

//
// UIC commands for SERDES (GPSS Quad) instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1
//    10 registers need to be updated.

// 1. PCS_L64_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x12

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101010

// 2. PCS_LCLK_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x50E11

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101058

// 3. PCS_LCLK_R1
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xF0000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10105C

// 4. PCS_LNTV_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x121E

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101050

// 5. PCS_LOVR_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x88

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101008

// 6. PCS_LPIP_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x58

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10100C

// 7. PCS_LRST_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x404

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101068

// 8. PMA_DES_PKDET
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xAD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101034

// 9. PMA_SERDES_RTL_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11010C0

// 10. PMA_SER_DRV_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110109C

// Begin - PMA register settings from good defaults data for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1


// 1. PMA_SER_DRV_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110109C


// 2. PMA_SER_DRV_CTRL_M0 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B240A

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11010A4


// 3. PMA_SER_DRV_CTRL_M2 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B0203

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11010AC


// 4. PMA_SER_DRV_CTRL_M3 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3B1B14

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11010B0


// 5. PMA_SER_DRV_CTRL_SEL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11010A0


// 6. PMA_SER_DRV_DATA_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101098


// 7. PMA_SER_TERM_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x7300

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101090


// End   - PMA register settings from good defaults data.

// Begin - PMA register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1

// End   - PMA register settings from override file.


//
// UIC commands for SERDES (GPSS Quad) instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3
//    10 registers need to be updated.

// 1. PCS_L64_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x12

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104010

// 2. PCS_LCLK_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x50E11

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104058

// 3. PCS_LCLK_R1
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xF0000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10405C

// 4. PCS_LNTV_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x121E

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104050

// 5. PCS_LOVR_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x88

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104008

// 6. PCS_LPIP_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x58

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10400C

// 7. PCS_LRST_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x404

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104068

// 8. PMA_DES_PKDET
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xAD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104034

// 9. PMA_SERDES_RTL_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11040C0

// 10. PMA_SER_DRV_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110409C

// Begin - PMA register settings from good defaults data for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3


// 1. PMA_SER_DRV_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110409C


// 2. PMA_SER_DRV_CTRL_M0 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B240A

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11040A4


// 3. PMA_SER_DRV_CTRL_M2 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B0203

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11040AC


// 4. PMA_SER_DRV_CTRL_M3 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3B1B14

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11040B0


// 5. PMA_SER_DRV_CTRL_SEL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11040A0


// 6. PMA_SER_DRV_DATA_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104098


// 7. PMA_SER_TERM_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x7300

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104090


// End   - PMA register settings from good defaults data.

// Begin - PMA register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3

// End   - PMA register settings from override file.


//
// UIC commands for SERDES (GPSS Quad) instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2
//    10 registers need to be updated.

// 1. PCS_L64_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x12

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102010

// 2. PCS_LCLK_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x50E11

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102058

// 3. PCS_LCLK_R1
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xF0000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10205C

// 4. PCS_LNTV_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x121E

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102050

// 5. PCS_LOVR_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x88

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102008

// 6. PCS_LPIP_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x58

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10200C

// 7. PCS_LRST_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x404

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102068

// 8. PMA_DES_PKDET
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xAD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102034

// 9. PMA_SERDES_RTL_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11020C0

// 10. PMA_SER_DRV_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110209C

// Begin - PMA register settings from good defaults data for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2


// 1. PMA_SER_DRV_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110209C


// 2. PMA_SER_DRV_CTRL_M0 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B240A

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11020A4


// 3. PMA_SER_DRV_CTRL_M2 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B0203

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11020AC


// 4. PMA_SER_DRV_CTRL_M3 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3B1B14

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11020B0


// 5. PMA_SER_DRV_CTRL_SEL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11020A0


// 6. PMA_SER_DRV_DATA_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102098


// 7. PMA_SER_TERM_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x7300

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102090


// End   - PMA register settings from good defaults data.

// Begin - PMA register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2

// End   - PMA register settings from override file.


//
// UIC commands for SERDES (GPSS Quad) instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0
//    10 registers need to be updated.

// 1. PCS_L64_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x12

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108010

// 2. PCS_LCLK_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x50E11

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108058

// 3. PCS_LCLK_R1
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xF0000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10805C

// 4. PCS_LNTV_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x121E

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108050

// 5. PCS_LOVR_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x88

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108008

// 6. PCS_LPIP_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x58

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10800C

// 7. PCS_LRST_R0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x404

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108068

// 8. PMA_DES_PKDET
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xAD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108034

// 9. PMA_SERDES_RTL_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11080C0

// 10. PMA_SER_DRV_CTRL
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110809C

// Begin - PMA register settings from good defaults data for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0


// 1. PMA_SER_DRV_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x11000000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110809C


// 2. PMA_SER_DRV_CTRL_M0 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B240A

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11080A4


// 3. PMA_SER_DRV_CTRL_M2 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1B0203

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11080AC


// 4. PMA_SER_DRV_CTRL_M3 set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3B1B14

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11080B0


// 5. PMA_SER_DRV_CTRL_SEL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xD

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x11080A0


// 6. PMA_SER_DRV_DATA_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108098


// 7. PMA_SER_TERM_CTRL set from UIC Good Default.
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x7300

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108090


// End   - PMA register settings from good defaults data.

// Begin - PMA register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0

// End   - PMA register settings from override file.

BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xF00000

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x2110190

// Begin - PCS and other register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1

// End   - PCS and other register settings from override file.

// Begin - PCS and other register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3

// End   - PCS and other register settings from override file.

// Begin - PCS and other register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2

// End   - PCS and other register settings from override file.

// Begin - PCS and other register settings from override file for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0

// End   - PCS and other register settings from override file.


// Begin - PMA SOFT reset de-assertion...

//       - (GPSS2)

// PMA_CMN_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1110000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_2 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_1 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102000


// PMA_SOFT_RESET_PERIPH( LANE_GPSS2_3 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108000


// End   - PMA SOFT reset de-assertion.

// Begin - PCS SOFT reset de-assertion...

//       - (GPSS2)

// PCSCMN_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_0 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_2 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_1 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102000


// PCS_SOFT_RESET_PERIPH( LANE_GPSS2_3 )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108000


// End   - PCS SOFT reset de-assertion.

// Begin - Enable Input Buffers 

// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110104C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110404C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110204C


// PMA_DES_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3F

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110804C


// End   - Enable Input Buffers 

// Begin - Internal PLL (used in design) PowerUp

// PMA_CMN_TXPLL_CTRL_TXPLL_BWSEL( QUADPLL_GPSS2_I )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0xE00010

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1110008


// End   - Internal PLL (used in design) PowerUp

// Begin - Deserializer PowerUp

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1

//    Transceiver in 'Tx only' mode - Deserializer will not be PoweredUp

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3

//    Transceiver in 'Tx only' mode - Deserializer will not be PoweredUp

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2

//    Transceiver in 'Tx only' mode - Deserializer will not be PoweredUp

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0

//    Transceiver in 'Tx only' mode - Deserializer will not be PoweredUp

// End   - Deserializer PowerUp

// Begin - Serializer PowerUp

// PMA_SER_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101078


// PMA_SER_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104078


// PMA_SER_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102078


// PMA_SER_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x2

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108078


// End   - Serializer PowerUp

// Wait Instruction - 1 uSecs was not added.


// Begin - Internal PLL (used in design) Reset De-Assertion

// PMA_CMN_TXPLL_CTRL_TXPLL_BWSEL( QUADPLL_GPSS2_I )
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x800010

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1110008


// End   - Internal PLL (used in design) Reset De-Assertion

// Begin - Deserializer Reset De-Assertion

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1

//    Transceiver in 'Tx only' mode - Deserializer will not be De-Asserted

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3

//    Transceiver in 'Tx only' mode - Deserializer will not be De-Asserted

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2

//    Transceiver in 'Tx only' mode - Deserializer will not be De-Asserted

// PMA_DES_RSTPD for instance DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0

//    Transceiver in 'Tx only' mode - Deserializer will not be De-Asserted

// End   - Deserializer Reset De-Assertion

// Begin - Serializer Reset De-Assertion

// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1101078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1104078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1102078


// PMA_SER_RSTPD
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x1108078


// End   - Serializer Reset De-Assertion

// Begin - Enable Fabric Resets

// PCS_PMA_CTRL_R0 Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3030347

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x101088


// PCS_LRST_OPT Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10106C


// PCS_PMA_CTRL_R0 Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3030347

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x104088


// PCS_LRST_OPT Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10406C


// PCS_PMA_CTRL_R0 Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3030347

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x102088


// PCS_LRST_OPT Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10206C


// PCS_PMA_CTRL_R0 Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x3030347

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x108088


// PCS_LRST_OPT Reset De-Assertion
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x1

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x10806C


// End   - Enable Fabric Resets

// Wait Instruction - 1 uSecs was not added.


// Begin - Bypass disable for output driver

// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110107C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110407C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110207C


// DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0  PMA_SER_DRV_BYP
BITWISE_LOAD DEST_ACC_ID-0x2
		DATA-0x0

STORE BUS_ID-0x0 XFER_SIZE-0x2 ACC_ID-0x2
		ADDRESS-0x110807C


// End   - Bypass disable for output driver
// XCVR_INIT_DONE.
BITWISE_LOAD DEST_ACC_ID-0x0
		DATA-0x11

STORE BUS_ID-0x2 XFER_SIZE-0x2 ACC_ID-0x0
		ADDRESS-0x0


// 276 instructions before XCVR_INIT_DONE.

// Wait Instruction - 2 uSecs
WAIT MICRO_SECONDS-0x0000002

END
