Global Net Report

Microchip Technology Inc. - Microchip Libero Software Release v2022.2 (Version 2022.2.0.10)

Date: Mon Nov 21 15:45:19 2022

Global Nets Information

From GB Location Net Name Fanout
1 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0 (1298, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y 4890
2 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0 (1297, 162) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_Y 3513
3 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0 (1298, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0_Y 3078
4 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0 (1309, 163) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_gbs_1 1696
5 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0 (1299, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y 1190
6 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0 (1307, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_Y 1016
7 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_RNIVO8D/U0 (1297, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_RNIVO8D/U0_Y 851
8 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_GB0 (1313, 163) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_gbs_1 536
9 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0 (1300, 162) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_Y 103
10 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_GB0 (1311, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_gbs_1 85
11 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_GB0 (1319, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_gbs_1 83
12 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_GB0 (1310, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_gbs_1 17
13 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_GB0 (1312, 163) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_gbs_1 17
14 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0 (1301, 163) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_Y 11
15 CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_1/U0 (1301, 162) CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_1/U0_Y 1

I/O to GB Connections

Port Name Pin Number I/O Function From From Location To Net Name Net Type Fanout
1 CAM1_RX_CLK_N M14 GPIO167PB7/CLKIN_W_0/CCC_SW_CLKIN_W_0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0/U_IOPADP:Y (0, 55) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0_Y HARDWIRED 2
2 CAM1_RX_CLK_N M14 GPIO167PB7/CLKIN_W_0/CCC_SW_CLKIN_W_0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0/U_IOPADP:Y (0, 55) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_GB0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0_Y HARDWIRED 2

Fabric to GB Connections

From From Location To Net Name Net Type Fanout
1 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0:Y (1319, 261) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_Y ROUTED 1
2 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:Q (1221, 184) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_Z ROUTED 2
3 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep:Q (1221, 175) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_RNIVO8D/U0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_Z ROUTED 1
4 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_GB_DEMOTE:Q (1411, 301) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_GB0 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_GB_DEMOTE_net ROUTED 2
5 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep:Q (1221, 184) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_GB0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_Z ROUTED 2
6 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_GB_DEMOTE:Q (1411, 301) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_GB_DEMOTE_net ROUTED 2
7 CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0/PF_OSC_C0_0/I_OSC_2:CLK (655, 2) CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_1/U0 CLOCKS_AND_RESETS_inst_0/PF_OSC_C0_0_RCOSC_2MHZ_CLK_DIV HARDWIRED 1

CCC to GB Connections

From From Location To Net Name Net Type Fanout
1 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 (2460, 377) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 HARDWIRED 1
2 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:OUT0 (2460, 377) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0_clkint_0 HARDWIRED 1
3 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 (2461, 5) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 HARDWIRED 1
4 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 (2460, 5) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 HARDWIRED 1
5 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:OUT0 (2461, 5) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_GB0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0_clkint_0 HARDWIRED 1
6 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 (2460, 5) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_GB0 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 HARDWIRED 1

CCC Input Connections

Port Name Pin Number I/O Function From From Location To CCC Location Net Name Net Type Fanout
1 CAM1_RX_CLK_N M14 GPIO167PB7/CLKIN_W_0/CCC_SW_CLKIN_W_0 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0/U_IOPADP:Y (0, 55) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0:REF_CLK_0 (2461, 5) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLK_0_Y ROUTED 2
2 - - - CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:OUT0 (2460, 5) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0:REF_CLK_0 (2460, 377) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0_clkint_0 ROUTED 1
3 - - - CLOCKS_AND_RESETS_inst_0/PF_XCVR_REF_CLK_C0_0/PF_XCVR_REF_CLK_C0_0/I_IO:Y[0] (2467, 371) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0:REF_CLK_0 (2460, 5) CLOCKS_AND_RESETS_inst_0/PF_XCVR_REF_CLK_C0_0_FAB_REF_CLK ROUTED 1

Local Nets to RGB Connections

From From Location Net Name Net Type Fanout RGB Location Local Fanout
1 DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0:TX_CLK_R (2460, 371) DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0_tx_rclkint_input_net HARDWIRED 1004 (1888, 259) 16
(1888, 286) 8
(1888, 313) 66
(1888, 340) 112
(1888, 367) 28
(1894, 286) 11
(1894, 313) 95
(1894, 340) 404
(1894, 367) 264
2 DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1:TX_CLK_R (2460, 317) DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1_tx_rclkint_input_net HARDWIRED 32 (1891, 313) 32
3 DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3:TX_CLK_R (2461, 344) DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3_tx_rclkint_input_net HARDWIRED 32 (1891, 340) 30
(1891, 367) 2
4 DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2:TX_CLK_R (2460, 344) DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2_tx_rclkint_input_net HARDWIRED 32 (1895, 341) 18
(1895, 368) 14

Global Nets to RGB Connections

From From Location Net Name Fanout RGB Location Local Fanout
1 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0 (1298, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_Y 4890 1 (721, 41) 222
2 (721, 68) 1811
3 (721, 95) 1260
4 (721, 122) 1467
5 (721, 149) 113
6 (727, 179) 17
2 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0 (1297, 162) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_Y 3513 1 (729, 231) 3
2 (729, 258) 809
3 (729, 285) 1605
4 (729, 312) 1058
5 (729, 339) 38
3 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0 (1298, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/AND2_0_RNIPAQ7/U0_Y 3078 1 (722, 41) 31
2 (722, 68) 1339
3 (722, 95) 1099
4 (722, 122) 609
4 CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_GB0 (1309, 163) CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/clkint_0/U0_gbs_1 1696 1 (1888, 258) 1
2 (1888, 285) 82
3 (1888, 312) 651
4 (1888, 339) 729
5 (1888, 366) 78
6 (1891, 366) 13
7 (1894, 285) 31
8 (1894, 312) 39
9 (1894, 339) 72
5 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0 (1299, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_Y 1190 1 (724, 122) 3
2 (724, 149) 83
3 (724, 179) 3
4 (730, 179) 17
5 (730, 206) 1
6 (730, 233) 284
7 (730, 260) 427
8 (730, 287) 345
9 (730, 314) 27
6 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0 (1307, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_Y 1016 1 (731, 232) 272
2 (731, 259) 417
3 (731, 286) 300
4 (731, 313) 27
7 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_RNIVO8D/U0 (1297, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C2_0/CORERESET_PF_C2_0/dff_15_rep_RNIVO8D/U0_Y 851 1 (724, 93) 161
2 (724, 120) 523
3 (724, 147) 150
4 (724, 177) 3
5 (730, 204) 1
6 (730, 231) 9
7 (730, 258) 4
8 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_GB0 (1313, 163) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_gbs_1 536 1 (1885, 259) 1
2 (1885, 340) 98
3 (1889, 287) 1
4 (1889, 314) 53
5 (1892, 341) 277
6 (1894, 366) 36
7 (1895, 314) 70
9 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0 (1300, 162) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_Y 103 1 (726, 232) 1
2 (726, 259) 56
3 (726, 286) 46
10 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_GB0 (1311, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/clkint_0/U0_gbs_1 85 1 (1886, 287) 38
2 (1889, 260) 47
11 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_GB0 (1319, 162) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/CORERESET_PF_C1_0/CORERESET_PF_C1_0/dff_15_rep_RNITC8F/U0_gbs_1 83 1 (1889, 259) 46
2 (1889, 286) 37
12 DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_GB0 (1310, 163) DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/CLKINT_0/U0_gbs_1 17 1 (1886, 260) 16
2 (1892, 14) 1
13 CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_GB0 (1312, 163) CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/clkint_0/U0_gbs_1 17 1 (1885, 286) 11
2 (1885, 313) 5
3 (1892, 368) 1
14 CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0 (1301, 163) CLOCKS_AND_RESETS_inst_0/CORERESET_CLK_200MHz/CORERESET_PF_C4_0/dff_15_rep_RNI2N2C/U0_Y 11 1 (730, 232) 3
2 (730, 259) 3
3 (730, 286) 5
15 CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_1/U0 (1301, 162) CLOCKS_AND_RESETS_inst_0/PF_CLK_DIV_C0_0/PF_CLK_DIV_C0_0/I_CD_1/U0_Y 1 (729, 232) 1

Clock Signals Summary

The number of clock signals through H-Chip Global resources 8
The number of clock signals through Row Global resources 50
The number of clock signals through Sector Global resources 223
The number of clock signals through Cluster Global resources 1840

Warning: Local Clock Nets

The following clocks are routed using regular routing resources instead of dedicated global resources. Clocks using regular routing have less predictable amounts of clock jitter versus the dedicated global resources. Microchip recommends using clock input and clock generation paths that maximize the usage of dedicated global routing resources, as well as promoting these signals below to dedicated global resources. Refer to the PolarFire and PolarFire SoC Clocking Resources User Guide for more information

From Driving Net To
1 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_8:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_8_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_21_rs:CLK
2 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_index_i_1:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_index_i_1_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_1_rs:CLK
3 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_14:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_14_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_19_rs:CLK
4 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_10:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_10_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_27_rs:CLK
5 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_9:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_9_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_6_rs:CLK
6 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_15:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_15_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_9_rs:CLK
7 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_12:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_12_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_3_rs:CLK
8 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_11:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_11_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_16_rs:CLK
9 DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_13:Y DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_frame_start_addr_i_13_Z DDR4_RD_WR_inst_0/DDR_Read_LPDDR4_0/DDR_read_controller_FHD_HDMI_RX_0/un1_reset_i_8_rs:CLK