Configuration Report for SERDES XCVR, PCIe, CCC and Transmit PLL

Microchip Technology Inc. - Microchip Libero Software Release v2022.2 (Version 2022.2.0.10)

Family: PolarFireSoC

Die: MPFS250T_ES

Package: FCG1152

Date: Mon Nov 21 15:50:12 2022

Report path: D:\Delme\SEV_PFSoC_OpenVX\designer\SEV_PFSoC_OpenVX\Design_Initialization_Data_Report.xml

Power Up to Functional Timing (PUFT)

INFO: The PUFT timing numbers reflect the time elapsed between the assertion of FABRIC_POR_N signal and the assertion of each signal in the below table.

Signal Name	PUFT (micro secs)
XCVR_INIT_DONE	579.600
DEVICE_INIT_DONE	598.800

Crypto Selection

Function	Enabled
Crypto	Yes

Q0_TXPLL0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2044000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x2044004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x2044008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x204400C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x2044010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x2044014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x2044018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x204401C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x2044020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x2044024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x2044028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x204402C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x2044030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x2044034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x2044038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x204403C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x2044040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_TXPLL1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2048000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x2048004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x2048008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x204800C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x2048010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x2048014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x2048018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x204801C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x2048020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x2048024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x2048028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x204802C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x2048030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x2048034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x2048038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x204803C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x2048040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PMA_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1042000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1042004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1042008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x104200C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1042010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1042014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1042018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1042020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1042024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1042028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x104202C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1042030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1042034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1042038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x104203C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1042040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1042044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1042048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x104204C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1042050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1042054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1042058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x104205C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1042070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1042074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1042078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x104207C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1042080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1042084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1042088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x104208C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1042090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1042094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1042098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x104209C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10420A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10420A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10420A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10420AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10420B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10420B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10420B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10420C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10420D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10420D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10420D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10420DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10420E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10420E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10420E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10420EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10420F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10420F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10420F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10420FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1042100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PCS_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x42000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x42004	0x00000000	0x00000000	No	1
LOVR_R0	0x42008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x4200C	0x0000005D	0x00000058	Yes	1
L64_R0	0x42010	0x01400000	0x01400000	No	N/A
L64_R1	0x42014	0x00000001	0x00000001	No	N/A
L64_R2	0x42018	0x00000000	0x00000000	No	N/A
L64_R3	0x4201C	0x00000000	0x00000000	No	N/A
L64_R4	0x42020	0x00000000	0x00000000	No	N/A
L64_R5	0x42024	0x00000000	0x00000000	No	N/A
L64_R6	0x42028	0x00000000	0x00000000	No	N/A
L64_R7	0x4202C	0x00000000	0x00000000	No	N/A
L64_R8	0x42030	0x00000000	0x00000000	No	N/A
L64_R9	0x42034	0x00000000	0x00000000	No	N/A
L64_R10	0x42038	0x00000000	0x00000000	No	N/A
L8_R0	0x42040	0x00000000	0x00000000	No	1
LNTV_R0	0x42050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x42058	0x00000000	0x00000000	No	1
LCLK_R1	0x4205C	0x03000000	0x00000000	Yes	1
LRST_R0	0x42068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x4206C	0x00000000	0x00000000	No	N/A
OOB_R0	0x42078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x4207C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x42080	0x00000000	0x00000000	No	N/A
OOB_R3	0x42084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x42088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x4208C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x42090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x42094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PCSCMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x50000	0x00000000	0x00000000	No	1
GSSCLK_CTRL	0x50004	0x00000000	0x00000000	No	1
QRST_R0	0x50008	0x00000000	0x00000000	No	1
QDBG_R0	0x5000C	0x00001000	0x00000000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PMA_CMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1050000	0x00000000	0x00000000	No	1
TXPLL_CLKBUF	0x1050004	0x00000000	0x00000000	No	1
TXPLL_CTRL	0x1050008	0x00E60010	0x00E60010	No	1
TXPLL_CLK_SEL	0x105000C	0x3F3F1C00	0x3F3F0000	Yes	1
TXPLL_DIV_1	0x1050010	0x00190019	0x00000000	Yes	1
TXPLL_DIV_2	0x1050014	0x01000001	0x00000000	Yes	1
TXPLL_JA_1	0x1050018	0x00640064	0x00640064	No	N/A
TXPLL_JA_2	0x105001C	0x00000064	0x00000064	No	N/A
TXPLL_JA_3	0x1050020	0x00640064	0x00640064	No	N/A
TXPLL_JA_4	0x1050024	0x01010001	0x01010001	No	N/A
TXPLL_JA_5	0x1050028	0x01010101	0x01010101	No	N/A
TXPLL_JA_6	0x105002C	0x01010101	0x01010101	No	N/A
TXPLL_JA_7	0x1050030	0x07000001	0x07000001	No	N/A
TXPLL_JA_8	0x1050034	0x00000000	0x00000000	No	N/A
TXPLL_JA_9	0x1050038	0x00180014	0x00180014	No	N/A
TXPLL_JA_10	0x105003C	0x00000000	0x00000000	No	N/A
TXPLL_JA_RST	0x1050040	0x00000055	0x00000055	No	N/A
SERDES_SSMOD	0x1050044	0x007F0102	0x007F0102	No	N/A
SERDES_RTERM	0x1050050	0x000D0703	0x000D0703	No	N/A
SERDES_RTT	0x1050054	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_MAIN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2050000	0x00000000	0x00000000	No	1
OVRLY	0x2050004	0x00000101	0x00000001	Yes	1
MAJOR	0x2050008	0x0000000B	0x0000000A	Yes	1
INT_PIPE_CLK_CTRL	0x205000C	0x00000000	0x030A0000	Yes	1
EXT_PIPE_CLK_CTRL	0x2050010	0x00000000	0x00000000	No	1
CLK_CTRL	0x2050014	0x00000000	0x00000000	No	1
QMUX_R0	0x2050018	0x00070031	0x00000031	Yes	1
DLL_CTRL0	0x2050100	0x8800000F	0x00000000	Yes	1
DLL_CTRL1	0x2050104	0x00000000	0x00000000	No	1
DLL_STAT0	0x2050108	0x00001801	0x00000801	Yes	1
DLL_STAT1	0x205010C	0x00000000	0x00000000	No	N/A
DLL_STAT2	0x2050110	0x00000000	0x00000000	No	N/A
TEST_DLL	0x2050118	0x00000000	0x00000000	No	N/A
SPARE	0x2050190	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PMA_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1041000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1041004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1041008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x104100C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1041010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1041014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1041018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1041020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1041024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1041028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x104102C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1041030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1041034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1041038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x104103C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1041040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1041044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1041048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x104104C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1041050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1041054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1041058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x104105C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1041070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1041074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1041078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x104107C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1041080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1041084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1041088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x104108C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1041090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1041094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1041098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x104109C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10410A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10410A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10410A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10410AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10410B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10410B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10410B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10410C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10410D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10410D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10410D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10410DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10410E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10410E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10410E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10410EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10410F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10410F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10410F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10410FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1041100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PCS_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x41000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x41004	0x00000000	0x00000000	No	1
LOVR_R0	0x41008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x4100C	0x0000005D	0x00000058	Yes	1
L64_R0	0x41010	0x01400000	0x01400000	No	N/A
L64_R1	0x41014	0x00000001	0x00000001	No	N/A
L64_R2	0x41018	0x00000000	0x00000000	No	N/A
L64_R3	0x4101C	0x00000000	0x00000000	No	N/A
L64_R4	0x41020	0x00000000	0x00000000	No	N/A
L64_R5	0x41024	0x00000000	0x00000000	No	N/A
L64_R6	0x41028	0x00000000	0x00000000	No	N/A
L64_R7	0x4102C	0x00000000	0x00000000	No	N/A
L64_R8	0x41030	0x00000000	0x00000000	No	N/A
L64_R9	0x41034	0x00000000	0x00000000	No	N/A
L64_R10	0x41038	0x00000000	0x00000000	No	N/A
L8_R0	0x41040	0x00000000	0x00000000	No	1
LNTV_R0	0x41050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x41058	0x00000000	0x00000000	No	1
LCLK_R1	0x4105C	0x03000000	0x00000000	Yes	1
LRST_R0	0x41068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x4106C	0x00000000	0x00000000	No	N/A
OOB_R0	0x41078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x4107C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x41080	0x00000000	0x00000000	No	N/A
OOB_R3	0x41084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x41088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x4108C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x41090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x41094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PMA_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1044000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1044004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1044008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x104400C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1044010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1044014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1044018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1044020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1044024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1044028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x104402C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1044030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1044034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1044038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x104403C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1044040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1044044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1044048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x104404C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1044050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1044054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1044058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x104405C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1044070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1044074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1044078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x104407C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1044080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1044084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1044088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x104408C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1044090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1044094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1044098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x104409C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10440A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10440A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10440A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10440AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10440B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10440B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10440B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10440C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10440D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10440D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10440D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10440DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10440E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10440E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10440E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10440EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10440F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10440F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10440F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10440FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1044100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PCS_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x44000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x44004	0x00000000	0x00000000	No	1
LOVR_R0	0x44008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x4400C	0x0000005D	0x00000058	Yes	1
L64_R0	0x44010	0x01400000	0x01400000	No	N/A
L64_R1	0x44014	0x00000001	0x00000001	No	N/A
L64_R2	0x44018	0x00000000	0x00000000	No	N/A
L64_R3	0x4401C	0x00000000	0x00000000	No	N/A
L64_R4	0x44020	0x00000000	0x00000000	No	N/A
L64_R5	0x44024	0x00000000	0x00000000	No	N/A
L64_R6	0x44028	0x00000000	0x00000000	No	N/A
L64_R7	0x4402C	0x00000000	0x00000000	No	N/A
L64_R8	0x44030	0x00000000	0x00000000	No	N/A
L64_R9	0x44034	0x00000000	0x00000000	No	N/A
L64_R10	0x44038	0x00000000	0x00000000	No	N/A
L8_R0	0x44040	0x00000000	0x00000000	No	1
LNTV_R0	0x44050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x44058	0x00000000	0x00000000	No	1
LCLK_R1	0x4405C	0x03000000	0x00000000	Yes	1
LRST_R0	0x44068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x4406C	0x00000000	0x00000000	No	N/A
OOB_R0	0x44078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x4407C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x44080	0x00000000	0x00000000	No	N/A
OOB_R3	0x44084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x44088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x4408C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x44090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x44094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PMA_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1048000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1048004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1048008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x104800C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1048010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1048014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1048018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1048020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1048024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1048028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x104802C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1048030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1048034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1048038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x104803C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1048040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1048044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1048048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x104804C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1048050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1048054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1048058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x104805C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1048070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1048074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1048078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x104807C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1048080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1048084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1048088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x104808C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1048090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1048094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1048098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x104809C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10480A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10480A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10480A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10480AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10480B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10480B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10480B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10480C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10480D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10480D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10480D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10480DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10480E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10480E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10480E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10480EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10480F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10480F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10480F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10480FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1048100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q0_PCS_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x48000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x48004	0x00000000	0x00000000	No	1
LOVR_R0	0x48008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x4800C	0x0000005D	0x00000058	Yes	1
L64_R0	0x48010	0x01400000	0x01400000	No	N/A
L64_R1	0x48014	0x00000001	0x00000001	No	N/A
L64_R2	0x48018	0x00000000	0x00000000	No	N/A
L64_R3	0x4801C	0x00000000	0x00000000	No	N/A
L64_R4	0x48020	0x00000000	0x00000000	No	N/A
L64_R5	0x48024	0x00000000	0x00000000	No	N/A
L64_R6	0x48028	0x00000000	0x00000000	No	N/A
L64_R7	0x4802C	0x00000000	0x00000000	No	N/A
L64_R8	0x48030	0x00000000	0x00000000	No	N/A
L64_R9	0x48034	0x00000000	0x00000000	No	N/A
L64_R10	0x48038	0x00000000	0x00000000	No	N/A
L8_R0	0x48040	0x00000000	0x00000000	No	1
LNTV_R0	0x48050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x48058	0x00000000	0x00000000	No	1
LCLK_R1	0x4805C	0x03000000	0x00000000	Yes	1
LRST_R0	0x48068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x4806C	0x00000000	0x00000000	No	N/A
OOB_R0	0x48078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x4807C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x48080	0x00000000	0x00000000	No	N/A
OOB_R3	0x48084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x48088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x4808C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x48090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x48094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PCIE0_PCIE_CTRL (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x3006000	0x00000000	0x00000000	No	1
DEV_CONTROL	0x3006004	0x00019110	0x00000000	Yes	1
CLOCK_CONTROL	0x3006008	0x1FC00000	0x00000000	Yes	1
SOFT_RESET_DEBUG_INFO	0x3006010	0x00000000	0x00000000	No	N/A
SOFT_RESET_CTLR	0x3006014	0x00100002	0x00100002	No	N/A
SEC_ERROR_EVENT_CNT	0x3006020	0x00000000	0x00000000	No	N/A
DED_ERROR_EVENT_CNT	0x3006024	0x00000000	0x00000000	No	N/A
SEC_ERROR_INT	0x3006028	0x00000000	0x00000000	No	N/A
SEC_ERROR_INT_MASK	0x300602C	0x00001111	0x00001111	No	N/A
DED_ERROR_INT	0x3006030	0x00000000	0x00000000	No	N/A
DED_ERROR_INT_MASK	0x3006034	0x00001111	0x00001111	No	N/A
ECC_CONTROL	0x3006038	0x00000000	0x00000000	No	N/A
ECC_ERR_LOC	0x300603C	0x00000000	0x00000000	No	N/A
RAM_MARGIN_1	0x3006040	0x00000000	0x00000000	No	N/A
RAM_MARGIN_2	0x3006044	0x00000000	0x00000000	No	N/A
RAM_POWER_CONTROL	0x3006048	0x00000000	0x04040404	Yes	N/A
DEBUG_SEL	0x3006050	0x00000000	0x00000000	No	N/A
LTSSM_STATE	0x300605C	0x00000000	0x00000000	No	N/A
PHY_COMMON_INTERFACE	0x3006060	0x00000000	0x00000000	No	N/A
PL_TX_LANEIF_0	0x3006064	0x00000000	0x00000000	No	N/A
PL_RX_LANEIF_0	0x3006068	0x00000000	0x00000000	No	N/A
PL_WAKECLKREQ	0x300606C	0x00000000	0x00000000	No	N/A
PCICONF_PCI_IDS_OVERRIDE	0x3006080	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_31_0	0x3006084	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_63_32	0x3006088	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_95_64	0x300608C	0x00000000	0x00000000	No	1
PCIE_PEX_DEV_LINK_SPC2	0x30060A0	0x00000200	0x00000000	Yes	1
PCIE_PEX_SPC	0x30060A4	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG0	0x3006100	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG1	0x3006104	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG2	0x3006108	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG0	0x3006120	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG1	0x3006124	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG2	0x3006128	0x00000000	0x00000000	No	N/A
PCIE_BAR_01	0x3006140	0x00000000	0x00000000	No	N/A
PCIE_BAR_23	0x3006144	0x00000000	0x00000000	No	N/A
PCIE_BAR_45	0x3006148	0x00000000	0x00000000	No	N/A
PCIE_EVENT_INT	0x300614C	0x00000000	0x00070000	Yes	N/A
SPARE	0x3006150	0x00000000	0x00000000	No	N/A
PCIE_BAR_WIN	0x3006180	0x00000000	0x00000000	No	1
TEST_BUS_IN_31_0	0x3006C80	0x00000000	0x00000000	No	N/A
TEST_BUS_IN_63_32	0x3006C84	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PCIE0_PCIE_BRIDGE (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
BRIDGE_VER	0x3004000	0x02511154	0x02511154	No	N/A
BRIDGE_BUS	0x3004004	0x11885153	0x11885153	No	N/A
BRIDGE_IMPL_IF	0x3004008	0x0000032B	0x0000032B	No	N/A
PCIE_IF_CONF	0x3004010	0x11440170	0x11440170	No	N/A
PCIE_BASIC_CONF	0x3004014	0x03110307	0x03110307	No	N/A
PCIE_BASIC_STATUS	0x3004018	0x20000100	0x20000100	No	N/A
AXI_SLVL_CONF	0x3004024	0xBB002121	0xBB002121	No	N/A
AXI_MST0_CONF	0x3004030	0x11883442	0x11883442	No	N/A
AXI_SLV0_CONF	0x3004034	0x44443443	0x44443443	No	N/A
GEN_SETTINGS	0x3004080	0x00019300	0x00019300	No	N/A
PCIE_CFGCTRL	0x3004084	0x00000000	0x00000000	No	N/A
PCIE_PIPE_DW0	0x3004088	0x20000000	0x20000000	No	N/A
PCIE_PIPE_DW1	0x300408C	0x08000001	0x08000001	No	N/A
PCIE_VC_CRED_DW0	0x3004090	0x0100B818	0x0100B818	No	N/A
PCIE_VC_CRED_DW1	0x3004094	0x00000001	0x00000001	No	N/A
PCIE_PCI_IDS_DW0	0x3004098	0x11001556	0x11001556	No	N/A
PCIE_PCI_IDS_DW1	0x300409C	0xFF000001	0xFF000001	No	N/A
PCIE_PCI_IDS_DW2	0x30040A0	0x11001556	0x11001556	No	N/A
PCIE_PCI_LPM	0x30040A4	0xFE000000	0xFE000000	No	N/A
PCIE_PCI_IRQ_DW0	0x30040A8	0x80000054	0x80000054	No	N/A
PCIE_PCI_IRQ_DW1	0x30040AC	0x00000000	0x00000000	No	N/A
PCIE_PCI_IRQ_DW2	0x30040B0	0x00000000	0x00000000	No	N/A
PCIE_PCI_IOV_DW0	0x30040B4	0x0000000A	0x0000000A	No	N/A
PCIE_PCI_IOV_DW1	0x30040B8	0x00000000	0x00000000	No	N/A
PCIE_PEX_DEV	0x30040C0	0x00000001	0x00000001	No	N/A
PCIE_PEX_DEV2	0x30040C4	0x0000081F	0x0000081F	No	N/A
PCIE_PEX_LINK	0x30040C8	0x01001C00	0x01001C00	No	N/A
PCIE_PEX_SLOT	0x30040CC	0x0000007F	0x0000007F	No	N/A
PCIE_PEX_ROOT_VC	0x30040D0	0x00000001	0x00000001	No	N/A
PCIE_PEX_SPC	0x30040D4	0x80005000	0x80005000	No	N/A
PCIE_PEX_SPC2	0x30040D8	0x000C6006	0x000C6006	No	N/A
PCIE_PEX_NFTS	0x30040DC	0x00202020	0x00202020	No	N/A
PCIE_PEX_L1SS	0x30040E0	0x00280A1D	0x00280A1D	No	N/A
PCIE_BAR_01_DW0	0x30040E4	0xFFFFF00C	0xFFFFF00C	No	N/A
PCIE_BAR_01_DW1	0x30040E8	0xFFFFFFFF	0xFFFFFFFF	No	N/A
PCIE_BAR_23_DW0	0x30040EC	0xFFFFE00C	0xFFFFE00C	No	N/A
PCIE_BAR_23_DW1	0x30040F0	0xFFFFFFFF	0xFFFFFFFF	No	N/A
PCIE_BAR_45_DW0	0x30040F4	0x00000000	0x00000000	No	N/A
PCIE_BAR_45_DW1	0x30040F8	0x00000000	0x00000000	No	N/A
PCIE_BAR_WIN	0x30040FC	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW0	0x3004100	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW1	0x3004104	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW2	0x3004108	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW3	0x300410C	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW4	0x3004110	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW5	0x3004114	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW6	0x3004118	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW7	0x300411C	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW0	0x3004120	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW1	0x3004124	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW2	0x3004128	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW3	0x300412C	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW4	0x3004130	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW5	0x3004134	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW6	0x3004138	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW7	0x300413C	0x00000000	0x00000000	No	N/A
PCIE_CFGNUM	0x3004140	0x00000000	0x00000000	No	N/A
PM_CONF_DW0	0x3004174	0x00000000	0x00000000	No	N/A
PM_CONF_DW1	0x3004178	0x00000000	0x00000000	No	N/A
PM_CONF_DW2	0x300417C	0x00000000	0x00000000	No	N/A
IMASK_LOCAL	0x3004180	0x00000000	0x00000000	No	N/A
ISTATUS_LOCAL	0x3004184	0x00000000	0x00000000	No	N/A
IMASK_HOST	0x3004188	0x00000000	0x00000000	No	N/A
ISTATUS_HOST	0x300418C	0x00000000	0x00000000	No	N/A
IMSI_ADDR	0x3004190	0x00000190	0x00000190	No	N/A
ISTATUS_MSI	0x3004194	0x00000000	0x00000000	No	N/A
ICMD_PM	0x3004198	0x00000000	0x00000000	No	N/A
ISTATUS_PM	0x300419C	0x00000000	0x00000000	No	N/A
ATS_PRI_REPORT	0x30041A0	0x00000000	0x00000000	No	N/A
LTR_VALUES	0x30041A4	0x00000000	0x00000000	No	N/A
ISTATUS_DMA0	0x30041B0	0x00000000	0x00000000	No	N/A
ISTATUS_DMA1	0x30041B4	0x00000000	0x00000000	No	N/A
ISTATUS_P_ADT_WIN0	0x30041D8	0x00000000	0x00000000	No	N/A
ISTATUS_P_ADT_WIN1	0x30041DC	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV0	0x30041E0	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV1	0x30041E4	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV2	0x30041E8	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV3	0x30041EC	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW0	0x3004200	0x000B0011	0x000B0011	No	N/A
ROUTING_RULES_R_DW1	0x3004204	0x00000015	0x00000015	No	N/A
ROUTING_RULES_R_DW2	0x3004208	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW3	0x300420C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW4	0x3004210	0x000E0011	0x000E0011	No	N/A
ROUTING_RULES_R_DW5	0x3004214	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW6	0x3004218	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW7	0x300421C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW8	0x3004220	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW9	0x3004224	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW10	0x3004228	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW11	0x300422C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW12	0x3004230	0x00000015	0x00000015	No	N/A
ROUTING_RULES_R_DW13	0x3004234	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW14	0x3004238	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW15	0x300423C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW0	0x3004240	0x000F0011	0x000F0011	No	N/A
ROUTING_RULES_W_DW1	0x3004244	0x00000014	0x00000014	No	N/A
ROUTING_RULES_W_DW2	0x3004248	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW3	0x300424C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW4	0x3004250	0x000B0011	0x000B0011	No	N/A
ROUTING_RULES_W_DW5	0x3004254	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW6	0x3004258	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW7	0x300425C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW8	0x3004260	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW9	0x3004264	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW10	0x3004268	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW11	0x300426C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW12	0x3004270	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW13	0x3004274	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW14	0x3004278	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW15	0x300427C	0x00000000	0x00000000	No	N/A
ARBITRATION_RULES_DW0	0x3004280	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW1	0x3004284	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW2	0x3004288	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW3	0x300428C	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW4	0x3004290	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW5	0x3004294	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW6	0x3004298	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW7	0x300429C	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW8	0x30042A0	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW9	0x30042A4	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW10	0x30042A8	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW11	0x30042AC	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW12	0x30042B0	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW13	0x30042B4	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW14	0x30042B8	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW15	0x30042BC	0x11111111	0x11111111	No	N/A
PRIORITY_RULES_DW0	0x30042C0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW1	0x30042C4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW2	0x30042C8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW3	0x30042CC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW4	0x30042D0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW5	0x30042D4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW6	0x30042D8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW7	0x30042DC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW8	0x30042E0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW9	0x30042E4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW10	0x30042E8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW11	0x30042EC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW12	0x30042F0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW13	0x30042F4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW14	0x30042F8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW15	0x30042FC	0x00000000	0x00000000	No	N/A
P2A_TC_QOS_CONV	0x30043C0	0x00000000	0x00000000	No	N/A
P2A_ATTR_CACHE_CONV	0x30043C4	0x00000000	0x00000000	No	N/A
P2A_NC_BASE_ADDR_DW0	0x30043C8	0x00000000	0x00000000	No	N/A
P2A_NC_BASE_ADDR_DW1	0x30043CC	0x00000000	0x00000000	No	N/A
DMA0_SRC_PARAM	0x3004400	0x00000000	0x00000000	No	N/A
DMA0_DESTPARAM	0x3004404	0x00000000	0x00000000	No	N/A
DMA0_SRCADDR_LDW	0x3004408	0x00000000	0x00000000	No	N/A
DMA0_SRCADDR_UDW	0x300440C	0x00000000	0x00000000	No	N/A
DMA0_DESTADDR_LDW	0x3004410	0x00000000	0x00000000	No	N/A
DMA0_DESTADDR_UDW	0x3004414	0x00000000	0x00000000	No	N/A
DMA0_LENGTH	0x3004418	0x00000000	0x00000000	No	N/A
DMA0_CONTROL	0x300441C	0x03000000	0x03000000	No	N/A
DMA0_STATUS	0x3004420	0x00000000	0x00000000	No	N/A
DMA0_PRC_LENGTH	0x3004424	0x00000000	0x00000000	No	N/A
DMA0_SHARE_ACCESS	0x3004428	0x00000000	0x00000000	No	N/A
DMA1_SRC_PARAM	0x3004440	0x00000004	0x00000004	No	N/A
DMA1_DESTPARAM	0x3004444	0x00000000	0x00000000	No	N/A
DMA1_SRCADDR_LDW	0x3004448	0x00000000	0x00000000	No	N/A
DMA1_SRCADDR_UDW	0x300444C	0x00000000	0x00000000	No	N/A
DMA1_DESTADDR_LDW	0x3004450	0x00000000	0x00000000	No	N/A
DMA1_DESTADDR_UDW	0x3004454	0x00000000	0x00000000	No	N/A
DMA1_LENGTH	0x3004458	0x00000000	0x00000000	No	N/A
DMA1_CONTROL	0x300445C	0x00000000	0x00000000	No	N/A
DMA1_STATUS	0x3004460	0x00000000	0x00000000	No	N/A
DMA1_PRC_LENGTH	0x3004464	0x00000000	0x00000000	No	N/A
DMA1_SHARE_ACCESS	0x3004468	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_SRCADDR_PARAM	0x3004600	0x00000017	0x00000017	No	N/A
ATR0_PCIE_WIN0_SRC_ADDR	0x3004604	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_ADDR_LSB	0x3004608	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_ADDR_UDW	0x300460C	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_PARAM	0x3004610	0x0000000C	0x0000000C	No	N/A
ATR0_PCIE_WIN0_TRSL_MASK_DW0	0x3004618	0xFFFFF000	0xFFFFF000	No	N/A
ATR0_PCIE_WIN0_TRSL_MASK_DW1	0x300461C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR1_PCIE_WIN0_SRCADDR_PARAM	0x3004620	0x00000016	0x00000016	No	N/A
ATR1_PCIE_WIN0_SRC_ADDR	0x3004624	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_ADDR_LSB	0x3004628	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_ADDR_UDW	0x300462C	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_PARAM	0x3004630	0x00000001	0x00000001	No	N/A
ATR1_PCIE_WIN0_TRSL_MASK_DW0	0x3004638	0xFFFFF000	0xFFFFF000	No	N/A
ATR1_PCIE_WIN0_TRSL_MASK_DW1	0x300463C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR2_PCIE_WIN0_SRCADDR_PARAM	0x3004640	0x00000019	0x00000019	No	N/A
ATR2_PCIE_WIN0_SRC_ADDR	0x3004644	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_ADDR_LSB	0x3004648	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_ADDR_UDW	0x300464C	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_PARAM	0x3004650	0x00000004	0x00000004	No	N/A
ATR2_PCIE_WIN0_TRSL_MASK_DW0	0x3004658	0xFFFFF000	0xFFFFF000	No	N/A
ATR2_PCIE_WIN0_TRSL_MASK_DW1	0x300465C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR3_PCIE_WIN0_SRCADDR_PARAM	0x3004660	0x00000016	0x00000016	No	N/A
ATR3_PCIE_WIN0_SRC_ADDR	0x3004664	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_ADDR_LSB	0x3004668	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_ADDR_UDW	0x300466C	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_PARAM	0x3004670	0x00000001	0x00000001	No	N/A
ATR3_PCIE_WIN0_TRSL_MASK_DW0	0x3004678	0xFFFFF000	0xFFFFF000	No	N/A
ATR3_PCIE_WIN0_TRSL_MASK_DW1	0x300467C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR4_PCIE_WIN0_SRCADDR_PARAM	0x3004680	0x00000016	0x00000016	No	N/A
ATR4_PCIE_WIN0_SRC_ADDR	0x3004684	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_ADDR_LSB	0x3004688	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_ADDR_UDW	0x300468C	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_PARAM	0x3004690	0x00000004	0x00000004	No	N/A
ATR4_PCIE_WIN0_TRSL_MASK_DW0	0x3004698	0xFFFFF000	0xFFFFF000	No	N/A
ATR4_PCIE_WIN0_TRSL_MASK_DW1	0x300469C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR5_PCIE_WIN0_SRCADDR_PARAM	0x30046A0	0x00000016	0x00000016	No	N/A
ATR5_PCIE_WIN0_SRC_ADDR	0x30046A4	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_ADDR_LSB	0x30046A8	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_ADDR_UDW	0x30046AC	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_PARAM	0x30046B0	0x00000004	0x00000004	No	N/A
ATR5_PCIE_WIN0_TRSL_MASK_DW0	0x30046B8	0xFFFFF000	0xFFFFF000	No	N/A
ATR5_PCIE_WIN0_TRSL_MASK_DW1	0x30046BC	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR0_AXI4_SLV0_SRCADDR_PARAM	0x3004800	0x00000016	0x00000016	No	N/A
ATR0_AXI4_SLV0_SRC_ADDR	0x3004804	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_ADDR_LSB	0x3004808	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_ADDR_UDW	0x300480C	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_PARAM	0x3004810	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_MASK_DW0	0x3004818	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_MASK_DW1	0x300481C	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_SRCADDR_PARAM	0x3004820	0x00000016	0x00000016	No	N/A
ATR1_AXI4_SLV0_SRC_ADDR	0x3004824	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_ADDR_LSB	0x3004828	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_ADDR_UDW	0x300482C	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_PARAM	0x3004830	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_MASK_DW0	0x3004838	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_MASK_DW1	0x300483C	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_SRCADDR_PARAM	0x3004840	0x00000016	0x00000016	No	N/A
ATR2_AXI4_SLV0_SRC_ADDR	0x3004844	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_ADDR_LSB	0x3004848	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_ADDR_UDW	0x300484C	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_PARAM	0x3004850	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_MASK_DW0	0x3004858	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_MASK_DW1	0x300485C	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_SRCADDR_PARAM	0x3004860	0x00000016	0x00000016	No	N/A
ATR3_AXI4_SLV0_SRC_ADDR	0x3004864	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_ADDR_LSB	0x3004868	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_ADDR_UDW	0x300486C	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_PARAM	0x3004870	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_MASK_DW0	0x3004878	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_MASK_DW1	0x300487C	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_SRCADDR_PARAM	0x3004880	0x00000016	0x00000016	No	N/A
ATR4_AXI4_SLV0_SRC_ADDR	0x3004884	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_ADDR_LSB	0x3004888	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_ADDR_UDW	0x300488C	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_PARAM	0x3004890	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_MASK_DW0	0x3004898	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_MASK_DW1	0x300489C	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_SRCADDR_PARAM	0x30048A0	0x00000016	0x00000016	No	N/A
ATR5_AXI4_SLV0_SRC_ADDR	0x30048A4	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_ADDR_LSB	0x30048A8	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_ADDR_UDW	0x30048AC	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_PARAM	0x30048B0	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_MASK_DW0	0x30048B8	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_MASK_DW1	0x30048BC	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PCIE1_PCIE_CTRL (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x300A000	0x00000000	0x00000000	No	1
DEV_CONTROL	0x300A004	0x00019110	0x00000000	Yes	1
CLOCK_CONTROL	0x300A008	0x1FC00000	0x00000000	Yes	1
SOFT_RESET_DEBUG_INFO	0x300A010	0x00000000	0x00000000	No	N/A
SOFT_RESET_CTLR	0x300A014	0x00100002	0x00100002	No	N/A
SEC_ERROR_EVENT_CNT	0x300A020	0x00000000	0x00000000	No	N/A
DED_ERROR_EVENT_CNT	0x300A024	0x00000000	0x00000000	No	N/A
SEC_ERROR_INT	0x300A028	0x00000000	0x00000000	No	N/A
SEC_ERROR_INT_MASK	0x300A02C	0x00001111	0x00001111	No	N/A
DED_ERROR_INT	0x300A030	0x00000000	0x00000000	No	N/A
DED_ERROR_INT_MASK	0x300A034	0x00001111	0x00001111	No	N/A
ECC_CONTROL	0x300A038	0x00000000	0x00000000	No	N/A
ECC_ERR_LOC	0x300A03C	0x00000000	0x00000000	No	N/A
RAM_MARGIN_1	0x300A040	0x00000000	0x00000000	No	N/A
RAM_MARGIN_2	0x300A044	0x00000000	0x00000000	No	N/A
RAM_POWER_CONTROL	0x300A048	0x00000000	0x04040404	Yes	N/A
DEBUG_SEL	0x300A050	0x00000000	0x00000000	No	N/A
LTSSM_STATE	0x300A05C	0x00000000	0x00000000	No	N/A
PHY_COMMON_INTERFACE	0x300A060	0x00000000	0x00000000	No	N/A
PL_TX_LANEIF_0	0x300A064	0x00000000	0x00000000	No	N/A
PL_RX_LANEIF_0	0x300A068	0x00000000	0x00000000	No	N/A
PL_WAKECLKREQ	0x300A06C	0x00000000	0x00000000	No	N/A
PCICONF_PCI_IDS_OVERRIDE	0x300A080	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_31_0	0x300A084	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_63_32	0x300A088	0x00000000	0x00000000	No	1
PCICONF_PCI_IDS_95_64	0x300A08C	0x00000000	0x00000000	No	1
PCIE_PEX_DEV_LINK_SPC2	0x300A0A0	0x00000200	0x00000000	Yes	1
PCIE_PEX_SPC	0x300A0A4	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG0	0x300A100	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG1	0x300A104	0x00000000	0x00000000	No	1
PCIE_AXI_MASTER_ATR_CFG2	0x300A108	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG0	0x300A120	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG1	0x300A124	0x00000000	0x00000000	No	1
AXI_SLAVE_PCIE_ATR_CFG2	0x300A128	0x00000000	0x00000000	No	N/A
PCIE_BAR_01	0x300A140	0x00000000	0x00000000	No	N/A
PCIE_BAR_23	0x300A144	0x00000000	0x00000000	No	N/A
PCIE_BAR_45	0x300A148	0x00000000	0x00000000	No	N/A
PCIE_EVENT_INT	0x300A14C	0x00000000	0x00070000	Yes	N/A
SPARE	0x300A150	0x00000000	0x00000000	No	N/A
PCIE_BAR_WIN	0x300A180	0x00000000	0x00000000	No	1
TEST_BUS_IN_31_0	0x300AC80	0x00000000	0x00000000	No	N/A
TEST_BUS_IN_63_32	0x300AC84	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PCIE1_PCIE_BRIDGE (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
BRIDGE_VER	0x3008000	0x02511154	0x02511154	No	N/A
BRIDGE_BUS	0x3008004	0x11885153	0x11885153	No	N/A
BRIDGE_IMPL_IF	0x3008008	0x0000032B	0x0000032B	No	N/A
PCIE_IF_CONF	0x3008010	0x11440170	0x11440170	No	N/A
PCIE_BASIC_CONF	0x3008014	0x03110307	0x03110307	No	N/A
PCIE_BASIC_STATUS	0x3008018	0x20000100	0x20000100	No	N/A
AXI_SLVL_CONF	0x3008024	0xBB002121	0xBB002121	No	N/A
AXI_MST0_CONF	0x3008030	0x11883442	0x11883442	No	N/A
AXI_SLV0_CONF	0x3008034	0x44443443	0x44443443	No	N/A
GEN_SETTINGS	0x3008080	0x00019300	0x00019300	No	N/A
PCIE_CFGCTRL	0x3008084	0x00000000	0x00000000	No	N/A
PCIE_PIPE_DW0	0x3008088	0x20000000	0x20000000	No	N/A
PCIE_PIPE_DW1	0x300808C	0x08000001	0x08000001	No	N/A
PCIE_VC_CRED_DW0	0x3008090	0x0100B818	0x0100B818	No	N/A
PCIE_VC_CRED_DW1	0x3008094	0x00000001	0x00000001	No	N/A
PCIE_PCI_IDS_DW0	0x3008098	0x11001556	0x11001556	No	N/A
PCIE_PCI_IDS_DW1	0x300809C	0xFF000001	0xFF000001	No	N/A
PCIE_PCI_IDS_DW2	0x30080A0	0x11001556	0x11001556	No	N/A
PCIE_PCI_LPM	0x30080A4	0xFE000000	0xFE000000	No	N/A
PCIE_PCI_IRQ_DW0	0x30080A8	0x80000054	0x80000054	No	N/A
PCIE_PCI_IRQ_DW1	0x30080AC	0x00000000	0x00000000	No	N/A
PCIE_PCI_IRQ_DW2	0x30080B0	0x00000000	0x00000000	No	N/A
PCIE_PCI_IOV_DW0	0x30080B4	0x0000000A	0x0000000A	No	N/A
PCIE_PCI_IOV_DW1	0x30080B8	0x00000000	0x00000000	No	N/A
PCIE_PEX_DEV	0x30080C0	0x00000001	0x00000001	No	N/A
PCIE_PEX_DEV2	0x30080C4	0x0000081F	0x0000081F	No	N/A
PCIE_PEX_LINK	0x30080C8	0x01001C00	0x01001C00	No	N/A
PCIE_PEX_SLOT	0x30080CC	0x0000007F	0x0000007F	No	N/A
PCIE_PEX_ROOT_VC	0x30080D0	0x00000001	0x00000001	No	N/A
PCIE_PEX_SPC	0x30080D4	0x80005000	0x80005000	No	N/A
PCIE_PEX_SPC2	0x30080D8	0x000C6006	0x000C6006	No	N/A
PCIE_PEX_NFTS	0x30080DC	0x00202020	0x00202020	No	N/A
PCIE_PEX_L1SS	0x30080E0	0x00280A1D	0x00280A1D	No	N/A
PCIE_BAR_01_DW0	0x30080E4	0xFFFFF00C	0xFFFFF00C	No	N/A
PCIE_BAR_01_DW1	0x30080E8	0xFFFFFFFF	0xFFFFFFFF	No	N/A
PCIE_BAR_23_DW0	0x30080EC	0xFFFFE00C	0xFFFFE00C	No	N/A
PCIE_BAR_23_DW1	0x30080F0	0xFFFFFFFF	0xFFFFFFFF	No	N/A
PCIE_BAR_45_DW0	0x30080F4	0x00000000	0x00000000	No	N/A
PCIE_BAR_45_DW1	0x30080F8	0x00000000	0x00000000	No	N/A
PCIE_BAR_WIN	0x30080FC	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW0	0x3008100	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW1	0x3008104	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW2	0x3008108	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW3	0x300810C	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW4	0x3008110	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW5	0x3008114	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW6	0x3008118	0x00000000	0x00000000	No	N/A
PCIE_EQ_PRESET_DW7	0x300811C	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW0	0x3008120	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW1	0x3008124	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW2	0x3008128	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW3	0x300812C	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW4	0x3008130	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW5	0x3008134	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW6	0x3008138	0x00000000	0x00000000	No	N/A
PCIE_SRIOV_DW7	0x300813C	0x00000000	0x00000000	No	N/A
PCIE_CFGNUM	0x3008140	0x00000000	0x00000000	No	N/A
PM_CONF_DW0	0x3008174	0x00000000	0x00000000	No	N/A
PM_CONF_DW1	0x3008178	0x00000000	0x00000000	No	N/A
PM_CONF_DW2	0x300817C	0x00000000	0x00000000	No	N/A
IMASK_LOCAL	0x3008180	0x00000000	0x00000000	No	N/A
ISTATUS_LOCAL	0x3008184	0x00000000	0x00000000	No	N/A
IMASK_HOST	0x3008188	0x00000000	0x00000000	No	N/A
ISTATUS_HOST	0x300818C	0x00000000	0x00000000	No	N/A
IMSI_ADDR	0x3008190	0x00000190	0x00000190	No	N/A
ISTATUS_MSI	0x3008194	0x00000000	0x00000000	No	N/A
ICMD_PM	0x3008198	0x00000000	0x00000000	No	N/A
ISTATUS_PM	0x300819C	0x00000000	0x00000000	No	N/A
ATS_PRI_REPORT	0x30081A0	0x00000000	0x00000000	No	N/A
LTR_VALUES	0x30081A4	0x00000000	0x00000000	No	N/A
ISTATUS_DMA0	0x30081B0	0x00000000	0x00000000	No	N/A
ISTATUS_DMA1	0x30081B4	0x00000000	0x00000000	No	N/A
ISTATUS_P_ADT_WIN0	0x30081D8	0x00000000	0x00000000	No	N/A
ISTATUS_P_ADT_WIN1	0x30081DC	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV0	0x30081E0	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV1	0x30081E4	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV2	0x30081E8	0x00000000	0x00000000	No	N/A
ISTATUS_A_ADT_SLV3	0x30081EC	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW0	0x3008200	0x000B0011	0x000B0011	No	N/A
ROUTING_RULES_R_DW1	0x3008204	0x00000015	0x00000015	No	N/A
ROUTING_RULES_R_DW2	0x3008208	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW3	0x300820C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW4	0x3008210	0x000E0011	0x000E0011	No	N/A
ROUTING_RULES_R_DW5	0x3008214	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW6	0x3008218	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW7	0x300821C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW8	0x3008220	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW9	0x3008224	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW10	0x3008228	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW11	0x300822C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW12	0x3008230	0x00000015	0x00000015	No	N/A
ROUTING_RULES_R_DW13	0x3008234	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW14	0x3008238	0x00000000	0x00000000	No	N/A
ROUTING_RULES_R_DW15	0x300823C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW0	0x3008240	0x000F0011	0x000F0011	No	N/A
ROUTING_RULES_W_DW1	0x3008244	0x00000014	0x00000014	No	N/A
ROUTING_RULES_W_DW2	0x3008248	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW3	0x300824C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW4	0x3008250	0x000B0011	0x000B0011	No	N/A
ROUTING_RULES_W_DW5	0x3008254	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW6	0x3008258	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW7	0x300825C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW8	0x3008260	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW9	0x3008264	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW10	0x3008268	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW11	0x300826C	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW12	0x3008270	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW13	0x3008274	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW14	0x3008278	0x00000000	0x00000000	No	N/A
ROUTING_RULES_W_DW15	0x300827C	0x00000000	0x00000000	No	N/A
ARBITRATION_RULES_DW0	0x3008280	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW1	0x3008284	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW2	0x3008288	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW3	0x300828C	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW4	0x3008290	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW5	0x3008294	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW6	0x3008298	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW7	0x300829C	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW8	0x30082A0	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW9	0x30082A4	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW10	0x30082A8	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW11	0x30082AC	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW12	0x30082B0	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW13	0x30082B4	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW14	0x30082B8	0x11111111	0x11111111	No	N/A
ARBITRATION_RULES_DW15	0x30082BC	0x11111111	0x11111111	No	N/A
PRIORITY_RULES_DW0	0x30082C0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW1	0x30082C4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW2	0x30082C8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW3	0x30082CC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW4	0x30082D0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW5	0x30082D4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW6	0x30082D8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW7	0x30082DC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW8	0x30082E0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW9	0x30082E4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW10	0x30082E8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW11	0x30082EC	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW12	0x30082F0	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW13	0x30082F4	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW14	0x30082F8	0x00000000	0x00000000	No	N/A
PRIORITY_RULES_DW15	0x30082FC	0x00000000	0x00000000	No	N/A
P2A_TC_QOS_CONV	0x30083C0	0x00000000	0x00000000	No	N/A
P2A_ATTR_CACHE_CONV	0x30083C4	0x00000000	0x00000000	No	N/A
P2A_NC_BASE_ADDR_DW0	0x30083C8	0x00000000	0x00000000	No	N/A
P2A_NC_BASE_ADDR_DW1	0x30083CC	0x00000000	0x00000000	No	N/A
DMA0_SRC_PARAM	0x3008400	0x00000000	0x00000000	No	N/A
DMA0_DESTPARAM	0x3008404	0x00000000	0x00000000	No	N/A
DMA0_SRCADDR_LDW	0x3008408	0x00000000	0x00000000	No	N/A
DMA0_SRCADDR_UDW	0x300840C	0x00000000	0x00000000	No	N/A
DMA0_DESTADDR_LDW	0x3008410	0x00000000	0x00000000	No	N/A
DMA0_DESTADDR_UDW	0x3008414	0x00000000	0x00000000	No	N/A
DMA0_LENGTH	0x3008418	0x00000000	0x00000000	No	N/A
DMA0_CONTROL	0x300841C	0x03000000	0x03000000	No	N/A
DMA0_STATUS	0x3008420	0x00000000	0x00000000	No	N/A
DMA0_PRC_LENGTH	0x3008424	0x00000000	0x00000000	No	N/A
DMA0_SHARE_ACCESS	0x3008428	0x00000000	0x00000000	No	N/A
DMA1_SRC_PARAM	0x3008440	0x00000004	0x00000004	No	N/A
DMA1_DESTPARAM	0x3008444	0x00000000	0x00000000	No	N/A
DMA1_SRCADDR_LDW	0x3008448	0x00000000	0x00000000	No	N/A
DMA1_SRCADDR_UDW	0x300844C	0x00000000	0x00000000	No	N/A
DMA1_DESTADDR_LDW	0x3008450	0x00000000	0x00000000	No	N/A
DMA1_DESTADDR_UDW	0x3008454	0x00000000	0x00000000	No	N/A
DMA1_LENGTH	0x3008458	0x00000000	0x00000000	No	N/A
DMA1_CONTROL	0x300845C	0x00000000	0x00000000	No	N/A
DMA1_STATUS	0x3008460	0x00000000	0x00000000	No	N/A
DMA1_PRC_LENGTH	0x3008464	0x00000000	0x00000000	No	N/A
DMA1_SHARE_ACCESS	0x3008468	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_SRCADDR_PARAM	0x3008600	0x00000017	0x00000017	No	N/A
ATR0_PCIE_WIN0_SRC_ADDR	0x3008604	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_ADDR_LSB	0x3008608	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_ADDR_UDW	0x300860C	0x00000000	0x00000000	No	N/A
ATR0_PCIE_WIN0_TRSL_PARAM	0x3008610	0x0000000C	0x0000000C	No	N/A
ATR0_PCIE_WIN0_TRSL_MASK_DW0	0x3008618	0xFFFFF000	0xFFFFF000	No	N/A
ATR0_PCIE_WIN0_TRSL_MASK_DW1	0x300861C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR1_PCIE_WIN0_SRCADDR_PARAM	0x3008620	0x00000016	0x00000016	No	N/A
ATR1_PCIE_WIN0_SRC_ADDR	0x3008624	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_ADDR_LSB	0x3008628	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_ADDR_UDW	0x300862C	0x00000000	0x00000000	No	N/A
ATR1_PCIE_WIN0_TRSL_PARAM	0x3008630	0x00000001	0x00000001	No	N/A
ATR1_PCIE_WIN0_TRSL_MASK_DW0	0x3008638	0xFFFFF000	0xFFFFF000	No	N/A
ATR1_PCIE_WIN0_TRSL_MASK_DW1	0x300863C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR2_PCIE_WIN0_SRCADDR_PARAM	0x3008640	0x00000019	0x00000019	No	N/A
ATR2_PCIE_WIN0_SRC_ADDR	0x3008644	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_ADDR_LSB	0x3008648	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_ADDR_UDW	0x300864C	0x00000000	0x00000000	No	N/A
ATR2_PCIE_WIN0_TRSL_PARAM	0x3008650	0x00000004	0x00000004	No	N/A
ATR2_PCIE_WIN0_TRSL_MASK_DW0	0x3008658	0xFFFFF000	0xFFFFF000	No	N/A
ATR2_PCIE_WIN0_TRSL_MASK_DW1	0x300865C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR3_PCIE_WIN0_SRCADDR_PARAM	0x3008660	0x00000016	0x00000016	No	N/A
ATR3_PCIE_WIN0_SRC_ADDR	0x3008664	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_ADDR_LSB	0x3008668	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_ADDR_UDW	0x300866C	0x00000000	0x00000000	No	N/A
ATR3_PCIE_WIN0_TRSL_PARAM	0x3008670	0x00000001	0x00000001	No	N/A
ATR3_PCIE_WIN0_TRSL_MASK_DW0	0x3008678	0xFFFFF000	0xFFFFF000	No	N/A
ATR3_PCIE_WIN0_TRSL_MASK_DW1	0x300867C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR4_PCIE_WIN0_SRCADDR_PARAM	0x3008680	0x00000016	0x00000016	No	N/A
ATR4_PCIE_WIN0_SRC_ADDR	0x3008684	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_ADDR_LSB	0x3008688	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_ADDR_UDW	0x300868C	0x00000000	0x00000000	No	N/A
ATR4_PCIE_WIN0_TRSL_PARAM	0x3008690	0x00000004	0x00000004	No	N/A
ATR4_PCIE_WIN0_TRSL_MASK_DW0	0x3008698	0xFFFFF000	0xFFFFF000	No	N/A
ATR4_PCIE_WIN0_TRSL_MASK_DW1	0x300869C	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR5_PCIE_WIN0_SRCADDR_PARAM	0x30086A0	0x00000016	0x00000016	No	N/A
ATR5_PCIE_WIN0_SRC_ADDR	0x30086A4	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_ADDR_LSB	0x30086A8	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_ADDR_UDW	0x30086AC	0x00000000	0x00000000	No	N/A
ATR5_PCIE_WIN0_TRSL_PARAM	0x30086B0	0x00000004	0x00000004	No	N/A
ATR5_PCIE_WIN0_TRSL_MASK_DW0	0x30086B8	0xFFFFF000	0xFFFFF000	No	N/A
ATR5_PCIE_WIN0_TRSL_MASK_DW1	0x30086BC	0xFFFFFFFF	0xFFFFFFFF	No	N/A
ATR0_AXI4_SLV0_SRCADDR_PARAM	0x3008800	0x00000016	0x00000016	No	N/A
ATR0_AXI4_SLV0_SRC_ADDR	0x3008804	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_ADDR_LSB	0x3008808	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_ADDR_UDW	0x300880C	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_PARAM	0x3008810	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_MASK_DW0	0x3008818	0x00000000	0x00000000	No	N/A
ATR0_AXI4_SLV0_TRSL_MASK_DW1	0x300881C	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_SRCADDR_PARAM	0x3008820	0x00000016	0x00000016	No	N/A
ATR1_AXI4_SLV0_SRC_ADDR	0x3008824	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_ADDR_LSB	0x3008828	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_ADDR_UDW	0x300882C	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_PARAM	0x3008830	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_MASK_DW0	0x3008838	0x00000000	0x00000000	No	N/A
ATR1_AXI4_SLV0_TRSL_MASK_DW1	0x300883C	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_SRCADDR_PARAM	0x3008840	0x00000016	0x00000016	No	N/A
ATR2_AXI4_SLV0_SRC_ADDR	0x3008844	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_ADDR_LSB	0x3008848	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_ADDR_UDW	0x300884C	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_PARAM	0x3008850	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_MASK_DW0	0x3008858	0x00000000	0x00000000	No	N/A
ATR2_AXI4_SLV0_TRSL_MASK_DW1	0x300885C	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_SRCADDR_PARAM	0x3008860	0x00000016	0x00000016	No	N/A
ATR3_AXI4_SLV0_SRC_ADDR	0x3008864	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_ADDR_LSB	0x3008868	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_ADDR_UDW	0x300886C	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_PARAM	0x3008870	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_MASK_DW0	0x3008878	0x00000000	0x00000000	No	N/A
ATR3_AXI4_SLV0_TRSL_MASK_DW1	0x300887C	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_SRCADDR_PARAM	0x3008880	0x00000016	0x00000016	No	N/A
ATR4_AXI4_SLV0_SRC_ADDR	0x3008884	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_ADDR_LSB	0x3008888	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_ADDR_UDW	0x300888C	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_PARAM	0x3008890	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_MASK_DW0	0x3008898	0x00000000	0x00000000	No	N/A
ATR4_AXI4_SLV0_TRSL_MASK_DW1	0x300889C	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_SRCADDR_PARAM	0x30088A0	0x00000016	0x00000016	No	N/A
ATR5_AXI4_SLV0_SRC_ADDR	0x30088A4	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_ADDR_LSB	0x30088A8	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_ADDR_UDW	0x30088AC	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_PARAM	0x30088B0	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_MASK_DW0	0x30088B8	0x00000000	0x00000000	No	N/A
ATR5_AXI4_SLV0_TRSL_MASK_DW1	0x30088BC	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PMA_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1088000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1088004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1088008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x108800C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1088010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1088014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1088018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1088020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1088024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1088028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x108802C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1088030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1088034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1088038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x108803C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1088040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1088044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1088048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x108804C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1088050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1088054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1088058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x108805C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1088070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1088074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1088078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x108807C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1088080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1088084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1088088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x108808C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1088090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1088094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1088098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x108809C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10880A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10880A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10880A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10880AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10880B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10880B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10880B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10880C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10880D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10880D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10880D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10880DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10880E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10880E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10880E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10880EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10880F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10880F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10880F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10880FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1088100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PCS_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x88000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x88004	0x00000000	0x00000000	No	1
LOVR_R0	0x88008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x8800C	0x0000005D	0x00000058	Yes	1
L64_R0	0x88010	0x01400000	0x01400000	No	N/A
L64_R1	0x88014	0x00000001	0x00000001	No	N/A
L64_R2	0x88018	0x00000000	0x00000000	No	N/A
L64_R3	0x8801C	0x00000000	0x00000000	No	N/A
L64_R4	0x88020	0x00000000	0x00000000	No	N/A
L64_R5	0x88024	0x00000000	0x00000000	No	N/A
L64_R6	0x88028	0x00000000	0x00000000	No	N/A
L64_R7	0x8802C	0x00000000	0x00000000	No	N/A
L64_R8	0x88030	0x00000000	0x00000000	No	N/A
L64_R9	0x88034	0x00000000	0x00000000	No	N/A
L64_R10	0x88038	0x00000000	0x00000000	No	N/A
L8_R0	0x88040	0x00000000	0x00000000	No	1
LNTV_R0	0x88050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x88058	0x00000000	0x00000000	No	1
LCLK_R1	0x8805C	0x03000000	0x00000000	Yes	1
LRST_R0	0x88068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x8806C	0x00000000	0x00000000	No	N/A
OOB_R0	0x88078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x8807C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x88080	0x00000000	0x00000000	No	N/A
OOB_R3	0x88084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x88088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x8808C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x88090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x88094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PCSCMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x90000	0x00000000	0x00000000	No	1
GSSCLK_CTRL	0x90004	0x00000000	0x00000000	No	1
QRST_R0	0x90008	0x00000000	0x00000000	No	1
QDBG_R0	0x9000C	0x00001000	0x00000000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PMA_CMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1090000	0x00000000	0x00000000	No	1
TXPLL_CLKBUF	0x1090004	0x00000000	0x00000000	No	1
TXPLL_CTRL	0x1090008	0x00E60010	0x00E60010	No	1
TXPLL_CLK_SEL	0x109000C	0x3F3F1C03	0x3F3F0000	Yes	1
TXPLL_DIV_1	0x1090010	0x00190019	0x00000000	Yes	1
TXPLL_DIV_2	0x1090014	0x01000001	0x00000000	Yes	1
TXPLL_JA_1	0x1090018	0x00640064	0x00640064	No	N/A
TXPLL_JA_2	0x109001C	0x00000064	0x00000064	No	N/A
TXPLL_JA_3	0x1090020	0x00640064	0x00640064	No	N/A
TXPLL_JA_4	0x1090024	0x01010001	0x01010001	No	N/A
TXPLL_JA_5	0x1090028	0x01010101	0x01010101	No	N/A
TXPLL_JA_6	0x109002C	0x01010101	0x01010101	No	N/A
TXPLL_JA_7	0x1090030	0x07000001	0x07000001	No	N/A
TXPLL_JA_8	0x1090034	0x00000000	0x00000000	No	N/A
TXPLL_JA_9	0x1090038	0x00180014	0x00180014	No	N/A
TXPLL_JA_10	0x109003C	0x00000000	0x00000000	No	N/A
TXPLL_JA_RST	0x1090040	0x00000055	0x00000055	No	N/A
SERDES_SSMOD	0x1090044	0x007F0102	0x007F0102	No	N/A
SERDES_RTERM	0x1090050	0x000D0703	0x000D0703	No	N/A
SERDES_RTT	0x1090054	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_MAIN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2090000	0x00000000	0x00000000	No	1
SPARE	0x2090190	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PMA_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1082000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1082004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1082008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x108200C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1082010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1082014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1082018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1082020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1082024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1082028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x108202C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1082030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1082034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1082038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x108203C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1082040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1082044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1082048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x108204C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1082050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1082054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1082058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x108205C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1082070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1082074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1082078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x108207C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1082080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1082084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1082088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x108208C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1082090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1082094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1082098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x108209C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10820A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10820A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10820A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10820AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10820B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10820B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10820B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10820C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10820D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10820D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10820D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10820DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10820E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10820E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10820E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10820EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10820F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10820F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10820F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10820FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1082100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PCS_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x82000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x82004	0x00000000	0x00000000	No	1
LOVR_R0	0x82008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x8200C	0x0000005D	0x00000058	Yes	1
L64_R0	0x82010	0x01400000	0x01400000	No	N/A
L64_R1	0x82014	0x00000001	0x00000001	No	N/A
L64_R2	0x82018	0x00000000	0x00000000	No	N/A
L64_R3	0x8201C	0x00000000	0x00000000	No	N/A
L64_R4	0x82020	0x00000000	0x00000000	No	N/A
L64_R5	0x82024	0x00000000	0x00000000	No	N/A
L64_R6	0x82028	0x00000000	0x00000000	No	N/A
L64_R7	0x8202C	0x00000000	0x00000000	No	N/A
L64_R8	0x82030	0x00000000	0x00000000	No	N/A
L64_R9	0x82034	0x00000000	0x00000000	No	N/A
L64_R10	0x82038	0x00000000	0x00000000	No	N/A
L8_R0	0x82040	0x00000000	0x00000000	No	1
LNTV_R0	0x82050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x82058	0x00000000	0x00000000	No	1
LCLK_R1	0x8205C	0x03000000	0x00000000	Yes	1
LRST_R0	0x82068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x8206C	0x00000000	0x00000000	No	N/A
OOB_R0	0x82078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x8207C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x82080	0x00000000	0x00000000	No	N/A
OOB_R3	0x82084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x82088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x8208C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x82090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x82094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PMA_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1084000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1084004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1084008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x108400C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1084010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1084014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1084018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1084020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1084024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1084028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x108402C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1084030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1084034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1084038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x108403C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1084040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1084044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1084048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x108404C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1084050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1084054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1084058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x108405C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1084070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1084074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1084078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x108407C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1084080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1084084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1084088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x108408C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1084090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1084094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1084098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x108409C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10840A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10840A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10840A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10840AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10840B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10840B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10840B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10840C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10840D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10840D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10840D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10840DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10840E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10840E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10840E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10840EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10840F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10840F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10840F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10840FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1084100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PCS_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x84000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x84004	0x00000000	0x00000000	No	1
LOVR_R0	0x84008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x8400C	0x0000005D	0x00000058	Yes	1
L64_R0	0x84010	0x01400000	0x01400000	No	N/A
L64_R1	0x84014	0x00000001	0x00000001	No	N/A
L64_R2	0x84018	0x00000000	0x00000000	No	N/A
L64_R3	0x8401C	0x00000000	0x00000000	No	N/A
L64_R4	0x84020	0x00000000	0x00000000	No	N/A
L64_R5	0x84024	0x00000000	0x00000000	No	N/A
L64_R6	0x84028	0x00000000	0x00000000	No	N/A
L64_R7	0x8402C	0x00000000	0x00000000	No	N/A
L64_R8	0x84030	0x00000000	0x00000000	No	N/A
L64_R9	0x84034	0x00000000	0x00000000	No	N/A
L64_R10	0x84038	0x00000000	0x00000000	No	N/A
L8_R0	0x84040	0x00000000	0x00000000	No	1
LNTV_R0	0x84050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x84058	0x00000000	0x00000000	No	1
LCLK_R1	0x8405C	0x03000000	0x00000000	Yes	1
LRST_R0	0x84068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x8406C	0x00000000	0x00000000	No	N/A
OOB_R0	0x84078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x8407C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x84080	0x00000000	0x00000000	No	N/A
OOB_R3	0x84084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x84088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x8408C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x84090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x84094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PMA_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1081000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1081004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1081008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x108100C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1081010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1081014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1081018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1081020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1081024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1081028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x108102C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1081030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1081034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1081038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x108103C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1081040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1081044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1081048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x108104C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1081050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1081054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1081058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x108105C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1081070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1081074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1081078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x108107C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1081080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1081084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1081088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x108108C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1081090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1081094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1081098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x108109C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x10810A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x10810A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x10810A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x10810AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x10810B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x10810B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x10810B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x10810C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x10810D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x10810D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x10810D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x10810DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x10810E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x10810E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x10810E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x10810EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x10810F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x10810F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x10810F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x10810FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1081100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_PCS_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x81000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x81004	0x00000000	0x00000000	No	1
LOVR_R0	0x81008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x8100C	0x0000005D	0x00000058	Yes	1
L64_R0	0x81010	0x01400000	0x01400000	No	N/A
L64_R1	0x81014	0x00000001	0x00000001	No	N/A
L64_R2	0x81018	0x00000000	0x00000000	No	N/A
L64_R3	0x8101C	0x00000000	0x00000000	No	N/A
L64_R4	0x81020	0x00000000	0x00000000	No	N/A
L64_R5	0x81024	0x00000000	0x00000000	No	N/A
L64_R6	0x81028	0x00000000	0x00000000	No	N/A
L64_R7	0x8102C	0x00000000	0x00000000	No	N/A
L64_R8	0x81030	0x00000000	0x00000000	No	N/A
L64_R9	0x81034	0x00000000	0x00000000	No	N/A
L64_R10	0x81038	0x00000000	0x00000000	No	N/A
L8_R0	0x81040	0x00000000	0x00000000	No	1
LNTV_R0	0x81050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x81058	0x00000000	0x00000000	No	1
LCLK_R1	0x8105C	0x03000000	0x00000000	Yes	1
LRST_R0	0x81068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x8106C	0x00000000	0x00000000	No	N/A
OOB_R0	0x81078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x8107C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x81080	0x00000000	0x00000000	No	N/A
OOB_R3	0x81084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x81088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x8108C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x81090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x81094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PMA_LANE0 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1101000	0x00000000	0x00000000	No	1
DES_CDR_CTRL_1	0x1101004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1101008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x110100C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1101010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1101014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1101018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1101020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1101024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1101028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x110102C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1101030	0x000000A7	0x000000A7	No	1
DES_PKDET	0x1101034	0x000000AC	0x000000AD	Yes	1
DES_RTL_EM	0x1101038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x110103C	0x00000008	0x00000008	No	1
DES_RXPLL_DIV	0x1101040	0x00002219	0x00002219	No	1
DES_TEST_BUS	0x1101044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1101048	0x0000003C	0x0000003C	No	1
DES_RSTPD	0x110104C	0x0000002F	0x0000003F	Yes	N/A
DES_RTL_ERR_CHK	0x1101050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1101054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1101058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x110105C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1101070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1101074	0x00000070	0x00000015	Yes	1
SER_RSTPD	0x1101078	0x00000006	0x00000001	Yes	N/A
SER_DRV_BYP	0x110107C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1101080	0x00008A10	0x00008A10	No	1
SER_RXDET_OUT	0x1101084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1101088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x110108C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1101090	0x00007200	0x00007300	Yes	1
SER_TEST_BUS	0x1101094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1101098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x110109C	0x01000000	0x11000000	Yes	1
SER_DRV_CTRL_SEL	0x11010A0	0x00000000	0x0000000D	Yes	1
SER_DRV_CTRL_M0	0x11010A4	0x001B3423	0x001B240A	Yes	N/A
SER_DRV_CTRL_M1	0x11010A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x11010AC	0x001B1B1B	0x001B0203	Yes	N/A
SER_DRV_CTRL_M3	0x11010B0	0x001B1B14	0x003B1B14	Yes	N/A
SER_DRV_CTRL_M4	0x11010B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x11010B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x11010C0	0x00000100	0x00000000	Yes	1
DES_DFE_CAL_CTRL_0	0x11010D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x11010D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x11010D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x11010DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x11010E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x11010E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x11010E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x11010EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x11010F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x11010F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x11010F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x11010FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1101100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PCS_LANE0 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE1)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x101000	0x00000000	0x00000000	No	N/A
LFWF_R0	0x101004	0x00000000	0x00000000	No	1
LOVR_R0	0x101008	0x00000010	0x00000088	Yes	1
LPIP_R0	0x10100C	0x0000005D	0x00000058	Yes	1
L64_R0	0x101010	0x01400000	0x00000012	Yes	N/A
L64_R1	0x101014	0x00000001	0x00000001	No	N/A
L64_R2	0x101018	0x00000000	0x00000000	No	N/A
L64_R3	0x10101C	0x00000000	0x00000000	No	N/A
L64_R4	0x101020	0x00000000	0x00000000	No	N/A
L64_R5	0x101024	0x00000000	0x00000000	No	N/A
L64_R6	0x101028	0x00000000	0x00000000	No	N/A
L64_R7	0x10102C	0x00000000	0x00000000	No	N/A
L64_R8	0x101030	0x00000000	0x00000000	No	N/A
L64_R9	0x101034	0x00000000	0x00000000	No	N/A
L64_R10	0x101038	0x00000000	0x00000000	No	N/A
L8_R0	0x101040	0x00000000	0x00000000	No	1
LNTV_R0	0x101050	0x00000E0E	0x0000121E	Yes	1
LCLK_R0	0x101058	0x00000000	0x00050E11	Yes	1
LCLK_R1	0x10105C	0x03000000	0x000F0000	Yes	1
LRST_R0	0x101068	0x00000004	0x00000404	Yes	N/A
LRST_OPT	0x10106C	0x00000000	0x00000001	Yes	N/A
OOB_R0	0x101078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x10107C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x101080	0x00000000	0x00000000	No	N/A
OOB_R3	0x101084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x101088	0x03030347	0x03030347	No	1
PMA_CTRL_R1	0x10108C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x101090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x101094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PMA_LANE2 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1104000	0x00000000	0x00000000	No	1
DES_CDR_CTRL_1	0x1104004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1104008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x110400C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1104010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1104014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1104018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1104020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1104024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1104028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x110402C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1104030	0x000000A7	0x000000A7	No	1
DES_PKDET	0x1104034	0x000000AC	0x000000AD	Yes	1
DES_RTL_EM	0x1104038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x110403C	0x00000008	0x00000008	No	1
DES_RXPLL_DIV	0x1104040	0x00002219	0x00002219	No	1
DES_TEST_BUS	0x1104044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1104048	0x0000003C	0x0000003C	No	1
DES_RSTPD	0x110404C	0x0000002F	0x0000003F	Yes	N/A
DES_RTL_ERR_CHK	0x1104050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1104054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1104058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x110405C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1104070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1104074	0x00000070	0x00000015	Yes	1
SER_RSTPD	0x1104078	0x00000006	0x00000001	Yes	N/A
SER_DRV_BYP	0x110407C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1104080	0x00008A10	0x00008A10	No	1
SER_RXDET_OUT	0x1104084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1104088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x110408C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1104090	0x00007200	0x00007300	Yes	1
SER_TEST_BUS	0x1104094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1104098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x110409C	0x01000000	0x11000000	Yes	1
SER_DRV_CTRL_SEL	0x11040A0	0x00000000	0x0000000D	Yes	1
SER_DRV_CTRL_M0	0x11040A4	0x001B3423	0x001B240A	Yes	N/A
SER_DRV_CTRL_M1	0x11040A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x11040AC	0x001B1B1B	0x001B0203	Yes	N/A
SER_DRV_CTRL_M3	0x11040B0	0x001B1B14	0x003B1B14	Yes	N/A
SER_DRV_CTRL_M4	0x11040B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x11040B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x11040C0	0x00000100	0x00000000	Yes	1
DES_DFE_CAL_CTRL_0	0x11040D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x11040D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x11040D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x11040DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x11040E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x11040E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x11040E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x11040EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x11040F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x11040F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x11040F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x11040FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1104100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PCS_LANE2 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE3)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x104000	0x00000000	0x00000000	No	N/A
LFWF_R0	0x104004	0x00000000	0x00000000	No	1
LOVR_R0	0x104008	0x00000010	0x00000088	Yes	1
LPIP_R0	0x10400C	0x0000005D	0x00000058	Yes	1
L64_R0	0x104010	0x01400000	0x00000012	Yes	N/A
L64_R1	0x104014	0x00000001	0x00000001	No	N/A
L64_R2	0x104018	0x00000000	0x00000000	No	N/A
L64_R3	0x10401C	0x00000000	0x00000000	No	N/A
L64_R4	0x104020	0x00000000	0x00000000	No	N/A
L64_R5	0x104024	0x00000000	0x00000000	No	N/A
L64_R6	0x104028	0x00000000	0x00000000	No	N/A
L64_R7	0x10402C	0x00000000	0x00000000	No	N/A
L64_R8	0x104030	0x00000000	0x00000000	No	N/A
L64_R9	0x104034	0x00000000	0x00000000	No	N/A
L64_R10	0x104038	0x00000000	0x00000000	No	N/A
L8_R0	0x104040	0x00000000	0x00000000	No	1
LNTV_R0	0x104050	0x00000E0E	0x0000121E	Yes	1
LCLK_R0	0x104058	0x00000000	0x00050E11	Yes	1
LCLK_R1	0x10405C	0x03000000	0x000F0000	Yes	1
LRST_R0	0x104068	0x00000004	0x00000404	Yes	N/A
LRST_OPT	0x10406C	0x00000000	0x00000001	Yes	N/A
OOB_R0	0x104078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x10407C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x104080	0x00000000	0x00000000	No	N/A
OOB_R3	0x104084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x104088	0x03030347	0x03030347	No	1
PMA_CTRL_R1	0x10408C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x104090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x104094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PMA_LANE1 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1102000	0x00000000	0x00000000	No	1
DES_CDR_CTRL_1	0x1102004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1102008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x110200C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1102010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1102014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1102018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1102020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1102024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1102028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x110202C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1102030	0x000000A7	0x000000A7	No	1
DES_PKDET	0x1102034	0x000000AC	0x000000AD	Yes	1
DES_RTL_EM	0x1102038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x110203C	0x00000008	0x00000008	No	1
DES_RXPLL_DIV	0x1102040	0x00002219	0x00002219	No	1
DES_TEST_BUS	0x1102044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1102048	0x0000003C	0x0000003C	No	1
DES_RSTPD	0x110204C	0x0000002F	0x0000003F	Yes	N/A
DES_RTL_ERR_CHK	0x1102050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1102054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1102058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x110205C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1102070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1102074	0x00000070	0x00000015	Yes	1
SER_RSTPD	0x1102078	0x00000006	0x00000001	Yes	N/A
SER_DRV_BYP	0x110207C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1102080	0x00008A10	0x00008A10	No	1
SER_RXDET_OUT	0x1102084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1102088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x110208C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1102090	0x00007200	0x00007300	Yes	1
SER_TEST_BUS	0x1102094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1102098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x110209C	0x01000000	0x11000000	Yes	1
SER_DRV_CTRL_SEL	0x11020A0	0x00000000	0x0000000D	Yes	1
SER_DRV_CTRL_M0	0x11020A4	0x001B3423	0x001B240A	Yes	N/A
SER_DRV_CTRL_M1	0x11020A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x11020AC	0x001B1B1B	0x001B0203	Yes	N/A
SER_DRV_CTRL_M3	0x11020B0	0x001B1B14	0x003B1B14	Yes	N/A
SER_DRV_CTRL_M4	0x11020B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x11020B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x11020C0	0x00000100	0x00000000	Yes	1
DES_DFE_CAL_CTRL_0	0x11020D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x11020D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x11020D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x11020DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x11020E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x11020E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x11020E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x11020EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x11020F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x11020F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x11020F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x11020FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1102100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PCS_LANE1 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE2)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x102000	0x00000000	0x00000000	No	N/A
LFWF_R0	0x102004	0x00000000	0x00000000	No	1
LOVR_R0	0x102008	0x00000010	0x00000088	Yes	1
LPIP_R0	0x10200C	0x0000005D	0x00000058	Yes	1
L64_R0	0x102010	0x01400000	0x00000012	Yes	N/A
L64_R1	0x102014	0x00000001	0x00000001	No	N/A
L64_R2	0x102018	0x00000000	0x00000000	No	N/A
L64_R3	0x10201C	0x00000000	0x00000000	No	N/A
L64_R4	0x102020	0x00000000	0x00000000	No	N/A
L64_R5	0x102024	0x00000000	0x00000000	No	N/A
L64_R6	0x102028	0x00000000	0x00000000	No	N/A
L64_R7	0x10202C	0x00000000	0x00000000	No	N/A
L64_R8	0x102030	0x00000000	0x00000000	No	N/A
L64_R9	0x102034	0x00000000	0x00000000	No	N/A
L64_R10	0x102038	0x00000000	0x00000000	No	N/A
L8_R0	0x102040	0x00000000	0x00000000	No	1
LNTV_R0	0x102050	0x00000E0E	0x0000121E	Yes	1
LCLK_R0	0x102058	0x00000000	0x00050E11	Yes	1
LCLK_R1	0x10205C	0x03000000	0x000F0000	Yes	1
LRST_R0	0x102068	0x00000004	0x00000404	Yes	N/A
LRST_OPT	0x10206C	0x00000000	0x00000001	Yes	N/A
OOB_R0	0x102078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x10207C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x102080	0x00000000	0x00000000	No	N/A
OOB_R3	0x102084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x102088	0x03030347	0x03030347	No	1
PMA_CTRL_R1	0x10208C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x102090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x102094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PMA_LANE3 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1108000	0x00000000	0x00000000	No	1
DES_CDR_CTRL_1	0x1108004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1108008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x110800C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1108010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1108014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1108018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1108020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1108024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1108028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x110802C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1108030	0x000000A7	0x000000A7	No	1
DES_PKDET	0x1108034	0x000000AC	0x000000AD	Yes	1
DES_RTL_EM	0x1108038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x110803C	0x00000008	0x00000008	No	1
DES_RXPLL_DIV	0x1108040	0x00002219	0x00002219	No	1
DES_TEST_BUS	0x1108044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1108048	0x0000003C	0x0000003C	No	1
DES_RSTPD	0x110804C	0x0000002F	0x0000003F	Yes	N/A
DES_RTL_ERR_CHK	0x1108050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1108054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1108058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x110805C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1108070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1108074	0x00000070	0x00000015	Yes	1
SER_RSTPD	0x1108078	0x00000006	0x00000001	Yes	N/A
SER_DRV_BYP	0x110807C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1108080	0x00008A10	0x00008A10	No	1
SER_RXDET_OUT	0x1108084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1108088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x110808C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1108090	0x00007200	0x00007300	Yes	1
SER_TEST_BUS	0x1108094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1108098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x110809C	0x01000000	0x11000000	Yes	1
SER_DRV_CTRL_SEL	0x11080A0	0x00000000	0x0000000D	Yes	1
SER_DRV_CTRL_M0	0x11080A4	0x001B3423	0x001B240A	Yes	N/A
SER_DRV_CTRL_M1	0x11080A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x11080AC	0x001B1B1B	0x001B0203	Yes	N/A
SER_DRV_CTRL_M3	0x11080B0	0x001B1B14	0x003B1B14	Yes	N/A
SER_DRV_CTRL_M4	0x11080B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x11080B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x11080C0	0x00000100	0x00000000	Yes	1
DES_DFE_CAL_CTRL_0	0x11080D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x11080D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x11080D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x11080DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x11080E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x11080E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x11080E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x11080EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x11080F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x11080F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x11080F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x11080FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1108100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PCS_LANE3 (DDR4_RD_WR_inst_0/PF_XCVR_ERM_C0_0/I_XCVR/LANE0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x108000	0x00000000	0x00000000	No	N/A
LFWF_R0	0x108004	0x00000000	0x00000000	No	1
LOVR_R0	0x108008	0x00000010	0x00000088	Yes	1
LPIP_R0	0x10800C	0x0000005D	0x00000058	Yes	1
L64_R0	0x108010	0x01400000	0x00000012	Yes	N/A
L64_R1	0x108014	0x00000001	0x00000001	No	N/A
L64_R2	0x108018	0x00000000	0x00000000	No	N/A
L64_R3	0x10801C	0x00000000	0x00000000	No	N/A
L64_R4	0x108020	0x00000000	0x00000000	No	N/A
L64_R5	0x108024	0x00000000	0x00000000	No	N/A
L64_R6	0x108028	0x00000000	0x00000000	No	N/A
L64_R7	0x10802C	0x00000000	0x00000000	No	N/A
L64_R8	0x108030	0x00000000	0x00000000	No	N/A
L64_R9	0x108034	0x00000000	0x00000000	No	N/A
L64_R10	0x108038	0x00000000	0x00000000	No	N/A
L8_R0	0x108040	0x00000000	0x00000000	No	1
LNTV_R0	0x108050	0x00000E0E	0x0000121E	Yes	1
LCLK_R0	0x108058	0x00000000	0x00050E11	Yes	1
LCLK_R1	0x10805C	0x03000000	0x000F0000	Yes	1
LRST_R0	0x108068	0x00000004	0x00000404	Yes	N/A
LRST_OPT	0x10806C	0x00000000	0x00000001	Yes	N/A
OOB_R0	0x108078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x10807C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x108080	0x00000000	0x00000000	No	N/A
OOB_R3	0x108084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x108088	0x03030347	0x03030347	No	1
PMA_CTRL_R1	0x10808C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x108090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x108094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PCSCMN

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x110000	0x00000000	0x00000000	No	1
GSSCLK_CTRL	0x110004	0x00000000	0x00000000	No	1
QRST_R0	0x110008	0x00000000	0x00000000	No	1
QDBG_R0	0x11000C	0x00001000	0x00000000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_PMA_CMN (CLOCKS_AND_RESETS_inst_0/PF_TX_PLL_C0_0/PF_TX_PLL_C0_0/txpll_isnt_0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1110000	0x00000000	0x00000000	No	1
TXPLL_CLKBUF	0x1110004	0x00000000	0x00000000	No	1
TXPLL_CTRL	0x1110008	0x00E60010	0x00800010	Yes	1
TXPLL_CLK_SEL	0x111000C	0x3F3F1C03	0x3F3F0305	Yes	1
TXPLL_DIV_1	0x1110010	0x00190019	0x0014000C	Yes	1
TXPLL_DIV_2	0x1110014	0x01000001	0x01000000	Yes	1
TXPLL_JA_1	0x1110018	0x00640064	0x00640064	No	N/A
TXPLL_JA_2	0x111001C	0x00000064	0x00000064	No	N/A
TXPLL_JA_3	0x1110020	0x00640064	0x00640064	No	N/A
TXPLL_JA_4	0x1110024	0x01010001	0x01010001	No	N/A
TXPLL_JA_5	0x1110028	0x01010101	0x01010101	No	N/A
TXPLL_JA_6	0x111002C	0x01010101	0x01010101	No	N/A
TXPLL_JA_7	0x1110030	0x07000001	0x07000001	No	N/A
TXPLL_JA_8	0x1110034	0x00000000	0x00000000	No	N/A
TXPLL_JA_9	0x1110038	0x00180014	0x00180014	No	N/A
TXPLL_JA_10	0x111003C	0x00000000	0x00000000	No	N/A
TXPLL_JA_RST	0x1110040	0x00000055	0x00000055	No	N/A
SERDES_SSMOD	0x1110044	0x007F0102	0x007F0102	No	N/A
SERDES_RTERM	0x1110050	0x000D0703	0x000D0703	No	N/A
SERDES_RTT	0x1110054	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_MAIN

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2110000	0x00000000	0x00000000	No	1
SPARE	0x2110190	0x00000000	0x00F00000	Yes	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PMA_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1208000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1208004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1208008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x120800C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1208010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1208014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1208018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1208020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1208024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1208028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x120802C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1208030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1208034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1208038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x120803C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1208040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1208044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1208048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x120804C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1208050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1208054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1208058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x120805C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1208070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1208074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1208078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x120807C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1208080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1208084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1208088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x120808C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1208090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1208094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1208098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x120809C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x12080A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x12080A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x12080A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x12080AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x12080B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x12080B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x12080B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x12080C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x12080D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x12080D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x12080D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x12080DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x12080E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x12080E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x12080E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x12080EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x12080F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x12080F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x12080F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x12080FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1208100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PCS_LANE3 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x208000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x208004	0x00000000	0x00000000	No	1
LOVR_R0	0x208008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x20800C	0x0000005D	0x00000058	Yes	1
L64_R0	0x208010	0x01400000	0x01400000	No	N/A
L64_R1	0x208014	0x00000001	0x00000001	No	N/A
L64_R2	0x208018	0x00000000	0x00000000	No	N/A
L64_R3	0x20801C	0x00000000	0x00000000	No	N/A
L64_R4	0x208020	0x00000000	0x00000000	No	N/A
L64_R5	0x208024	0x00000000	0x00000000	No	N/A
L64_R6	0x208028	0x00000000	0x00000000	No	N/A
L64_R7	0x20802C	0x00000000	0x00000000	No	N/A
L64_R8	0x208030	0x00000000	0x00000000	No	N/A
L64_R9	0x208034	0x00000000	0x00000000	No	N/A
L64_R10	0x208038	0x00000000	0x00000000	No	N/A
L8_R0	0x208040	0x00000000	0x00000000	No	1
LNTV_R0	0x208050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x208058	0x00000000	0x00000000	No	1
LCLK_R1	0x20805C	0x03000000	0x00000000	Yes	1
LRST_R0	0x208068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x20806C	0x00000000	0x00000000	No	N/A
OOB_R0	0x208078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x20807C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x208080	0x00000000	0x00000000	No	N/A
OOB_R3	0x208084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x208088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x20808C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x208090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x208094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PCSCMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x210000	0x00000000	0x00000000	No	1
GSSCLK_CTRL	0x210004	0x00000000	0x00000000	No	1
QRST_R0	0x210008	0x00000000	0x00000000	No	1
QDBG_R0	0x21000C	0x00001000	0x00000000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PMA_CMN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1210000	0x00000000	0x00000000	No	1
TXPLL_CLKBUF	0x1210004	0x00000000	0x00000000	No	1
TXPLL_CTRL	0x1210008	0x00E60010	0x00E60010	No	1
TXPLL_CLK_SEL	0x121000C	0x3F3F1C03	0x3F3F0000	Yes	1
TXPLL_DIV_1	0x1210010	0x00190019	0x00000000	Yes	1
TXPLL_DIV_2	0x1210014	0x01000001	0x00000000	Yes	1
TXPLL_JA_1	0x1210018	0x00640064	0x00640064	No	N/A
TXPLL_JA_2	0x121001C	0x00000064	0x00000064	No	N/A
TXPLL_JA_3	0x1210020	0x00640064	0x00640064	No	N/A
TXPLL_JA_4	0x1210024	0x01010001	0x01010001	No	N/A
TXPLL_JA_5	0x1210028	0x01010101	0x01010101	No	N/A
TXPLL_JA_6	0x121002C	0x01010101	0x01010101	No	N/A
TXPLL_JA_7	0x1210030	0x07000001	0x07000001	No	N/A
TXPLL_JA_8	0x1210034	0x00000000	0x00000000	No	N/A
TXPLL_JA_9	0x1210038	0x00180014	0x00180014	No	N/A
TXPLL_JA_10	0x121003C	0x00000000	0x00000000	No	N/A
TXPLL_JA_RST	0x1210040	0x00000055	0x00000055	No	N/A
SERDES_SSMOD	0x1210044	0x007F0102	0x007F0102	No	N/A
SERDES_RTERM	0x1210050	0x000D0703	0x000D0703	No	N/A
SERDES_RTT	0x1210054	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_MAIN (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x2210000	0x00000000	0x00000000	No	1
SPARE	0x2210190	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PMA_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1202000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1202004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1202008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x120200C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1202010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1202014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1202018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1202020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1202024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1202028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x120202C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1202030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1202034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1202038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x120203C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1202040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1202044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1202048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x120204C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1202050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1202054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1202058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x120205C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1202070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1202074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1202078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x120207C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1202080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1202084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1202088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x120208C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1202090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1202094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1202098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x120209C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x12020A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x12020A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x12020A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x12020AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x12020B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x12020B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x12020B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x12020C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x12020D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x12020D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x12020D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x12020DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x12020E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x12020E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x12020E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x12020EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x12020F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x12020F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x12020F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x12020FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1202100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PCS_LANE1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x202000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x202004	0x00000000	0x00000000	No	1
LOVR_R0	0x202008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x20200C	0x0000005D	0x00000058	Yes	1
L64_R0	0x202010	0x01400000	0x01400000	No	N/A
L64_R1	0x202014	0x00000001	0x00000001	No	N/A
L64_R2	0x202018	0x00000000	0x00000000	No	N/A
L64_R3	0x20201C	0x00000000	0x00000000	No	N/A
L64_R4	0x202020	0x00000000	0x00000000	No	N/A
L64_R5	0x202024	0x00000000	0x00000000	No	N/A
L64_R6	0x202028	0x00000000	0x00000000	No	N/A
L64_R7	0x20202C	0x00000000	0x00000000	No	N/A
L64_R8	0x202030	0x00000000	0x00000000	No	N/A
L64_R9	0x202034	0x00000000	0x00000000	No	N/A
L64_R10	0x202038	0x00000000	0x00000000	No	N/A
L8_R0	0x202040	0x00000000	0x00000000	No	1
LNTV_R0	0x202050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x202058	0x00000000	0x00000000	No	1
LCLK_R1	0x20205C	0x03000000	0x00000000	Yes	1
LRST_R0	0x202068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x20206C	0x00000000	0x00000000	No	N/A
OOB_R0	0x202078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x20207C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x202080	0x00000000	0x00000000	No	N/A
OOB_R3	0x202084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x202088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x20208C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x202090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x202094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PMA_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1204000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1204004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1204008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x120400C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1204010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1204014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1204018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1204020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1204024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1204028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x120402C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1204030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1204034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1204038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x120403C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1204040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1204044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1204048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x120404C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1204050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1204054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1204058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x120405C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1204070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1204074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1204078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x120407C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1204080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1204084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1204088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x120408C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1204090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1204094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1204098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x120409C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x12040A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x12040A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x12040A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x12040AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x12040B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x12040B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x12040B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x12040C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x12040D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x12040D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x12040D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x12040DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x12040E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x12040E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x12040E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x12040EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x12040F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x12040F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x12040F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x12040FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1204100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PCS_LANE2 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x204000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x204004	0x00000000	0x00000000	No	1
LOVR_R0	0x204008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x20400C	0x0000005D	0x00000058	Yes	1
L64_R0	0x204010	0x01400000	0x01400000	No	N/A
L64_R1	0x204014	0x00000001	0x00000001	No	N/A
L64_R2	0x204018	0x00000000	0x00000000	No	N/A
L64_R3	0x20401C	0x00000000	0x00000000	No	N/A
L64_R4	0x204020	0x00000000	0x00000000	No	N/A
L64_R5	0x204024	0x00000000	0x00000000	No	N/A
L64_R6	0x204028	0x00000000	0x00000000	No	N/A
L64_R7	0x20402C	0x00000000	0x00000000	No	N/A
L64_R8	0x204030	0x00000000	0x00000000	No	N/A
L64_R9	0x204034	0x00000000	0x00000000	No	N/A
L64_R10	0x204038	0x00000000	0x00000000	No	N/A
L8_R0	0x204040	0x00000000	0x00000000	No	1
LNTV_R0	0x204050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x204058	0x00000000	0x00000000	No	1
LCLK_R1	0x20405C	0x03000000	0x00000000	Yes	1
LRST_R0	0x204068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x20406C	0x00000000	0x00000000	No	N/A
OOB_R0	0x204078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x20407C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x204080	0x00000000	0x00000000	No	N/A
OOB_R3	0x204084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x204088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x20408C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x204090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x204094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PMA_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x1201000	0x00000000	0x00000100	Yes	1
DES_CDR_CTRL_1	0x1201004	0x00000000	0x00000000	No	N/A
DES_CDR_CTRL_2	0x1201008	0x00000015	0x00000015	No	N/A
DES_CDR_CTRL_3	0x120100C	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_1	0x1201010	0x00000015	0x00000015	No	N/A
DES_DFEEM_CTRL_2	0x1201014	0x00000000	0x00000000	No	N/A
DES_DFEEM_CTRL_3	0x1201018	0x00000000	0x00000000	No	1
DES_DFE_CTRL_1	0x1201020	0x00000000	0x00000000	No	N/A
DES_DFE_CTRL_2	0x1201024	0x00000000	0x00000000	No	1
DES_EM_CTRL_1	0x1201028	0x00000000	0x00000000	No	N/A
DES_EM_CTRL_2	0x120102C	0x00000000	0x00000000	No	1
DES_IN_TERM	0x1201030	0x000000A7	0x00000010	Yes	1
DES_PKDET	0x1201034	0x000000AC	0x00000000	Yes	1
DES_RTL_EM	0x1201038	0x000000C8	0x000000C8	No	N/A
DES_RTL_LOCK_CTRL	0x120103C	0x00000008	0x00000000	Yes	1
DES_RXPLL_DIV	0x1201040	0x00002219	0x00000000	Yes	1
DES_TEST_BUS	0x1201044	0x00000000	0x00000000	No	1
DES_CLK_CTRL	0x1201048	0x0000003C	0x00000007	Yes	1
DES_RSTPD	0x120104C	0x0000002F	0x0000002F	No	N/A
DES_RTL_ERR_CHK	0x1201050	0x00000000	0x00000000	No	N/A
DES_PCIE1_2_RXPLL_DIV	0x1201054	0x02322219	0x02322219	No	N/A
DES_SATA1_2_RXPLL_DIV	0x1201058	0x22184418	0x22184418	No	N/A
DES_SATA3_RXPLL_DIV	0x120105C	0x00000230	0x00000230	No	N/A
SER_CTRL	0x1201070	0x00000000	0x00000000	No	1
SER_CLK_CTRL	0x1201074	0x00000070	0x00000000	Yes	1
SER_RSTPD	0x1201078	0x00000006	0x00000006	No	N/A
SER_DRV_BYP	0x120107C	0x00000000	0x00000000	No	1
SER_RXDET_CTRL	0x1201080	0x00008A10	0x00008A00	Yes	1
SER_RXDET_OUT	0x1201084	0x00000000	0x00000000	No	N/A
SER_STATIC_LSB	0x1201088	0x00000000	0x00000000	No	N/A
SER_STATIC_MSB	0x120108C	0x00000000	0x00000000	No	N/A
SER_TERM_CTRL	0x1201090	0x00007200	0x00000100	Yes	1
SER_TEST_BUS	0x1201094	0xE0000000	0xE0000000	No	1
SER_DRV_DATA_CTRL	0x1201098	0x00000000	0x00000000	No	1
SER_DRV_CTRL	0x120109C	0x01000000	0x00000000	Yes	1
SER_DRV_CTRL_SEL	0x12010A0	0x00000000	0x00000000	No	1
SER_DRV_CTRL_M0	0x12010A4	0x001B3423	0x001B3423	No	N/A
SER_DRV_CTRL_M1	0x12010A8	0x00232C27	0x00232C27	No	N/A
SER_DRV_CTRL_M2	0x12010AC	0x001B1B1B	0x001B1B1B	No	N/A
SER_DRV_CTRL_M3	0x12010B0	0x001B1B14	0x001B1B14	No	N/A
SER_DRV_CTRL_M4	0x12010B4	0x00240C0A	0x00240C0A	No	N/A
SER_DRV_CTRL_M5	0x12010B8	0x1B383B38	0x1B383B38	No	N/A
SERDES_RTL_CTRL	0x12010C0	0x00000100	0x00000100	No	1
DES_DFE_CAL_CTRL_0	0x12010D0	0x64100702	0x64100702	No	N/A
DES_DFE_CAL_CTRL_1	0x12010D4	0x01034018	0x01034018	No	N/A
DES_DFE_CAL_CTRL_2	0x12010D8	0x00800000	0x00800000	No	N/A
DES_DFE_CAL_CMD	0x12010DC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_BYPASS	0x12010E0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_EYE_DATA	0x12010E4	0x00000000	0x00000000	No	N/A
DES_DFE_CDRH0_MON	0x12010E8	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_0	0x12010EC	0x00000000	0x00000000	No	N/A
DES_DFE_COEFF_MON_1	0x12010F0	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_OS_MON	0x12010F4	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_0	0x12010F8	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_ST_1	0x12010FC	0x00000000	0x00000000	No	N/A
DES_DFE_CAL_FLAG	0x1201100	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_PCS_LANE0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x201000	0x00000000	0x00000100	Yes	N/A
LFWF_R0	0x201004	0x00000000	0x00000000	No	1
LOVR_R0	0x201008	0x00000010	0x00000000	Yes	1
LPIP_R0	0x20100C	0x0000005D	0x00000058	Yes	1
L64_R0	0x201010	0x01400000	0x01400000	No	N/A
L64_R1	0x201014	0x00000001	0x00000001	No	N/A
L64_R2	0x201018	0x00000000	0x00000000	No	N/A
L64_R3	0x20101C	0x00000000	0x00000000	No	N/A
L64_R4	0x201020	0x00000000	0x00000000	No	N/A
L64_R5	0x201024	0x00000000	0x00000000	No	N/A
L64_R6	0x201028	0x00000000	0x00000000	No	N/A
L64_R7	0x20102C	0x00000000	0x00000000	No	N/A
L64_R8	0x201030	0x00000000	0x00000000	No	N/A
L64_R9	0x201034	0x00000000	0x00000000	No	N/A
L64_R10	0x201038	0x00000000	0x00000000	No	N/A
L8_R0	0x201040	0x00000000	0x00000000	No	1
LNTV_R0	0x201050	0x00000E0E	0x00000000	Yes	1
LCLK_R0	0x201058	0x00000000	0x00000000	No	1
LCLK_R1	0x20105C	0x03000000	0x00000000	Yes	1
LRST_R0	0x201068	0x00000004	0x00000004	No	N/A
LRST_OPT	0x20106C	0x00000000	0x00000000	No	N/A
OOB_R0	0x201078	0x110F110F	0x110F110F	No	N/A
OOB_R1	0x20107C	0x9888332D	0x9888332D	No	N/A
OOB_R2	0x201080	0x00000000	0x00000000	No	N/A
OOB_R3	0x201084	0x00000000	0x00000000	No	N/A
PMA_CTRL_R0	0x201088	0x03030347	0x03030300	Yes	1
PMA_CTRL_R1	0x20108C	0x000A0640	0x000A0640	No	N/A
PMA_CTRL_R2	0x201090	0x000000A6	0x000000A6	No	N/A
MSTR_CTRL	0x201094	0x00000000	0x00000000	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PLL_NE_0 (CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x8040000	0x00000000	0x00000000	No	N/A
PLL_CTRL	0x8040004	0x0000107C	0x00001087	Yes	N/A
PLL_REF_FB	0x8040008	0x00000000	0x00000100	Yes	N/A
PLL_FRACN	0x804000C	0x00000000	0x00000000	No	N/A
PLL_DIV_0_1	0x8040010	0x00000000	0x01000600	Yes	N/A
PLL_DIV_2_3	0x8040014	0x00000000	0x01000100	Yes	N/A
PLL_CTRL2	0x8040018	0x00001006	0x00000014	Yes	N/A
PLL_CAL	0x804001C	0x00000000	0x0000000E	Yes	N/A
PLL_PHADJ	0x8040020	0x00004001	0x00004000	Yes	N/A
SSCG_REG_0	0x8040024	0x00000000	0x00000001	Yes	N/A
SSCG_REG_1	0x8040028	0x00000000	0x0000000A	Yes	N/A
SSCG_REG_2	0x804002C	0x00000000	0x00000060	Yes	N/A
SSCG_REG_3	0x8040030	0x00000000	0x00000001	Yes	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PLL_SE_0 (CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x8010000	0x00000000	0x00000000	No	N/A
PLL_CTRL	0x8010004	0x0000107C	0x00001087	Yes	N/A
PLL_REF_FB	0x8010008	0x00000000	0x00000100	Yes	N/A
PLL_FRACN	0x801000C	0x00000000	0x00000003	Yes	N/A
PLL_DIV_0_1	0x8010010	0x00000000	0x01001900	Yes	N/A
PLL_DIV_2_3	0x8010014	0x00000000	0x01000100	Yes	N/A
PLL_CTRL2	0x8010018	0x00001006	0x00000014	Yes	N/A
PLL_CAL	0x801001C	0x00000000	0x0000000E	Yes	N/A
PLL_PHADJ	0x8010020	0x00004001	0x00004000	Yes	N/A
SSCG_REG_0	0x8010024	0x00000000	0x2AE21941	Yes	N/A
SSCG_REG_1	0x8010028	0x00000000	0x0000000A	Yes	N/A
SSCG_REG_2	0x801002C	0x00000000	0x00000021	Yes	N/A
SSCG_REG_3	0x8010030	0x00000000	0x00000001	Yes	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

PLL_SE_1 (DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x8020000	0x00000000	0x00000000	No	N/A
PLL_CTRL	0x8020004	0x0000107C	0x00001087	Yes	N/A
PLL_REF_FB	0x8020008	0x00000000	0x00001900	Yes	N/A
PLL_FRACN	0x802000C	0x00000000	0x00000000	No	N/A
PLL_DIV_0_1	0x8020010	0x00000000	0x01000700	Yes	N/A
PLL_DIV_2_3	0x8020014	0x00000000	0x01000100	Yes	N/A
PLL_CTRL2	0x8020018	0x00001006	0x00000014	Yes	N/A
PLL_CAL	0x802001C	0x00000000	0x0000000E	Yes	N/A
PLL_PHADJ	0x8020020	0x00004001	0x00004000	Yes	N/A
SSCG_REG_0	0x8020024	0x00000000	0x00000001	Yes	N/A
SSCG_REG_1	0x8020028	0x00000000	0x0000000A	Yes	N/A
SSCG_REG_2	0x802002C	0x00000000	0x00000770	Yes	N/A
SSCG_REG_3	0x8020030	0x00000000	0x00000001	Yes	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

MSS (MSS/I_MSS)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
CRYPTO_DLL_CTRL0	0x7010004	0x8800000F	0x8810000F	Yes	1
CRYPTO_DLL_CTRL1	0x7010008	0x00000000	0x00000000	No	1
CRYPTO_DLL_STAT0	0x701000C	0x00001801	0x00001800	Yes	1
CRYPTO_CONTROL_USER	0x7010040	0x00000006	0x000000EC	Yes	1
CRYPTO_INTERRUPT_ENABLE	0x701004C	0x00000000	0x00000000	No	1
CRYPTO_MARGIN	0x7010060	0x00000000	0x00000000	No	1
SCB_REGS_DLL0_CTRL0	0x7040200	0x8800000F	0x8810000F	Yes	1
SCB_REGS_DLL0_CTRL1	0x7040204	0x00000000	0x00000000	No	1
SCB_REGS_DLL0_STAT0	0x7040208	0x00001003	0x00001000	Yes	1
SCB_REGS_DLL1_CTRL0	0x7040220	0x8800000F	0x8810000F	Yes	1
SCB_REGS_DLL1_CTRL1	0x7040224	0x00000000	0x00000000	No	1
SCB_REGS_DLL1_STAT0	0x7040228	0x00001003	0x00001000	Yes	1
SCB_REGS_DLL2_CTRL0	0x7040240	0x8800000F	0x88080003	Yes	1
SCB_REGS_DLL2_CTRL1	0x7040244	0x00000000	0x00000080	Yes	1
SCB_REGS_DLL2_STAT0	0x7040248	0x00001003	0x00001002	Yes	1
SCB_REGS_DLL3_CTRL0	0x7040260	0x8800000F	0x88080003	Yes	1
SCB_REGS_DLL3_CTRL1	0x7040264	0x00000000	0x00000080	Yes	1
SCB_REGS_DLL3_STAT0	0x7040268	0x00001003	0x00001002	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_TXPLL0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x4080000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x4080004	0x00000000	0x00000433	Yes	1
EXTPLL_CTRL	0x4080008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x408000C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x4080010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x4080014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x4080018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x408001C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x4080020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x4080024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x4080028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x408002C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x4080030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x4080034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x4080038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x408003C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x4080040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q2_TXPLL1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x4040000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x4040004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x4040008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x404000C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x4040010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x4040014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x4040018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x404001C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x4040020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x4040024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x4040028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x404002C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x4040030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x4040034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x4040038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x404003C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x4040040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_TXPLL0 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x4010000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x4010004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x4010008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x401000C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x4010010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x4010014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x4010018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x401001C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x4010020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x4010024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x4010028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x401002C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x4010030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x4010034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x4010038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x401003C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x4010040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q1_TXPLL1 (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x4020000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x4020004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x4020008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x402000C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x4020010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x4020014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x4020018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x402001C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x4020020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x4020024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x4020028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x402002C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x4020030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x4020034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x4020038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x402003C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x4020040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Q3_TXPLL (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x4100000	0x00000000	0x00000000	No	1
EXTPLL_CLKBUF	0x4100004	0x00000000	0x00000000	No	1
EXTPLL_CTRL	0x4100008	0x00CE0009	0x00CE0000	Yes	1
EXTPLL_CLK_SEL	0x410000C	0x00001F00	0x00000000	Yes	1
EXTPLL_DIV_1	0x4100010	0x00140014	0x00000000	Yes	1
EXTPLL_DIV_2	0x4100014	0x01000001	0x00000000	Yes	1
EXTPLL_JA_1	0x4100018	0x00640064	0x00640064	No	N/A
EXTPLL_JA_2	0x410001C	0x00000064	0x00000064	No	N/A
EXTPLL_JA_3	0x4100020	0x000A0064	0x000A0064	No	N/A
EXTPLL_JA_4	0x4100024	0x0101000F	0x0101000F	No	N/A
EXTPLL_JA_5	0x4100028	0x01010101	0x01010101	No	N/A
EXTPLL_JA_6	0x410002C	0x01010101	0x01010101	No	N/A
EXTPLL_JA_7	0x4100030	0x07000001	0x07000001	No	N/A
EXTPLL_JA_8	0x4100034	0x00000000	0x00000000	No	N/A
EXTPLL_JA_9	0x4100038	0x00180014	0x00180014	No	N/A
EXTPLL_JA_10	0x410003C	0x00000000	0x00000000	No	N/A
EXTPLL_JA_RST	0x4100040	0x00000055	0x00000055	No	N/A

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

G5SOC_CONTROL_TVS (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
SOFT_RESET	0x7020000	0x00000100	0x00000000	Yes	1
TVS_CONTROL	0x7020008	0x00000000	0x00000020	Yes	1
TVS_TRIGGER	0x702002C	0x00000000	0xFFFF0000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

G5SOC_CONTROL_VOLTAGEDETECT (Unused)

Register Name	Address	Silicon Default Value	Configured Value	Modified	Lock Value(*)
VDETECTOR	0x7020004	0x00000007	0x00000000	Yes	1

Note: (*) Lock Value = 0, disables modification of the Register. Lock Value = N/A, locking does not apply to the Register.

Block-Level Control For Locking Peripheral Blocks.

Peripheral Block Name	Name For Locking The Block	Instance Name	Lock Value(*)
CCC PLL	PLL_NE_0_LOCK	CLOCKS_AND_RESETS_inst_0/PF_CCC_C1_0/PF_CCC_C1_0/pll_inst_0	1
CCC PLL	PLL_NE_1_LOCK	N/A	1
CCC PLL	PLL_NW_0_LOCK	N/A	1
CCC PLL	PLL_NW_1_LOCK	N/A	1
CCC PLL	PLL_SE_0_LOCK	CLOCKS_AND_RESETS_inst_0/PF_CCC_C0_0/PF_CCC_C0_0/pll_inst_0	1
CCC PLL	PLL_SE_1_LOCK	DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_CCC_C2_0/PF_CCC_C2_0/pll_inst_0	1
CCC PLL	PLL_SW_0_LOCK	N/A	1
CCC PLL	PLL_SW_1_LOCK	N/A	1
CCC DLL	DLL_NE_0_LOCK	N/A	1
CCC DLL	DLL_NE_1_LOCK	N/A	1
CCC DLL	DLL_NW_0_LOCK	N/A	1
CCC DLL	DLL_NW_1_LOCK	N/A	1
CCC DLL	DLL_SE_0_LOCK	N/A	1
CCC DLL	DLL_SE_1_LOCK	N/A	1
CCC DLL	DLL_SW_0_LOCK	N/A	1
CCC DLL	DLL_SW_1_LOCK	N/A	1
Lane Controller	LANECTRL_N_0_LOCK	N/A	1
Lane Controller	LANECTRL_N_10_LOCK	N/A	1
Lane Controller	LANECTRL_N_11_LOCK	N/A	1
Lane Controller	LANECTRL_N_1_LOCK	N/A	1
Lane Controller	LANECTRL_N_2_LOCK	N/A	1
Lane Controller	LANECTRL_N_3_LOCK	N/A	1
Lane Controller	LANECTRL_N_4_LOCK	N/A	1
Lane Controller	LANECTRL_N_5_LOCK	N/A	1
Lane Controller	LANECTRL_N_6_LOCK	N/A	1
Lane Controller	LANECTRL_N_7_LOCK	N/A	1
Lane Controller	LANECTRL_N_8_LOCK	N/A	1
Lane Controller	LANECTRL_N_9_LOCK	N/A	1
Lane Controller	LANECTRL_S_0_LOCK	N/A	1
Lane Controller	LANECTRL_S_10_LOCK	N/A	1
Lane Controller	LANECTRL_S_11_LOCK	N/A	1
Lane Controller	LANECTRL_S_12_LOCK	N/A	1
Lane Controller	LANECTRL_S_13_LOCK	N/A	1
Lane Controller	LANECTRL_S_1_LOCK	N/A	1
Lane Controller	LANECTRL_S_2_LOCK	N/A	1
Lane Controller	LANECTRL_S_3_LOCK	N/A	1
Lane Controller	LANECTRL_S_4_LOCK	N/A	1
Lane Controller	LANECTRL_S_5_LOCK	N/A	1
Lane Controller	LANECTRL_S_6_LOCK	N/A	1
Lane Controller	LANECTRL_S_7_LOCK	N/A	1
Lane Controller	LANECTRL_S_8_LOCK	N/A	1
Lane Controller	LANECTRL_S_9_LOCK	N/A	1
Lane Controller	LANECTRL_W_0_LOCK	DDR4_RD_WR_inst_0/IMX334_IF_TOP_0/PF_IOD_GENERIC_RX_C0_0/PF_IOD_0/PF_LANECTRL_0/I_LANECTRL	0
Lane Controller	LANECTRL_W_1_LOCK	N/A	1
Lane Controller	LANECTRL_W_2_LOCK	N/A	1
Lane Controller	LANECTRL_W_3_LOCK	N/A	1
Lane Controller	LANECTRL_W_4_LOCK	N/A	1
Corner CFM	CRNCOMMON_NE_LOCK	N/A	1
Corner CFM	CRNCOMMON_NW_LOCK	N/A	1
Corner CFM	CRNCOMMON_SE_LOCK	N/A	1
Corner CFM	CRNCOMMON_SW_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_E_0_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_NE_0_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_NW_0_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_SE_0_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_SW_0_LOCK	N/A	1
IOCALIB / BNKCTRL / Clock Controls	ICBMUXINGPC_W_0_LOCK	N/A	1
IOCALIB / BNKCTRL	VREFBANKDYNPC_NE_H_LOCK	N/A	1
IOCALIB / BNKCTRL	VREFBANKDYNPC_NW_V_LOCK	N/A	1
IOCALIB / BNKCTRL	VREFBANKDYNPC_SW_H_LOCK	N/A	1

Note: (*) Lock Value = 0, disables modification of the Peripheral Block.

Q1_GPSS_COMMON (Unused pin tie-off)

Input Pin	Tie-Off
PCS_DEBUG_0[0]	1
PCS_DEBUG_0[10]	1
PCS_DEBUG_0[11]	1
PCS_DEBUG_0[12]	1
PCS_DEBUG_0[13]	1
PCS_DEBUG_0[14]	1
PCS_DEBUG_0[15]	1
PCS_DEBUG_0[16]	1
PCS_DEBUG_0[17]	1
PCS_DEBUG_0[18]	1
PCS_DEBUG_0[19]	1
PCS_DEBUG_0[1]	1
PCS_DEBUG_0[2]	1
PCS_DEBUG_0[3]	1
PCS_DEBUG_0[4]	1
PCS_DEBUG_0[5]	1
PCS_DEBUG_0[6]	1
PCS_DEBUG_0[7]	1
PCS_DEBUG_0[8]	1
PCS_DEBUG_0[9]	1
PCS_DEBUG_1[0]	1
PCS_DEBUG_1[10]	1
PCS_DEBUG_1[11]	1
PCS_DEBUG_1[12]	1
PCS_DEBUG_1[13]	1
PCS_DEBUG_1[14]	1
PCS_DEBUG_1[15]	1
PCS_DEBUG_1[16]	1
PCS_DEBUG_1[17]	1
PCS_DEBUG_1[18]	1
PCS_DEBUG_1[19]	1
PCS_DEBUG_1[1]	1
PCS_DEBUG_1[2]	1
PCS_DEBUG_1[3]	1
PCS_DEBUG_1[4]	1
PCS_DEBUG_1[5]	1
PCS_DEBUG_1[6]	1
PCS_DEBUG_1[7]	1
PCS_DEBUG_1[8]	1
PCS_DEBUG_1[9]	1
PCS_DEBUG_2[0]	1
PCS_DEBUG_2[10]	1
PCS_DEBUG_2[11]	1
PCS_DEBUG_2[12]	1
PCS_DEBUG_2[13]	1
PCS_DEBUG_2[14]	1
PCS_DEBUG_2[15]	1
PCS_DEBUG_2[16]	1
PCS_DEBUG_2[17]	1
PCS_DEBUG_2[18]	1
PCS_DEBUG_2[19]	1
PCS_DEBUG_2[1]	1
PCS_DEBUG_2[2]	1
PCS_DEBUG_2[3]	1
PCS_DEBUG_2[4]	1
PCS_DEBUG_2[5]	1
PCS_DEBUG_2[6]	1
PCS_DEBUG_2[7]	1
PCS_DEBUG_2[8]	1
PCS_DEBUG_2[9]	1
PCS_DEBUG_3[0]	1
PCS_DEBUG_3[10]	1
PCS_DEBUG_3[11]	1
PCS_DEBUG_3[12]	1
PCS_DEBUG_3[13]	1
PCS_DEBUG_3[14]	1
PCS_DEBUG_3[15]	1
PCS_DEBUG_3[16]	1
PCS_DEBUG_3[17]	1
PCS_DEBUG_3[18]	1
PCS_DEBUG_3[19]	1
PCS_DEBUG_3[1]	1
PCS_DEBUG_3[2]	1
PCS_DEBUG_3[3]	1
PCS_DEBUG_3[4]	1
PCS_DEBUG_3[5]	1
PCS_DEBUG_3[6]	1
PCS_DEBUG_3[7]	1
PCS_DEBUG_3[8]	1
PCS_DEBUG_3[9]	1
PMA_DEBUG_0	1
PMA_DEBUG_1	1
PMA_DEBUG_2	1
PMA_DEBUG_3	1

Q2_GPSS_COMMON (Unused pin tie-off)

Input Pin	Tie-Off
PCS_DEBUG_0[0]	1
PCS_DEBUG_0[10]	1
PCS_DEBUG_0[11]	1
PCS_DEBUG_0[12]	1
PCS_DEBUG_0[13]	1
PCS_DEBUG_0[14]	1
PCS_DEBUG_0[15]	1
PCS_DEBUG_0[16]	1
PCS_DEBUG_0[17]	1
PCS_DEBUG_0[18]	1
PCS_DEBUG_0[19]	1
PCS_DEBUG_0[1]	1
PCS_DEBUG_0[2]	1
PCS_DEBUG_0[3]	1
PCS_DEBUG_0[4]	1
PCS_DEBUG_0[5]	1
PCS_DEBUG_0[6]	1
PCS_DEBUG_0[7]	1
PCS_DEBUG_0[8]	1
PCS_DEBUG_0[9]	1
PCS_DEBUG_1[0]	1
PCS_DEBUG_1[10]	1
PCS_DEBUG_1[11]	1
PCS_DEBUG_1[12]	1
PCS_DEBUG_1[13]	1
PCS_DEBUG_1[14]	1
PCS_DEBUG_1[15]	1
PCS_DEBUG_1[16]	1
PCS_DEBUG_1[17]	1
PCS_DEBUG_1[18]	1
PCS_DEBUG_1[19]	1
PCS_DEBUG_1[1]	1
PCS_DEBUG_1[2]	1
PCS_DEBUG_1[3]	1
PCS_DEBUG_1[4]	1
PCS_DEBUG_1[5]	1
PCS_DEBUG_1[6]	1
PCS_DEBUG_1[7]	1
PCS_DEBUG_1[8]	1
PCS_DEBUG_1[9]	1
PCS_DEBUG_2[0]	1
PCS_DEBUG_2[10]	1
PCS_DEBUG_2[11]	1
PCS_DEBUG_2[12]	1
PCS_DEBUG_2[13]	1
PCS_DEBUG_2[14]	1
PCS_DEBUG_2[15]	1
PCS_DEBUG_2[16]	1
PCS_DEBUG_2[17]	1
PCS_DEBUG_2[18]	1
PCS_DEBUG_2[19]	1
PCS_DEBUG_2[1]	1
PCS_DEBUG_2[2]	1
PCS_DEBUG_2[3]	1
PCS_DEBUG_2[4]	1
PCS_DEBUG_2[5]	1
PCS_DEBUG_2[6]	1
PCS_DEBUG_2[7]	1
PCS_DEBUG_2[8]	1
PCS_DEBUG_2[9]	1
PCS_DEBUG_3[0]	1
PCS_DEBUG_3[10]	1
PCS_DEBUG_3[11]	1
PCS_DEBUG_3[12]	1
PCS_DEBUG_3[13]	1
PCS_DEBUG_3[14]	1
PCS_DEBUG_3[15]	1
PCS_DEBUG_3[16]	1
PCS_DEBUG_3[17]	1
PCS_DEBUG_3[18]	1
PCS_DEBUG_3[19]	1
PCS_DEBUG_3[1]	1
PCS_DEBUG_3[2]	1
PCS_DEBUG_3[3]	1
PCS_DEBUG_3[4]	1
PCS_DEBUG_3[5]	1
PCS_DEBUG_3[6]	1
PCS_DEBUG_3[7]	1
PCS_DEBUG_3[8]	1
PCS_DEBUG_3[9]	1
PMA_DEBUG_0	1
PMA_DEBUG_1	1
PMA_DEBUG_2	1
PMA_DEBUG_3	1

Q3_GPSS_COMMON (Unused pin tie-off)

Input Pin	Tie-Off
PCS_DEBUG_0[0]	1
PCS_DEBUG_0[10]	1
PCS_DEBUG_0[11]	1
PCS_DEBUG_0[12]	1
PCS_DEBUG_0[13]	1
PCS_DEBUG_0[14]	1
PCS_DEBUG_0[15]	1
PCS_DEBUG_0[16]	1
PCS_DEBUG_0[17]	1
PCS_DEBUG_0[18]	1
PCS_DEBUG_0[19]	1
PCS_DEBUG_0[1]	1
PCS_DEBUG_0[2]	1
PCS_DEBUG_0[3]	1
PCS_DEBUG_0[4]	1
PCS_DEBUG_0[5]	1
PCS_DEBUG_0[6]	1
PCS_DEBUG_0[7]	1
PCS_DEBUG_0[8]	1
PCS_DEBUG_0[9]	1
PCS_DEBUG_1[0]	1
PCS_DEBUG_1[10]	1
PCS_DEBUG_1[11]	1
PCS_DEBUG_1[12]	1
PCS_DEBUG_1[13]	1
PCS_DEBUG_1[14]	1
PCS_DEBUG_1[15]	1
PCS_DEBUG_1[16]	1
PCS_DEBUG_1[17]	1
PCS_DEBUG_1[18]	1
PCS_DEBUG_1[19]	1
PCS_DEBUG_1[1]	1
PCS_DEBUG_1[2]	1
PCS_DEBUG_1[3]	1
PCS_DEBUG_1[4]	1
PCS_DEBUG_1[5]	1
PCS_DEBUG_1[6]	1
PCS_DEBUG_1[7]	1
PCS_DEBUG_1[8]	1
PCS_DEBUG_1[9]	1
PCS_DEBUG_2[0]	1
PCS_DEBUG_2[10]	1
PCS_DEBUG_2[11]	1
PCS_DEBUG_2[12]	1
PCS_DEBUG_2[13]	1
PCS_DEBUG_2[14]	1
PCS_DEBUG_2[15]	1
PCS_DEBUG_2[16]	1
PCS_DEBUG_2[17]	1
PCS_DEBUG_2[18]	1
PCS_DEBUG_2[19]	1
PCS_DEBUG_2[1]	1
PCS_DEBUG_2[2]	1
PCS_DEBUG_2[3]	1
PCS_DEBUG_2[4]	1
PCS_DEBUG_2[5]	1
PCS_DEBUG_2[6]	1
PCS_DEBUG_2[7]	1
PCS_DEBUG_2[8]	1
PCS_DEBUG_2[9]	1
PCS_DEBUG_3[0]	1
PCS_DEBUG_3[10]	1
PCS_DEBUG_3[11]	1
PCS_DEBUG_3[12]	1
PCS_DEBUG_3[13]	1
PCS_DEBUG_3[14]	1
PCS_DEBUG_3[15]	1
PCS_DEBUG_3[16]	1
PCS_DEBUG_3[17]	1
PCS_DEBUG_3[18]	1
PCS_DEBUG_3[19]	1
PCS_DEBUG_3[1]	1
PCS_DEBUG_3[2]	1
PCS_DEBUG_3[3]	1
PCS_DEBUG_3[4]	1
PCS_DEBUG_3[5]	1
PCS_DEBUG_3[6]	1
PCS_DEBUG_3[7]	1
PCS_DEBUG_3[8]	1
PCS_DEBUG_3[9]	1
PMA_DEBUG_0	1
PMA_DEBUG_1	1
PMA_DEBUG_2	1
PMA_DEBUG_3	1

Q0_PCIE_COMMON (Unused pin tie-off)

Input Pin	Tie-Off
AXI_CLK	1
AXI_CLK_STABLE	0
PCIE_DEBUG_0[0]	1
PCIE_DEBUG_0[10]	1
PCIE_DEBUG_0[11]	1
PCIE_DEBUG_0[12]	1
PCIE_DEBUG_0[13]	1
PCIE_DEBUG_0[14]	1
PCIE_DEBUG_0[15]	1
PCIE_DEBUG_0[16]	1
PCIE_DEBUG_0[17]	1
PCIE_DEBUG_0[18]	1
PCIE_DEBUG_0[19]	1
PCIE_DEBUG_0[1]	1
PCIE_DEBUG_0[20]	1
PCIE_DEBUG_0[21]	1
PCIE_DEBUG_0[22]	1
PCIE_DEBUG_0[23]	1
PCIE_DEBUG_0[24]	1
PCIE_DEBUG_0[25]	1
PCIE_DEBUG_0[26]	1
PCIE_DEBUG_0[27]	1
PCIE_DEBUG_0[28]	1
PCIE_DEBUG_0[29]	1
PCIE_DEBUG_0[2]	1
PCIE_DEBUG_0[30]	1
PCIE_DEBUG_0[31]	1
PCIE_DEBUG_0[3]	1
PCIE_DEBUG_0[4]	1
PCIE_DEBUG_0[5]	1
PCIE_DEBUG_0[6]	1
PCIE_DEBUG_0[7]	1
PCIE_DEBUG_0[8]	1
PCIE_DEBUG_0[9]	1
PCIE_DEBUG_1[0]	1
PCIE_DEBUG_1[10]	1
PCIE_DEBUG_1[11]	1
PCIE_DEBUG_1[12]	1
PCIE_DEBUG_1[13]	1
PCIE_DEBUG_1[14]	1
PCIE_DEBUG_1[15]	1
PCIE_DEBUG_1[16]	1
PCIE_DEBUG_1[17]	1
PCIE_DEBUG_1[18]	1
PCIE_DEBUG_1[19]	1
PCIE_DEBUG_1[1]	1
PCIE_DEBUG_1[20]	1
PCIE_DEBUG_1[21]	1
PCIE_DEBUG_1[22]	1
PCIE_DEBUG_1[23]	1
PCIE_DEBUG_1[24]	1
PCIE_DEBUG_1[25]	1
PCIE_DEBUG_1[26]	1
PCIE_DEBUG_1[27]	1
PCIE_DEBUG_1[28]	1
PCIE_DEBUG_1[29]	1
PCIE_DEBUG_1[2]	1
PCIE_DEBUG_1[30]	1
PCIE_DEBUG_1[31]	1
PCIE_DEBUG_1[3]	1
PCIE_DEBUG_1[4]	1
PCIE_DEBUG_1[5]	1
PCIE_DEBUG_1[6]	1
PCIE_DEBUG_1[7]	1
PCIE_DEBUG_1[8]	1
PCIE_DEBUG_1[9]	1
PCS_DEBUG_0[0]	1
PCS_DEBUG_0[10]	1
PCS_DEBUG_0[11]	1
PCS_DEBUG_0[12]	1
PCS_DEBUG_0[13]	1
PCS_DEBUG_0[14]	1
PCS_DEBUG_0[15]	1
PCS_DEBUG_0[16]	1
PCS_DEBUG_0[17]	1
PCS_DEBUG_0[18]	1
PCS_DEBUG_0[19]	1
PCS_DEBUG_0[1]	1
PCS_DEBUG_0[2]	1
PCS_DEBUG_0[3]	1
PCS_DEBUG_0[4]	1
PCS_DEBUG_0[5]	1
PCS_DEBUG_0[6]	1
PCS_DEBUG_0[7]	1
PCS_DEBUG_0[8]	1
PCS_DEBUG_0[9]	1
PCS_DEBUG_1[0]	1
PCS_DEBUG_1[10]	1
PCS_DEBUG_1[11]	1
PCS_DEBUG_1[12]	1
PCS_DEBUG_1[13]	1
PCS_DEBUG_1[14]	1
PCS_DEBUG_1[15]	1
PCS_DEBUG_1[16]	1
PCS_DEBUG_1[17]	1
PCS_DEBUG_1[18]	1
PCS_DEBUG_1[19]	1
PCS_DEBUG_1[1]	1
PCS_DEBUG_1[2]	1
PCS_DEBUG_1[3]	1
PCS_DEBUG_1[4]	1
PCS_DEBUG_1[5]	1
PCS_DEBUG_1[6]	1
PCS_DEBUG_1[7]	1
PCS_DEBUG_1[8]	1
PCS_DEBUG_1[9]	1
PCS_DEBUG_2[0]	1
PCS_DEBUG_2[10]	1
PCS_DEBUG_2[11]	1
PCS_DEBUG_2[12]	1
PCS_DEBUG_2[13]	1
PCS_DEBUG_2[14]	1
PCS_DEBUG_2[15]	1
PCS_DEBUG_2[16]	1
PCS_DEBUG_2[17]	1
PCS_DEBUG_2[18]	1
PCS_DEBUG_2[19]	1
PCS_DEBUG_2[1]	1
PCS_DEBUG_2[2]	1
PCS_DEBUG_2[3]	1
PCS_DEBUG_2[4]	1
PCS_DEBUG_2[5]	1
PCS_DEBUG_2[6]	1
PCS_DEBUG_2[7]	1
PCS_DEBUG_2[8]	1
PCS_DEBUG_2[9]	1
PCS_DEBUG_3[0]	1
PCS_DEBUG_3[10]	1
PCS_DEBUG_3[11]	1
PCS_DEBUG_3[12]	1
PCS_DEBUG_3[13]	1
PCS_DEBUG_3[14]	1
PCS_DEBUG_3[15]	1
PCS_DEBUG_3[16]	1
PCS_DEBUG_3[17]	1
PCS_DEBUG_3[18]	1
PCS_DEBUG_3[19]	1
PCS_DEBUG_3[1]	1
PCS_DEBUG_3[2]	1
PCS_DEBUG_3[3]	1
PCS_DEBUG_3[4]	1
PCS_DEBUG_3[5]	1
PCS_DEBUG_3[6]	1
PCS_DEBUG_3[7]	1
PCS_DEBUG_3[8]	1
PCS_DEBUG_3[9]	1
PMA_DEBUG_0	1
PMA_DEBUG_1	1
PMA_DEBUG_2	1
PMA_DEBUG_3	1

PCIE_PCIESS_0 (Unused pin tie-off)

Input Pin	Tie-Off
AXI_CLK	1
AXI_CLK_STABLE	1
DRI_ARST_N	1
DRI_BRIDGE_ARST_N	1
DRI_BRIDGE_CLK	1
DRI_BRIDGE_CTRL[0]	1
DRI_BRIDGE_CTRL[10]	1
DRI_BRIDGE_CTRL[1]	1
DRI_BRIDGE_CTRL[2]	1
DRI_BRIDGE_CTRL[3]	1
DRI_BRIDGE_CTRL[4]	1
DRI_BRIDGE_CTRL[5]	1
DRI_BRIDGE_CTRL[6]	1
DRI_BRIDGE_CTRL[7]	1
DRI_BRIDGE_CTRL[8]	1
DRI_BRIDGE_CTRL[9]	1
DRI_BRIDGE_WDATA[0]	1
DRI_BRIDGE_WDATA[10]	1
DRI_BRIDGE_WDATA[11]	1
DRI_BRIDGE_WDATA[12]	1
DRI_BRIDGE_WDATA[13]	1
DRI_BRIDGE_WDATA[14]	1
DRI_BRIDGE_WDATA[15]	1
DRI_BRIDGE_WDATA[16]	1
DRI_BRIDGE_WDATA[17]	1
DRI_BRIDGE_WDATA[18]	1
DRI_BRIDGE_WDATA[19]	1
DRI_BRIDGE_WDATA[1]	1
DRI_BRIDGE_WDATA[20]	1
DRI_BRIDGE_WDATA[21]	1
DRI_BRIDGE_WDATA[22]	1
DRI_BRIDGE_WDATA[23]	1
DRI_BRIDGE_WDATA[24]	1
DRI_BRIDGE_WDATA[25]	1
DRI_BRIDGE_WDATA[26]	1
DRI_BRIDGE_WDATA[27]	1
DRI_BRIDGE_WDATA[28]	1
DRI_BRIDGE_WDATA[29]	1
DRI_BRIDGE_WDATA[2]	1
DRI_BRIDGE_WDATA[30]	1
DRI_BRIDGE_WDATA[31]	1
DRI_BRIDGE_WDATA[32]	1
DRI_BRIDGE_WDATA[3]	1
DRI_BRIDGE_WDATA[4]	1
DRI_BRIDGE_WDATA[5]	1
DRI_BRIDGE_WDATA[6]	1
DRI_BRIDGE_WDATA[7]	1
DRI_BRIDGE_WDATA[8]	1
DRI_BRIDGE_WDATA[9]	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
INTERRUPT[0]	1
INTERRUPT[1]	1
INTERRUPT[2]	1
INTERRUPT[3]	1
INTERRUPT[4]	1
INTERRUPT[5]	1
INTERRUPT[6]	1
INTERRUPT[7]	1
LINK_BRIDGE_ADDR[0]	1
LINK_BRIDGE_ADDR[1]	1
LINK_BRIDGE_ADDR[2]	1
LINK_BRIDGE_ARST_N	1
LINK_BRIDGE_CLK	1
LINK_BRIDGE_EN	1
LINK_BRIDGE_WDATA[0]	1
LINK_BRIDGE_WDATA[1]	1
LINK_BRIDGE_WDATA[2]	1
LINK_BRIDGE_WDATA[3]	1
LINK_CTRL_ADDR[0]	1
LINK_CTRL_ADDR[1]	1
LINK_CTRL_ADDR[2]	1
LINK_CTRL_ARST_N	1
LINK_CTRL_CLK	1
LINK_CTRL_EN	1
LINK_CTRL_WDATA[0]	1
LINK_CTRL_WDATA[1]	1
LINK_CTRL_WDATA[2]	1
LINK_CTRL_WDATA[3]	1
MPERST_N	0
M_ARREADY	1
M_AWREADY	1
M_BID[0]	1
M_BID[1]	1
M_BID[2]	1
M_BID[3]	1
M_BRESP[0]	1
M_BRESP[1]	1
M_BVALID	1
M_RDATA[0]	1
M_RDATA[10]	1
M_RDATA[11]	1
M_RDATA[12]	1
M_RDATA[13]	1
M_RDATA[14]	1
M_RDATA[15]	1
M_RDATA[16]	1
M_RDATA[17]	1
M_RDATA[18]	1
M_RDATA[19]	1
M_RDATA[1]	1
M_RDATA[20]	1
M_RDATA[21]	1
M_RDATA[22]	1
M_RDATA[23]	1
M_RDATA[24]	1
M_RDATA[25]	1
M_RDATA[26]	1
M_RDATA[27]	1
M_RDATA[28]	1
M_RDATA[29]	1
M_RDATA[2]	1
M_RDATA[30]	1
M_RDATA[31]	1
M_RDATA[32]	1
M_RDATA[33]	1
M_RDATA[34]	1
M_RDATA[35]	1
M_RDATA[36]	1
M_RDATA[37]	1
M_RDATA[38]	1
M_RDATA[39]	1
M_RDATA[3]	1
M_RDATA[40]	1
M_RDATA[41]	1
M_RDATA[42]	1
M_RDATA[43]	1
M_RDATA[44]	1
M_RDATA[45]	1
M_RDATA[46]	1
M_RDATA[47]	1
M_RDATA[48]	1
M_RDATA[49]	1
M_RDATA[4]	1
M_RDATA[50]	1
M_RDATA[51]	1
M_RDATA[52]	1
M_RDATA[53]	1
M_RDATA[54]	1
M_RDATA[55]	1
M_RDATA[56]	1
M_RDATA[57]	1
M_RDATA[58]	1
M_RDATA[59]	1
M_RDATA[5]	1
M_RDATA[60]	1
M_RDATA[61]	1
M_RDATA[62]	1
M_RDATA[63]	1
M_RDATA[6]	1
M_RDATA[7]	1
M_RDATA[8]	1
M_RDATA[9]	1
M_RDERR	1
M_RID[0]	1
M_RID[1]	1
M_RID[2]	1
M_RID[3]	1
M_RLAST	1
M_RRESP[0]	1
M_RRESP[1]	1
M_RVALID	1
M_WREADY	1
PCLK_OUT_0	1
PCLK_OUT_1	1
PCLK_OUT_2	1
PCLK_OUT_3	1
PHYSTATUS_0	1
PHYSTATUS_1	1
PHYSTATUS_2	1
PHYSTATUS_3	1
RXDATAK_0[0]	1
RXDATAK_0[1]	1
RXDATAK_0[2]	1
RXDATAK_0[3]	1
RXDATAK_1[0]	1
RXDATAK_1[1]	1
RXDATAK_1[2]	1
RXDATAK_1[3]	1
RXDATAK_2[0]	1
RXDATAK_2[1]	1
RXDATAK_2[2]	1
RXDATAK_2[3]	1
RXDATAK_3[0]	1
RXDATAK_3[1]	1
RXDATAK_3[2]	1
RXDATAK_3[3]	1
RXDATA_0[0]	1
RXDATA_0[10]	1
RXDATA_0[11]	1
RXDATA_0[12]	1
RXDATA_0[13]	1
RXDATA_0[14]	1
RXDATA_0[15]	1
RXDATA_0[16]	1
RXDATA_0[17]	1
RXDATA_0[18]	1
RXDATA_0[19]	1
RXDATA_0[1]	1
RXDATA_0[20]	1
RXDATA_0[21]	1
RXDATA_0[22]	1
RXDATA_0[23]	1
RXDATA_0[24]	1
RXDATA_0[25]	1
RXDATA_0[26]	1
RXDATA_0[27]	1
RXDATA_0[28]	1
RXDATA_0[29]	1
RXDATA_0[2]	1
RXDATA_0[30]	1
RXDATA_0[31]	1
RXDATA_0[3]	1
RXDATA_0[4]	1
RXDATA_0[5]	1
RXDATA_0[6]	1
RXDATA_0[7]	1
RXDATA_0[8]	1
RXDATA_0[9]	1
RXDATA_1[0]	1
RXDATA_1[10]	1
RXDATA_1[11]	1
RXDATA_1[12]	1
RXDATA_1[13]	1
RXDATA_1[14]	1
RXDATA_1[15]	1
RXDATA_1[16]	1
RXDATA_1[17]	1
RXDATA_1[18]	1
RXDATA_1[19]	1
RXDATA_1[1]	1
RXDATA_1[20]	1
RXDATA_1[21]	1
RXDATA_1[22]	1
RXDATA_1[23]	1
RXDATA_1[24]	1
RXDATA_1[25]	1
RXDATA_1[26]	1
RXDATA_1[27]	1
RXDATA_1[28]	1
RXDATA_1[29]	1
RXDATA_1[2]	1
RXDATA_1[30]	1
RXDATA_1[31]	1
RXDATA_1[3]	1
RXDATA_1[4]	1
RXDATA_1[5]	1
RXDATA_1[6]	1
RXDATA_1[7]	1
RXDATA_1[8]	1
RXDATA_1[9]	1
RXDATA_2[0]	1
RXDATA_2[10]	1
RXDATA_2[11]	1
RXDATA_2[12]	1
RXDATA_2[13]	1
RXDATA_2[14]	1
RXDATA_2[15]	1
RXDATA_2[16]	1
RXDATA_2[17]	1
RXDATA_2[18]	1
RXDATA_2[19]	1
RXDATA_2[1]	1
RXDATA_2[20]	1
RXDATA_2[21]	1
RXDATA_2[22]	1
RXDATA_2[23]	1
RXDATA_2[24]	1
RXDATA_2[25]	1
RXDATA_2[26]	1
RXDATA_2[27]	1
RXDATA_2[28]	1
RXDATA_2[29]	1
RXDATA_2[2]	1
RXDATA_2[30]	1
RXDATA_2[31]	1
RXDATA_2[3]	1
RXDATA_2[4]	1
RXDATA_2[5]	1
RXDATA_2[6]	1
RXDATA_2[7]	1
RXDATA_2[8]	1
RXDATA_2[9]	1
RXDATA_3[0]	1
RXDATA_3[10]	1
RXDATA_3[11]	1
RXDATA_3[12]	1
RXDATA_3[13]	1
RXDATA_3[14]	1
RXDATA_3[15]	1
RXDATA_3[16]	1
RXDATA_3[17]	1
RXDATA_3[18]	1
RXDATA_3[19]	1
RXDATA_3[1]	1
RXDATA_3[20]	1
RXDATA_3[21]	1
RXDATA_3[22]	1
RXDATA_3[23]	1
RXDATA_3[24]	1
RXDATA_3[25]	1
RXDATA_3[26]	1
RXDATA_3[27]	1
RXDATA_3[28]	1
RXDATA_3[29]	1
RXDATA_3[2]	1
RXDATA_3[30]	1
RXDATA_3[31]	1
RXDATA_3[3]	1
RXDATA_3[4]	1
RXDATA_3[5]	1
RXDATA_3[6]	1
RXDATA_3[7]	1
RXDATA_3[8]	1
RXDATA_3[9]	1
RXELECIDLE_0	1
RXELECIDLE_1	1
RXELECIDLE_2	1
RXELECIDLE_3	1
RXSTATUS_0[0]	1
RXSTATUS_0[1]	1
RXSTATUS_0[2]	1
RXSTATUS_1[0]	1
RXSTATUS_1[1]	1
RXSTATUS_1[2]	1
RXSTATUS_2[0]	1
RXSTATUS_2[1]	1
RXSTATUS_2[2]	1
RXSTATUS_3[0]	1
RXSTATUS_3[1]	1
RXSTATUS_3[2]	1
RXVALID_0	1
RXVALID_1	1
RXVALID_2	1
RXVALID_3	1
S_ARADDR_0	1
S_ARADDR_1	1
S_ARADDR_10	1
S_ARADDR_11	1
S_ARADDR_12	1
S_ARADDR_13	1
S_ARADDR_14	1
S_ARADDR_15	1
S_ARADDR_16	1
S_ARADDR_17	1
S_ARADDR_18	1
S_ARADDR_19	1
S_ARADDR_2	1
S_ARADDR_20	1
S_ARADDR_21	1
S_ARADDR_22	1
S_ARADDR_23	1
S_ARADDR_24	1
S_ARADDR_25	1
S_ARADDR_26	1
S_ARADDR_27	1
S_ARADDR_28	1
S_ARADDR_29	1
S_ARADDR_3	1
S_ARADDR_30	1
S_ARADDR_31	1
S_ARADDR_4	1
S_ARADDR_5	1
S_ARADDR_6	1
S_ARADDR_7	1
S_ARADDR_8	1
S_ARADDR_9	1
S_ARBURST[0]	1
S_ARBURST[1]	1
S_ARID[0]	1
S_ARID[1]	1
S_ARID[2]	1
S_ARID[3]	1
S_ARLEN[0]	1
S_ARLEN[1]	1
S_ARLEN[2]	1
S_ARLEN[3]	1
S_ARLEN[4]	1
S_ARLEN[5]	1
S_ARLEN[6]	1
S_ARLEN[7]	1
S_ARSIZE[0]	1
S_ARSIZE[1]	1
S_ARVALID	1
S_AWADDR_0	1
S_AWADDR_1	1
S_AWADDR_10	1
S_AWADDR_11	1
S_AWADDR_12	1
S_AWADDR_13	1
S_AWADDR_14	1
S_AWADDR_15	1
S_AWADDR_16	1
S_AWADDR_17	1
S_AWADDR_18	1
S_AWADDR_19	1
S_AWADDR_2	1
S_AWADDR_20	1
S_AWADDR_21	1
S_AWADDR_22	1
S_AWADDR_23	1
S_AWADDR_24	1
S_AWADDR_25	1
S_AWADDR_26	1
S_AWADDR_27	1
S_AWADDR_28	1
S_AWADDR_29	1
S_AWADDR_3	1
S_AWADDR_30	1
S_AWADDR_31	1
S_AWADDR_4	1
S_AWADDR_5	1
S_AWADDR_6	1
S_AWADDR_7	1
S_AWADDR_8	1
S_AWADDR_9	1
S_AWBURST[0]	1
S_AWBURST[1]	1
S_AWID[0]	1
S_AWID[1]	1
S_AWID[2]	1
S_AWID[3]	1
S_AWLEN[0]	1
S_AWLEN[1]	1
S_AWLEN[2]	1
S_AWLEN[3]	1
S_AWLEN[4]	1
S_AWLEN[5]	1
S_AWLEN[6]	1
S_AWLEN[7]	1
S_AWSIZE[0]	1
S_AWSIZE[1]	1
S_AWVALID	1
S_BREADY	1
S_RREADY	1
S_WDATA[0]	1
S_WDATA[10]	1
S_WDATA[11]	1
S_WDATA[12]	1
S_WDATA[13]	1
S_WDATA[14]	1
S_WDATA[15]	1
S_WDATA[16]	1
S_WDATA[17]	1
S_WDATA[18]	1
S_WDATA[19]	1
S_WDATA[1]	1
S_WDATA[20]	1
S_WDATA[21]	1
S_WDATA[22]	1
S_WDATA[23]	1
S_WDATA[24]	1
S_WDATA[25]	1
S_WDATA[26]	1
S_WDATA[27]	1
S_WDATA[28]	1
S_WDATA[29]	1
S_WDATA[2]	1
S_WDATA[30]	1
S_WDATA[31]	1
S_WDATA[32]	1
S_WDATA[33]	1
S_WDATA[34]	1
S_WDATA[35]	1
S_WDATA[36]	1
S_WDATA[37]	1
S_WDATA[38]	1
S_WDATA[39]	1
S_WDATA[3]	1
S_WDATA[40]	1
S_WDATA[41]	1
S_WDATA[42]	1
S_WDATA[43]	1
S_WDATA[44]	1
S_WDATA[45]	1
S_WDATA[46]	1
S_WDATA[47]	1
S_WDATA[48]	1
S_WDATA[49]	1
S_WDATA[4]	1
S_WDATA[50]	1
S_WDATA[51]	1
S_WDATA[52]	1
S_WDATA[53]	1
S_WDATA[54]	1
S_WDATA[55]	1
S_WDATA[56]	1
S_WDATA[57]	1
S_WDATA[58]	1
S_WDATA[59]	1
S_WDATA[5]	1
S_WDATA[60]	1
S_WDATA[61]	1
S_WDATA[62]	1
S_WDATA[63]	1
S_WDATA[6]	1
S_WDATA[7]	1
S_WDATA[8]	1
S_WDATA[9]	1
S_WDERR	1
S_WLAST	1
S_WSTRB[0]	1
S_WSTRB[1]	1
S_WSTRB[2]	1
S_WSTRB[3]	1
S_WSTRB[4]	1
S_WSTRB[5]	1
S_WSTRB[6]	1
S_WSTRB[7]	1
S_WVALID	1
TL_CLK	0
WAKEREQ	1
XCVR_ARST_N[0]	1
XCVR_ARST_N[1]	1

PCIE_PCIESS_1 (Unused pin tie-off)

Input Pin	Tie-Off
AXI_CLK	1
AXI_CLK_STABLE	1
DRI_ARST_N	1
DRI_BRIDGE_ARST_N	1
DRI_BRIDGE_CLK	1
DRI_BRIDGE_CTRL[0]	1
DRI_BRIDGE_CTRL[10]	1
DRI_BRIDGE_CTRL[1]	1
DRI_BRIDGE_CTRL[2]	1
DRI_BRIDGE_CTRL[3]	1
DRI_BRIDGE_CTRL[4]	1
DRI_BRIDGE_CTRL[5]	1
DRI_BRIDGE_CTRL[6]	1
DRI_BRIDGE_CTRL[7]	1
DRI_BRIDGE_CTRL[8]	1
DRI_BRIDGE_CTRL[9]	1
DRI_BRIDGE_WDATA[0]	1
DRI_BRIDGE_WDATA[10]	1
DRI_BRIDGE_WDATA[11]	1
DRI_BRIDGE_WDATA[12]	1
DRI_BRIDGE_WDATA[13]	1
DRI_BRIDGE_WDATA[14]	1
DRI_BRIDGE_WDATA[15]	1
DRI_BRIDGE_WDATA[16]	1
DRI_BRIDGE_WDATA[17]	1
DRI_BRIDGE_WDATA[18]	1
DRI_BRIDGE_WDATA[19]	1
DRI_BRIDGE_WDATA[1]	1
DRI_BRIDGE_WDATA[20]	1
DRI_BRIDGE_WDATA[21]	1
DRI_BRIDGE_WDATA[22]	1
DRI_BRIDGE_WDATA[23]	1
DRI_BRIDGE_WDATA[24]	1
DRI_BRIDGE_WDATA[25]	1
DRI_BRIDGE_WDATA[26]	1
DRI_BRIDGE_WDATA[27]	1
DRI_BRIDGE_WDATA[28]	1
DRI_BRIDGE_WDATA[29]	1
DRI_BRIDGE_WDATA[2]	1
DRI_BRIDGE_WDATA[30]	1
DRI_BRIDGE_WDATA[31]	1
DRI_BRIDGE_WDATA[32]	1
DRI_BRIDGE_WDATA[3]	1
DRI_BRIDGE_WDATA[4]	1
DRI_BRIDGE_WDATA[5]	1
DRI_BRIDGE_WDATA[6]	1
DRI_BRIDGE_WDATA[7]	1
DRI_BRIDGE_WDATA[8]	1
DRI_BRIDGE_WDATA[9]	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
INTERRUPT[0]	1
INTERRUPT[1]	1
INTERRUPT[2]	1
INTERRUPT[3]	1
INTERRUPT[4]	1
INTERRUPT[5]	1
INTERRUPT[6]	1
INTERRUPT[7]	1
LINK_BRIDGE_ADDR[0]	1
LINK_BRIDGE_ADDR[1]	1
LINK_BRIDGE_ADDR[2]	1
LINK_BRIDGE_ARST_N	1
LINK_BRIDGE_CLK	1
LINK_BRIDGE_EN	1
LINK_BRIDGE_WDATA[0]	1
LINK_BRIDGE_WDATA[1]	1
LINK_BRIDGE_WDATA[2]	1
LINK_BRIDGE_WDATA[3]	1
LINK_CTRL_ADDR[0]	1
LINK_CTRL_ADDR[1]	1
LINK_CTRL_ADDR[2]	1
LINK_CTRL_ARST_N	1
LINK_CTRL_CLK	1
LINK_CTRL_EN	1
LINK_CTRL_WDATA[0]	1
LINK_CTRL_WDATA[1]	1
LINK_CTRL_WDATA[2]	1
LINK_CTRL_WDATA[3]	1
MPERST_N	0
M_ARREADY	1
M_AWREADY	1
M_BID[0]	1
M_BID[1]	1
M_BID[2]	1
M_BID[3]	1
M_BRESP[0]	1
M_BRESP[1]	1
M_BVALID	1
M_RDATA[0]	1
M_RDATA[10]	1
M_RDATA[11]	1
M_RDATA[12]	1
M_RDATA[13]	1
M_RDATA[14]	1
M_RDATA[15]	1
M_RDATA[16]	1
M_RDATA[17]	1
M_RDATA[18]	1
M_RDATA[19]	1
M_RDATA[1]	1
M_RDATA[20]	1
M_RDATA[21]	1
M_RDATA[22]	1
M_RDATA[23]	1
M_RDATA[24]	1
M_RDATA[25]	1
M_RDATA[26]	1
M_RDATA[27]	1
M_RDATA[28]	1
M_RDATA[29]	1
M_RDATA[2]	1
M_RDATA[30]	1
M_RDATA[31]	1
M_RDATA[32]	1
M_RDATA[33]	1
M_RDATA[34]	1
M_RDATA[35]	1
M_RDATA[36]	1
M_RDATA[37]	1
M_RDATA[38]	1
M_RDATA[39]	1
M_RDATA[3]	1
M_RDATA[40]	1
M_RDATA[41]	1
M_RDATA[42]	1
M_RDATA[43]	1
M_RDATA[44]	1
M_RDATA[45]	1
M_RDATA[46]	1
M_RDATA[47]	1
M_RDATA[48]	1
M_RDATA[49]	1
M_RDATA[4]	1
M_RDATA[50]	1
M_RDATA[51]	1
M_RDATA[52]	1
M_RDATA[53]	1
M_RDATA[54]	1
M_RDATA[55]	1
M_RDATA[56]	1
M_RDATA[57]	1
M_RDATA[58]	1
M_RDATA[59]	1
M_RDATA[5]	1
M_RDATA[60]	1
M_RDATA[61]	1
M_RDATA[62]	1
M_RDATA[63]	1
M_RDATA[6]	1
M_RDATA[7]	1
M_RDATA[8]	1
M_RDATA[9]	1
M_RDERR	1
M_RID[0]	1
M_RID[1]	1
M_RID[2]	1
M_RID[3]	1
M_RLAST	1
M_RRESP[0]	1
M_RRESP[1]	1
M_RVALID	1
M_WREADY	1
PCLK_OUT_0	1
PCLK_OUT_1	1
PCLK_OUT_2	1
PCLK_OUT_3	1
PHYSTATUS_0	1
PHYSTATUS_1	1
PHYSTATUS_2	1
PHYSTATUS_3	1
RXDATAK_0[0]	1
RXDATAK_0[1]	1
RXDATAK_0[2]	1
RXDATAK_0[3]	1
RXDATAK_1[0]	1
RXDATAK_1[1]	1
RXDATAK_1[2]	1
RXDATAK_1[3]	1
RXDATAK_2[0]	1
RXDATAK_2[1]	1
RXDATAK_2[2]	1
RXDATAK_2[3]	1
RXDATAK_3[0]	1
RXDATAK_3[1]	1
RXDATAK_3[2]	1
RXDATAK_3[3]	1
RXDATA_0[0]	1
RXDATA_0[10]	1
RXDATA_0[11]	1
RXDATA_0[12]	1
RXDATA_0[13]	1
RXDATA_0[14]	1
RXDATA_0[15]	1
RXDATA_0[16]	1
RXDATA_0[17]	1
RXDATA_0[18]	1
RXDATA_0[19]	1
RXDATA_0[1]	1
RXDATA_0[20]	1
RXDATA_0[21]	1
RXDATA_0[22]	1
RXDATA_0[23]	1
RXDATA_0[24]	1
RXDATA_0[25]	1
RXDATA_0[26]	1
RXDATA_0[27]	1
RXDATA_0[28]	1
RXDATA_0[29]	1
RXDATA_0[2]	1
RXDATA_0[30]	1
RXDATA_0[31]	1
RXDATA_0[3]	1
RXDATA_0[4]	1
RXDATA_0[5]	1
RXDATA_0[6]	1
RXDATA_0[7]	1
RXDATA_0[8]	1
RXDATA_0[9]	1
RXDATA_1[0]	1
RXDATA_1[10]	1
RXDATA_1[11]	1
RXDATA_1[12]	1
RXDATA_1[13]	1
RXDATA_1[14]	1
RXDATA_1[15]	1
RXDATA_1[16]	1
RXDATA_1[17]	1
RXDATA_1[18]	1
RXDATA_1[19]	1
RXDATA_1[1]	1
RXDATA_1[20]	1
RXDATA_1[21]	1
RXDATA_1[22]	1
RXDATA_1[23]	1
RXDATA_1[24]	1
RXDATA_1[25]	1
RXDATA_1[26]	1
RXDATA_1[27]	1
RXDATA_1[28]	1
RXDATA_1[29]	1
RXDATA_1[2]	1
RXDATA_1[30]	1
RXDATA_1[31]	1
RXDATA_1[3]	1
RXDATA_1[4]	1
RXDATA_1[5]	1
RXDATA_1[6]	1
RXDATA_1[7]	1
RXDATA_1[8]	1
RXDATA_1[9]	1
RXDATA_2[0]	1
RXDATA_2[10]	1
RXDATA_2[11]	1
RXDATA_2[12]	1
RXDATA_2[13]	1
RXDATA_2[14]	1
RXDATA_2[15]	1
RXDATA_2[16]	1
RXDATA_2[17]	1
RXDATA_2[18]	1
RXDATA_2[19]	1
RXDATA_2[1]	1
RXDATA_2[20]	1
RXDATA_2[21]	1
RXDATA_2[22]	1
RXDATA_2[23]	1
RXDATA_2[24]	1
RXDATA_2[25]	1
RXDATA_2[26]	1
RXDATA_2[27]	1
RXDATA_2[28]	1
RXDATA_2[29]	1
RXDATA_2[2]	1
RXDATA_2[30]	1
RXDATA_2[31]	1
RXDATA_2[3]	1
RXDATA_2[4]	1
RXDATA_2[5]	1
RXDATA_2[6]	1
RXDATA_2[7]	1
RXDATA_2[8]	1
RXDATA_2[9]	1
RXDATA_3[0]	1
RXDATA_3[10]	1
RXDATA_3[11]	1
RXDATA_3[12]	1
RXDATA_3[13]	1
RXDATA_3[14]	1
RXDATA_3[15]	1
RXDATA_3[16]	1
RXDATA_3[17]	1
RXDATA_3[18]	1
RXDATA_3[19]	1
RXDATA_3[1]	1
RXDATA_3[20]	1
RXDATA_3[21]	1
RXDATA_3[22]	1
RXDATA_3[23]	1
RXDATA_3[24]	1
RXDATA_3[25]	1
RXDATA_3[26]	1
RXDATA_3[27]	1
RXDATA_3[28]	1
RXDATA_3[29]	1
RXDATA_3[2]	1
RXDATA_3[30]	1
RXDATA_3[31]	1
RXDATA_3[3]	1
RXDATA_3[4]	1
RXDATA_3[5]	1
RXDATA_3[6]	1
RXDATA_3[7]	1
RXDATA_3[8]	1
RXDATA_3[9]	1
RXELECIDLE_0	1
RXELECIDLE_1	1
RXELECIDLE_2	1
RXELECIDLE_3	1
RXSTATUS_0[0]	1
RXSTATUS_0[1]	1
RXSTATUS_0[2]	1
RXSTATUS_1[0]	1
RXSTATUS_1[1]	1
RXSTATUS_1[2]	1
RXSTATUS_2[0]	1
RXSTATUS_2[1]	1
RXSTATUS_2[2]	1
RXSTATUS_3[0]	1
RXSTATUS_3[1]	1
RXSTATUS_3[2]	1
RXVALID_0	1
RXVALID_1	1
RXVALID_2	1
RXVALID_3	1
S_ARADDR_0	1
S_ARADDR_1	1
S_ARADDR_10	1
S_ARADDR_11	1
S_ARADDR_12	1
S_ARADDR_13	1
S_ARADDR_14	1
S_ARADDR_15	1
S_ARADDR_16	1
S_ARADDR_17	1
S_ARADDR_18	1
S_ARADDR_19	1
S_ARADDR_2	1
S_ARADDR_20	1
S_ARADDR_21	1
S_ARADDR_22	1
S_ARADDR_23	1
S_ARADDR_24	1
S_ARADDR_25	1
S_ARADDR_26	1
S_ARADDR_27	1
S_ARADDR_28	1
S_ARADDR_29	1
S_ARADDR_3	1
S_ARADDR_30	1
S_ARADDR_31	1
S_ARADDR_4	1
S_ARADDR_5	1
S_ARADDR_6	1
S_ARADDR_7	1
S_ARADDR_8	1
S_ARADDR_9	1
S_ARBURST[0]	1
S_ARBURST[1]	1
S_ARID[0]	1
S_ARID[1]	1
S_ARID[2]	1
S_ARID[3]	1
S_ARLEN[0]	1
S_ARLEN[1]	1
S_ARLEN[2]	1
S_ARLEN[3]	1
S_ARLEN[4]	1
S_ARLEN[5]	1
S_ARLEN[6]	1
S_ARLEN[7]	1
S_ARSIZE[0]	1
S_ARSIZE[1]	1
S_ARVALID	1
S_AWADDR_0	1
S_AWADDR_1	1
S_AWADDR_10	1
S_AWADDR_11	1
S_AWADDR_12	1
S_AWADDR_13	1
S_AWADDR_14	1
S_AWADDR_15	1
S_AWADDR_16	1
S_AWADDR_17	1
S_AWADDR_18	1
S_AWADDR_19	1
S_AWADDR_2	1
S_AWADDR_20	1
S_AWADDR_21	1
S_AWADDR_22	1
S_AWADDR_23	1
S_AWADDR_24	1
S_AWADDR_25	1
S_AWADDR_26	1
S_AWADDR_27	1
S_AWADDR_28	1
S_AWADDR_29	1
S_AWADDR_3	1
S_AWADDR_30	1
S_AWADDR_31	1
S_AWADDR_4	1
S_AWADDR_5	1
S_AWADDR_6	1
S_AWADDR_7	1
S_AWADDR_8	1
S_AWADDR_9	1
S_AWBURST[0]	1
S_AWBURST[1]	1
S_AWID[0]	1
S_AWID[1]	1
S_AWID[2]	1
S_AWID[3]	1
S_AWLEN[0]	1
S_AWLEN[1]	1
S_AWLEN[2]	1
S_AWLEN[3]	1
S_AWLEN[4]	1
S_AWLEN[5]	1
S_AWLEN[6]	1
S_AWLEN[7]	1
S_AWSIZE[0]	1
S_AWSIZE[1]	1
S_AWVALID	1
S_BREADY	1
S_RREADY	1
S_WDATA[0]	1
S_WDATA[10]	1
S_WDATA[11]	1
S_WDATA[12]	1
S_WDATA[13]	1
S_WDATA[14]	1
S_WDATA[15]	1
S_WDATA[16]	1
S_WDATA[17]	1
S_WDATA[18]	1
S_WDATA[19]	1
S_WDATA[1]	1
S_WDATA[20]	1
S_WDATA[21]	1
S_WDATA[22]	1
S_WDATA[23]	1
S_WDATA[24]	1
S_WDATA[25]	1
S_WDATA[26]	1
S_WDATA[27]	1
S_WDATA[28]	1
S_WDATA[29]	1
S_WDATA[2]	1
S_WDATA[30]	1
S_WDATA[31]	1
S_WDATA[32]	1
S_WDATA[33]	1
S_WDATA[34]	1
S_WDATA[35]	1
S_WDATA[36]	1
S_WDATA[37]	1
S_WDATA[38]	1
S_WDATA[39]	1
S_WDATA[3]	1
S_WDATA[40]	1
S_WDATA[41]	1
S_WDATA[42]	1
S_WDATA[43]	1
S_WDATA[44]	1
S_WDATA[45]	1
S_WDATA[46]	1
S_WDATA[47]	1
S_WDATA[48]	1
S_WDATA[49]	1
S_WDATA[4]	1
S_WDATA[50]	1
S_WDATA[51]	1
S_WDATA[52]	1
S_WDATA[53]	1
S_WDATA[54]	1
S_WDATA[55]	1
S_WDATA[56]	1
S_WDATA[57]	1
S_WDATA[58]	1
S_WDATA[59]	1
S_WDATA[5]	1
S_WDATA[60]	1
S_WDATA[61]	1
S_WDATA[62]	1
S_WDATA[63]	1
S_WDATA[6]	1
S_WDATA[7]	1
S_WDATA[8]	1
S_WDATA[9]	1
S_WDERR	1
S_WLAST	1
S_WSTRB[0]	1
S_WSTRB[1]	1
S_WSTRB[2]	1
S_WSTRB[3]	1
S_WSTRB[4]	1
S_WSTRB[5]	1
S_WSTRB[6]	1
S_WSTRB[7]	1
S_WVALID	1
TL_CLK	0
WAKEREQ	1
XCVR_ARST_N[0]	1
XCVR_ARST_N[1]	1

Q0_TXPLL0 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q0_TXPLL1 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q1_TXPLL0 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q1_TXPLL1 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q2_TXPLL0 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q2_TXPLL1 (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

Q3_TXPLL (Unused pin tie-off)

Input Pin	Tie-Off
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FAB_REF_CLK	1
JA_REF_CLK	1
LINK_ADDR[0]	1
LINK_ADDR[1]	1
LINK_ADDR[2]	1
LINK_ARST_N	1
LINK_CLK	1
LINK_EN	1
LINK_WDATA[0]	1
LINK_WDATA[1]	1
LINK_WDATA[2]	1
LINK_WDATA[3]	1
REF_CLK_N	1
REF_CLK_P	1

DLL_NE_0 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_NE_1 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_NW_0 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_NW_1 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_SE_0 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_SE_1 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_SW_0 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

DLL_SW_1 (Unused pin tie-off)

Input Pin	Tie-Off
ALU_HOLD	1
CLK_MOVE	1
CODE_MOVE	1
CODE_UPDATE	1
DIR	1
DRI_ARST_N	1
DRI_CLK	1
DRI_CTRL[0]	1
DRI_CTRL[10]	1
DRI_CTRL[1]	1
DRI_CTRL[2]	1
DRI_CTRL[3]	1
DRI_CTRL[4]	1
DRI_CTRL[5]	1
DRI_CTRL[6]	1
DRI_CTRL[7]	1
DRI_CTRL[8]	1
DRI_CTRL[9]	1
DRI_WDATA[0]	1
DRI_WDATA[10]	1
DRI_WDATA[11]	1
DRI_WDATA[12]	1
DRI_WDATA[13]	1
DRI_WDATA[14]	1
DRI_WDATA[15]	1
DRI_WDATA[16]	1
DRI_WDATA[17]	1
DRI_WDATA[18]	1
DRI_WDATA[19]	1
DRI_WDATA[1]	1
DRI_WDATA[20]	1
DRI_WDATA[21]	1
DRI_WDATA[22]	1
DRI_WDATA[23]	1
DRI_WDATA[24]	1
DRI_WDATA[25]	1
DRI_WDATA[26]	1
DRI_WDATA[27]	1
DRI_WDATA[28]	1
DRI_WDATA[29]	1
DRI_WDATA[2]	1
DRI_WDATA[30]	1
DRI_WDATA[31]	1
DRI_WDATA[32]	1
DRI_WDATA[3]	1
DRI_WDATA[4]	1
DRI_WDATA[5]	1
DRI_WDATA[6]	1
DRI_WDATA[7]	1
DRI_WDATA[8]	1
DRI_WDATA[9]	1
FB_CLK	1
PHASE_LOAD	1
POWERDOWN_N	0
REF_CLK	1

CRNCOMMON_NE (Unused pin tie-off)

Input Pin	Tie-Off
REFCLK_SYNC_EN	1

CRNCOMMON_NW (Unused pin tie-off)

Input Pin	Tie-Off
REFCLK_SYNC_EN	1

CRNCOMMON_SE (Unused pin tie-off)

Input Pin	Tie-Off
REFCLK_SYNC_EN	1

CRNCOMMON_SW (Unused pin tie-off)

Input Pin	Tie-Off
REFCLK_SYNC_EN	1

VREFCTRL_NE_H (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

VREFCTRL_NW_ICBN0 (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

VREFCTRL_NW_V (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

VREFCTRL_SE_ICBW (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

VREFCTRL_SW_H (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

VREFCTRL_W_ICBW (Unused pin tie-off)

Input Pin	Tie-Off
LOAD	1
MOVE	1
VREF_DIRECTION	1

BANKCTRLMPC_NW (Unused pin tie-off)

Input Pin	Tie-Off
A	1

BANKCTRLMPC_SE (Unused pin tie-off)

Input Pin	Tie-Off
A	1

BANKCTRLGPIO_NW_V (Unused pin tie-off)

Input Pin	Tie-Off
CALIB_DIRECTION	1
CALIB_LOAD	1
CALIB_LOCK	1
CALIB_MOVE_DIFFR_PVT	1
CALIB_MOVE_NCODE	1
CALIB_MOVE_PCODE	1
CALIB_START	1

BANKCTRLGPIO_SE_ICBW (Unused pin tie-off)

Input Pin	Tie-Off
CALIB_DIRECTION	1
CALIB_LOAD	1
CALIB_LOCK	1
CALIB_MOVE_DIFFR_PVT	1
CALIB_MOVE_NCODE	1
CALIB_MOVE_PCODE	1
CALIB_START	1

BANKCTRLGPIO_SW_H (Unused pin tie-off)

Input Pin	Tie-Off
CALIB_DIRECTION	1
CALIB_LOAD	1
CALIB_LOCK	1
CALIB_MOVE_DIFFR_PVT	1
CALIB_MOVE_NCODE	1
CALIB_MOVE_PCODE	1
CALIB_START	1

BANKCTRLGPIO_W_ICBW (Unused pin tie-off)

Input Pin	Tie-Off
CALIB_DIRECTION	1
CALIB_LOAD	1
CALIB_LOCK	1
CALIB_MOVE_DIFFR_PVT	1
CALIB_MOVE_NCODE	1
CALIB_MOVE_PCODE	1
CALIB_START	1

CLKSTOPEN_E_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_E_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_NE_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_NE_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_NW_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_NW_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_SE_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_SE_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_SW_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_SW_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_W_0 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

CLKSTOPEN_W_1 (Unused pin tie-off)

Input Pin	Tie-Off
EN	1

NGMUX_E_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_E_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_NE_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_NE_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_NW_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_NW_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_SE_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_SE_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_SW_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_SW_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_W_0 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

NGMUX_W_1 (Unused pin tie-off)

Input Pin	Tie-Off
CLK0	1
CLK1	1
SEL	0

ICBINT_E_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_E_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_NE_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_NE_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_NW_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_NW_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_SE_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_SE_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_SW_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_SW_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_W_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBINT_W_1 (Unused pin tie-off)

Input Pin	Tie-Off
A	0

ICBMUXINGPC_E_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

ICBMUXINGPC_NE_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

ICBMUXINGPC_NW_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

ICBMUXINGPC_SE_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

ICBMUXINGPC_SW_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

ICBMUXINGPC_W_0 (Unused pin tie-off)

Input Pin	Tie-Off
A	1

APBS_G5C (Unused pin tie-off)

Input Pin	Tie-Off
CRYPTO_DRI_INTERRUPT	1
CRYPTO_DRI_RDATA[0]	1
CRYPTO_DRI_RDATA[10]	1
CRYPTO_DRI_RDATA[11]	1
CRYPTO_DRI_RDATA[12]	1
CRYPTO_DRI_RDATA[13]	1
CRYPTO_DRI_RDATA[14]	1
CRYPTO_DRI_RDATA[15]	1
CRYPTO_DRI_RDATA[16]	1
CRYPTO_DRI_RDATA[17]	1
CRYPTO_DRI_RDATA[18]	1
CRYPTO_DRI_RDATA[19]	1
CRYPTO_DRI_RDATA[1]	1
CRYPTO_DRI_RDATA[20]	1
CRYPTO_DRI_RDATA[21]	1
CRYPTO_DRI_RDATA[22]	1
CRYPTO_DRI_RDATA[23]	1
CRYPTO_DRI_RDATA[24]	1
CRYPTO_DRI_RDATA[25]	1
CRYPTO_DRI_RDATA[26]	1
CRYPTO_DRI_RDATA[27]	1
CRYPTO_DRI_RDATA[28]	1
CRYPTO_DRI_RDATA[29]	1
CRYPTO_DRI_RDATA[2]	1
CRYPTO_DRI_RDATA[30]	1
CRYPTO_DRI_RDATA[31]	1
CRYPTO_DRI_RDATA[32]	1
CRYPTO_DRI_RDATA[3]	1
CRYPTO_DRI_RDATA[4]	1
CRYPTO_DRI_RDATA[5]	1
CRYPTO_DRI_RDATA[6]	1
CRYPTO_DRI_RDATA[7]	1
CRYPTO_DRI_RDATA[8]	1
CRYPTO_DRI_RDATA[9]	1
DLL0_NE_DRI_INTERRUPT	1
DLL0_NE_DRI_RDATA[0]	1
DLL0_NE_DRI_RDATA[10]	1
DLL0_NE_DRI_RDATA[11]	1
DLL0_NE_DRI_RDATA[12]	1
DLL0_NE_DRI_RDATA[13]	1
DLL0_NE_DRI_RDATA[14]	1
DLL0_NE_DRI_RDATA[15]	1
DLL0_NE_DRI_RDATA[16]	1
DLL0_NE_DRI_RDATA[17]	1
DLL0_NE_DRI_RDATA[18]	1
DLL0_NE_DRI_RDATA[19]	1
DLL0_NE_DRI_RDATA[1]	1
DLL0_NE_DRI_RDATA[20]	1
DLL0_NE_DRI_RDATA[21]	1
DLL0_NE_DRI_RDATA[22]	1
DLL0_NE_DRI_RDATA[23]	1
DLL0_NE_DRI_RDATA[24]	1
DLL0_NE_DRI_RDATA[25]	1
DLL0_NE_DRI_RDATA[26]	1
DLL0_NE_DRI_RDATA[27]	1
DLL0_NE_DRI_RDATA[28]	1
DLL0_NE_DRI_RDATA[29]	1
DLL0_NE_DRI_RDATA[2]	1
DLL0_NE_DRI_RDATA[30]	1
DLL0_NE_DRI_RDATA[31]	1
DLL0_NE_DRI_RDATA[32]	1
DLL0_NE_DRI_RDATA[3]	1
DLL0_NE_DRI_RDATA[4]	1
DLL0_NE_DRI_RDATA[5]	1
DLL0_NE_DRI_RDATA[6]	1
DLL0_NE_DRI_RDATA[7]	1
DLL0_NE_DRI_RDATA[8]	1
DLL0_NE_DRI_RDATA[9]	1
DLL0_NW_DRI_INTERRUPT	1
DLL0_NW_DRI_RDATA[0]	1
DLL0_NW_DRI_RDATA[10]	1
DLL0_NW_DRI_RDATA[11]	1
DLL0_NW_DRI_RDATA[12]	1
DLL0_NW_DRI_RDATA[13]	1
DLL0_NW_DRI_RDATA[14]	1
DLL0_NW_DRI_RDATA[15]	1
DLL0_NW_DRI_RDATA[16]	1
DLL0_NW_DRI_RDATA[17]	1
DLL0_NW_DRI_RDATA[18]	1
DLL0_NW_DRI_RDATA[19]	1
DLL0_NW_DRI_RDATA[1]	1
DLL0_NW_DRI_RDATA[20]	1
DLL0_NW_DRI_RDATA[21]	1
DLL0_NW_DRI_RDATA[22]	1
DLL0_NW_DRI_RDATA[23]	1
DLL0_NW_DRI_RDATA[24]	1
DLL0_NW_DRI_RDATA[25]	1
DLL0_NW_DRI_RDATA[26]	1
DLL0_NW_DRI_RDATA[27]	1
DLL0_NW_DRI_RDATA[28]	1
DLL0_NW_DRI_RDATA[29]	1
DLL0_NW_DRI_RDATA[2]	1
DLL0_NW_DRI_RDATA[30]	1
DLL0_NW_DRI_RDATA[31]	1
DLL0_NW_DRI_RDATA[32]	1
DLL0_NW_DRI_RDATA[3]	1
DLL0_NW_DRI_RDATA[4]	1
DLL0_NW_DRI_RDATA[5]	1
DLL0_NW_DRI_RDATA[6]	1
DLL0_NW_DRI_RDATA[7]	1
DLL0_NW_DRI_RDATA[8]	1
DLL0_NW_DRI_RDATA[9]	1
DLL0_SE_DRI_INTERRUPT	1
DLL0_SE_DRI_RDATA[0]	1
DLL0_SE_DRI_RDATA[10]	1
DLL0_SE_DRI_RDATA[11]	1
DLL0_SE_DRI_RDATA[12]	1
DLL0_SE_DRI_RDATA[13]	1
DLL0_SE_DRI_RDATA[14]	1
DLL0_SE_DRI_RDATA[15]	1
DLL0_SE_DRI_RDATA[16]	1
DLL0_SE_DRI_RDATA[17]	1
DLL0_SE_DRI_RDATA[18]	1
DLL0_SE_DRI_RDATA[19]	1
DLL0_SE_DRI_RDATA[1]	1
DLL0_SE_DRI_RDATA[20]	1
DLL0_SE_DRI_RDATA[21]	1
DLL0_SE_DRI_RDATA[22]	1
DLL0_SE_DRI_RDATA[23]	1
DLL0_SE_DRI_RDATA[24]	1
DLL0_SE_DRI_RDATA[25]	1
DLL0_SE_DRI_RDATA[26]	1
DLL0_SE_DRI_RDATA[27]	1
DLL0_SE_DRI_RDATA[28]	1
DLL0_SE_DRI_RDATA[29]	1
DLL0_SE_DRI_RDATA[2]	1
DLL0_SE_DRI_RDATA[30]	1
DLL0_SE_DRI_RDATA[31]	1
DLL0_SE_DRI_RDATA[32]	1
DLL0_SE_DRI_RDATA[3]	1
DLL0_SE_DRI_RDATA[4]	1
DLL0_SE_DRI_RDATA[5]	1
DLL0_SE_DRI_RDATA[6]	1
DLL0_SE_DRI_RDATA[7]	1
DLL0_SE_DRI_RDATA[8]	1
DLL0_SE_DRI_RDATA[9]	1
DLL0_SW_DRI_INTERRUPT	1
DLL0_SW_DRI_RDATA[0]	1
DLL0_SW_DRI_RDATA[10]	1
DLL0_SW_DRI_RDATA[11]	1
DLL0_SW_DRI_RDATA[12]	1
DLL0_SW_DRI_RDATA[13]	1
DLL0_SW_DRI_RDATA[14]	1
DLL0_SW_DRI_RDATA[15]	1
DLL0_SW_DRI_RDATA[16]	1
DLL0_SW_DRI_RDATA[17]	1
DLL0_SW_DRI_RDATA[18]	1
DLL0_SW_DRI_RDATA[19]	1
DLL0_SW_DRI_RDATA[1]	1
DLL0_SW_DRI_RDATA[20]	1
DLL0_SW_DRI_RDATA[21]	1
DLL0_SW_DRI_RDATA[22]	1
DLL0_SW_DRI_RDATA[23]	1
DLL0_SW_DRI_RDATA[24]	1
DLL0_SW_DRI_RDATA[25]	1
DLL0_SW_DRI_RDATA[26]	1
DLL0_SW_DRI_RDATA[27]	1
DLL0_SW_DRI_RDATA[28]	1
DLL0_SW_DRI_RDATA[29]	1
DLL0_SW_DRI_RDATA[2]	1
DLL0_SW_DRI_RDATA[30]	1
DLL0_SW_DRI_RDATA[31]	1
DLL0_SW_DRI_RDATA[32]	1
DLL0_SW_DRI_RDATA[3]	1
DLL0_SW_DRI_RDATA[4]	1
DLL0_SW_DRI_RDATA[5]	1
DLL0_SW_DRI_RDATA[6]	1
DLL0_SW_DRI_RDATA[7]	1
DLL0_SW_DRI_RDATA[8]	1
DLL0_SW_DRI_RDATA[9]	1
DLL1_NE_DRI_INTERRUPT	1
DLL1_NE_DRI_RDATA[0]	1
DLL1_NE_DRI_RDATA[10]	1
DLL1_NE_DRI_RDATA[11]	1
DLL1_NE_DRI_RDATA[12]	1
DLL1_NE_DRI_RDATA[13]	1
DLL1_NE_DRI_RDATA[14]	1
DLL1_NE_DRI_RDATA[15]	1
DLL1_NE_DRI_RDATA[16]	1
DLL1_NE_DRI_RDATA[17]	1
DLL1_NE_DRI_RDATA[18]	1
DLL1_NE_DRI_RDATA[19]	1
DLL1_NE_DRI_RDATA[1]	1
DLL1_NE_DRI_RDATA[20]	1
DLL1_NE_DRI_RDATA[21]	1
DLL1_NE_DRI_RDATA[22]	1
DLL1_NE_DRI_RDATA[23]	1
DLL1_NE_DRI_RDATA[24]	1
DLL1_NE_DRI_RDATA[25]	1
DLL1_NE_DRI_RDATA[26]	1
DLL1_NE_DRI_RDATA[27]	1
DLL1_NE_DRI_RDATA[28]	1
DLL1_NE_DRI_RDATA[29]	1
DLL1_NE_DRI_RDATA[2]	1
DLL1_NE_DRI_RDATA[30]	1
DLL1_NE_DRI_RDATA[31]	1
DLL1_NE_DRI_RDATA[32]	1
DLL1_NE_DRI_RDATA[3]	1
DLL1_NE_DRI_RDATA[4]	1
DLL1_NE_DRI_RDATA[5]	1
DLL1_NE_DRI_RDATA[6]	1
DLL1_NE_DRI_RDATA[7]	1
DLL1_NE_DRI_RDATA[8]	1
DLL1_NE_DRI_RDATA[9]	1
DLL1_NW_DRI_INTERRUPT	1
DLL1_NW_DRI_RDATA[0]	1
DLL1_NW_DRI_RDATA[10]	1
DLL1_NW_DRI_RDATA[11]	1
DLL1_NW_DRI_RDATA[12]	1
DLL1_NW_DRI_RDATA[13]	1
DLL1_NW_DRI_RDATA[14]	1
DLL1_NW_DRI_RDATA[15]	1
DLL1_NW_DRI_RDATA[16]	1
DLL1_NW_DRI_RDATA[17]	1
DLL1_NW_DRI_RDATA[18]	1
DLL1_NW_DRI_RDATA[19]	1
DLL1_NW_DRI_RDATA[1]	1
DLL1_NW_DRI_RDATA[20]	1
DLL1_NW_DRI_RDATA[21]	1
DLL1_NW_DRI_RDATA[22]	1
DLL1_NW_DRI_RDATA[23]	1
DLL1_NW_DRI_RDATA[24]	1
DLL1_NW_DRI_RDATA[25]	1
DLL1_NW_DRI_RDATA[26]	1
DLL1_NW_DRI_RDATA[27]	1
DLL1_NW_DRI_RDATA[28]	1
DLL1_NW_DRI_RDATA[29]	1
DLL1_NW_DRI_RDATA[2]	1
DLL1_NW_DRI_RDATA[30]	1
DLL1_NW_DRI_RDATA[31]	1
DLL1_NW_DRI_RDATA[32]	1
DLL1_NW_DRI_RDATA[3]	1
DLL1_NW_DRI_RDATA[4]	1
DLL1_NW_DRI_RDATA[5]	1
DLL1_NW_DRI_RDATA[6]	1
DLL1_NW_DRI_RDATA[7]	1
DLL1_NW_DRI_RDATA[8]	1
DLL1_NW_DRI_RDATA[9]	1
DLL1_SE_DRI_INTERRUPT	1
DLL1_SE_DRI_RDATA[0]	1
DLL1_SE_DRI_RDATA[10]	1
DLL1_SE_DRI_RDATA[11]	1
DLL1_SE_DRI_RDATA[12]	1
DLL1_SE_DRI_RDATA[13]	1
DLL1_SE_DRI_RDATA[14]	1
DLL1_SE_DRI_RDATA[15]	1
DLL1_SE_DRI_RDATA[16]	1
DLL1_SE_DRI_RDATA[17]	1
DLL1_SE_DRI_RDATA[18]	1
DLL1_SE_DRI_RDATA[19]	1
DLL1_SE_DRI_RDATA[1]	1
DLL1_SE_DRI_RDATA[20]	1
DLL1_SE_DRI_RDATA[21]	1
DLL1_SE_DRI_RDATA[22]	1
DLL1_SE_DRI_RDATA[23]	1
DLL1_SE_DRI_RDATA[24]	1
DLL1_SE_DRI_RDATA[25]	1
DLL1_SE_DRI_RDATA[26]	1
DLL1_SE_DRI_RDATA[27]	1
DLL1_SE_DRI_RDATA[28]	1
DLL1_SE_DRI_RDATA[29]	1
DLL1_SE_DRI_RDATA[2]	1
DLL1_SE_DRI_RDATA[30]	1
DLL1_SE_DRI_RDATA[31]	1
DLL1_SE_DRI_RDATA[32]	1
DLL1_SE_DRI_RDATA[3]	1
DLL1_SE_DRI_RDATA[4]	1
DLL1_SE_DRI_RDATA[5]	1
DLL1_SE_DRI_RDATA[6]	1
DLL1_SE_DRI_RDATA[7]	1
DLL1_SE_DRI_RDATA[8]	1
DLL1_SE_DRI_RDATA[9]	1
DLL1_SW_DRI_INTERRUPT	1
DLL1_SW_DRI_RDATA[0]	1
DLL1_SW_DRI_RDATA[10]	1
DLL1_SW_DRI_RDATA[11]	1
DLL1_SW_DRI_RDATA[12]	1
DLL1_SW_DRI_RDATA[13]	1
DLL1_SW_DRI_RDATA[14]	1
DLL1_SW_DRI_RDATA[15]	1
DLL1_SW_DRI_RDATA[16]	1
DLL1_SW_DRI_RDATA[17]	1
DLL1_SW_DRI_RDATA[18]	1
DLL1_SW_DRI_RDATA[19]	1
DLL1_SW_DRI_RDATA[1]	1
DLL1_SW_DRI_RDATA[20]	1
DLL1_SW_DRI_RDATA[21]	1
DLL1_SW_DRI_RDATA[22]	1
DLL1_SW_DRI_RDATA[23]	1
DLL1_SW_DRI_RDATA[24]	1
DLL1_SW_DRI_RDATA[25]	1
DLL1_SW_DRI_RDATA[26]	1
DLL1_SW_DRI_RDATA[27]	1
DLL1_SW_DRI_RDATA[28]	1
DLL1_SW_DRI_RDATA[29]	1
DLL1_SW_DRI_RDATA[2]	1
DLL1_SW_DRI_RDATA[30]	1
DLL1_SW_DRI_RDATA[31]	1
DLL1_SW_DRI_RDATA[32]	1
DLL1_SW_DRI_RDATA[3]	1
DLL1_SW_DRI_RDATA[4]	1
DLL1_SW_DRI_RDATA[5]	1
DLL1_SW_DRI_RDATA[6]	1
DLL1_SW_DRI_RDATA[7]	1
DLL1_SW_DRI_RDATA[8]	1
DLL1_SW_DRI_RDATA[9]	1
PADDR[0]	1
PADDR[10]	1
PADDR[11]	1
PADDR[12]	1
PADDR[13]	1
PADDR[14]	1
PADDR[15]	1
PADDR[16]	1
PADDR[17]	1
PADDR[18]	1
PADDR[19]	1
PADDR[1]	1
PADDR[20]	1
PADDR[21]	1
PADDR[22]	1
PADDR[23]	1
PADDR[24]	1
PADDR[25]	1
PADDR[26]	1
PADDR[27]	1
PADDR[28]	1
PADDR[2]	1
PADDR[3]	1
PADDR[4]	1
PADDR[5]	1
PADDR[6]	1
PADDR[7]	1
PADDR[8]	1
PADDR[9]	1
PCIE0_DRI_INTERRUPT	1
PCIE0_DRI_RDATA[0]	1
PCIE0_DRI_RDATA[10]	1
PCIE0_DRI_RDATA[11]	1
PCIE0_DRI_RDATA[12]	1
PCIE0_DRI_RDATA[13]	1
PCIE0_DRI_RDATA[14]	1
PCIE0_DRI_RDATA[15]	1
PCIE0_DRI_RDATA[16]	1
PCIE0_DRI_RDATA[17]	1
PCIE0_DRI_RDATA[18]	1
PCIE0_DRI_RDATA[19]	1
PCIE0_DRI_RDATA[1]	1
PCIE0_DRI_RDATA[20]	1
PCIE0_DRI_RDATA[21]	1
PCIE0_DRI_RDATA[22]	1
PCIE0_DRI_RDATA[23]	1
PCIE0_DRI_RDATA[24]	1
PCIE0_DRI_RDATA[25]	1
PCIE0_DRI_RDATA[26]	1
PCIE0_DRI_RDATA[27]	1
PCIE0_DRI_RDATA[28]	1
PCIE0_DRI_RDATA[29]	1
PCIE0_DRI_RDATA[2]	1
PCIE0_DRI_RDATA[30]	1
PCIE0_DRI_RDATA[31]	1
PCIE0_DRI_RDATA[32]	1
PCIE0_DRI_RDATA[3]	1
PCIE0_DRI_RDATA[4]	1
PCIE0_DRI_RDATA[5]	1
PCIE0_DRI_RDATA[6]	1
PCIE0_DRI_RDATA[7]	1
PCIE0_DRI_RDATA[8]	1
PCIE0_DRI_RDATA[9]	1
PCIE1_DRI_INTERRUPT	1
PCIE1_DRI_RDATA[0]	1
PCIE1_DRI_RDATA[10]	1
PCIE1_DRI_RDATA[11]	1
PCIE1_DRI_RDATA[12]	1
PCIE1_DRI_RDATA[13]	1
PCIE1_DRI_RDATA[14]	1
PCIE1_DRI_RDATA[15]	1
PCIE1_DRI_RDATA[16]	1
PCIE1_DRI_RDATA[17]	1
PCIE1_DRI_RDATA[18]	1
PCIE1_DRI_RDATA[19]	1
PCIE1_DRI_RDATA[1]	1
PCIE1_DRI_RDATA[20]	1
PCIE1_DRI_RDATA[21]	1
PCIE1_DRI_RDATA[22]	1
PCIE1_DRI_RDATA[23]	1
PCIE1_DRI_RDATA[24]	1
PCIE1_DRI_RDATA[25]	1
PCIE1_DRI_RDATA[26]	1
PCIE1_DRI_RDATA[27]	1
PCIE1_DRI_RDATA[28]	1
PCIE1_DRI_RDATA[29]	1
PCIE1_DRI_RDATA[2]	1
PCIE1_DRI_RDATA[30]	1
PCIE1_DRI_RDATA[31]	1
PCIE1_DRI_RDATA[32]	1
PCIE1_DRI_RDATA[3]	1
PCIE1_DRI_RDATA[4]	1
PCIE1_DRI_RDATA[5]	1
PCIE1_DRI_RDATA[6]	1
PCIE1_DRI_RDATA[7]	1
PCIE1_DRI_RDATA[8]	1
PCIE1_DRI_RDATA[9]	1
PCLK	1
PENABLE	1
PLL0_NE_DRI_INTERRUPT	1
PLL0_NE_DRI_RDATA[0]	1
PLL0_NE_DRI_RDATA[10]	1
PLL0_NE_DRI_RDATA[11]	1
PLL0_NE_DRI_RDATA[12]	1
PLL0_NE_DRI_RDATA[13]	1
PLL0_NE_DRI_RDATA[14]	1
PLL0_NE_DRI_RDATA[15]	1
PLL0_NE_DRI_RDATA[16]	1
PLL0_NE_DRI_RDATA[17]	1
PLL0_NE_DRI_RDATA[18]	1
PLL0_NE_DRI_RDATA[19]	1
PLL0_NE_DRI_RDATA[1]	1
PLL0_NE_DRI_RDATA[20]	1
PLL0_NE_DRI_RDATA[21]	1
PLL0_NE_DRI_RDATA[22]	1
PLL0_NE_DRI_RDATA[23]	1
PLL0_NE_DRI_RDATA[24]	1
PLL0_NE_DRI_RDATA[25]	1
PLL0_NE_DRI_RDATA[26]	1
PLL0_NE_DRI_RDATA[27]	1
PLL0_NE_DRI_RDATA[28]	1
PLL0_NE_DRI_RDATA[29]	1
PLL0_NE_DRI_RDATA[2]	1
PLL0_NE_DRI_RDATA[30]	1
PLL0_NE_DRI_RDATA[31]	1
PLL0_NE_DRI_RDATA[32]	1
PLL0_NE_DRI_RDATA[3]	1
PLL0_NE_DRI_RDATA[4]	1
PLL0_NE_DRI_RDATA[5]	1
PLL0_NE_DRI_RDATA[6]	1
PLL0_NE_DRI_RDATA[7]	1
PLL0_NE_DRI_RDATA[8]	1
PLL0_NE_DRI_RDATA[9]	1
PLL0_NW_DRI_INTERRUPT	1
PLL0_NW_DRI_RDATA[0]	1
PLL0_NW_DRI_RDATA[10]	1
PLL0_NW_DRI_RDATA[11]	1
PLL0_NW_DRI_RDATA[12]	1
PLL0_NW_DRI_RDATA[13]	1
PLL0_NW_DRI_RDATA[14]	1
PLL0_NW_DRI_RDATA[15]	1
PLL0_NW_DRI_RDATA[16]	1
PLL0_NW_DRI_RDATA[17]	1
PLL0_NW_DRI_RDATA[18]	1
PLL0_NW_DRI_RDATA[19]	1
PLL0_NW_DRI_RDATA[1]	1
PLL0_NW_DRI_RDATA[20]	1
PLL0_NW_DRI_RDATA[21]	1
PLL0_NW_DRI_RDATA[22]	1
PLL0_NW_DRI_RDATA[23]	1
PLL0_NW_DRI_RDATA[24]	1
PLL0_NW_DRI_RDATA[25]	1
PLL0_NW_DRI_RDATA[26]	1
PLL0_NW_DRI_RDATA[27]	1
PLL0_NW_DRI_RDATA[28]	1
PLL0_NW_DRI_RDATA[29]	1
PLL0_NW_DRI_RDATA[2]	1
PLL0_NW_DRI_RDATA[30]	1
PLL0_NW_DRI_RDATA[31]	1
PLL0_NW_DRI_RDATA[32]	1
PLL0_NW_DRI_RDATA[3]	1
PLL0_NW_DRI_RDATA[4]	1
PLL0_NW_DRI_RDATA[5]	1
PLL0_NW_DRI_RDATA[6]	1
PLL0_NW_DRI_RDATA[7]	1
PLL0_NW_DRI_RDATA[8]	1
PLL0_NW_DRI_RDATA[9]	1
PLL0_SE_DRI_INTERRUPT	1
PLL0_SE_DRI_RDATA[0]	1
PLL0_SE_DRI_RDATA[10]	1
PLL0_SE_DRI_RDATA[11]	1
PLL0_SE_DRI_RDATA[12]	1
PLL0_SE_DRI_RDATA[13]	1
PLL0_SE_DRI_RDATA[14]	1
PLL0_SE_DRI_RDATA[15]	1
PLL0_SE_DRI_RDATA[16]	1
PLL0_SE_DRI_RDATA[17]	1
PLL0_SE_DRI_RDATA[18]	1
PLL0_SE_DRI_RDATA[19]	1
PLL0_SE_DRI_RDATA[1]	1
PLL0_SE_DRI_RDATA[20]	1
PLL0_SE_DRI_RDATA[21]	1
PLL0_SE_DRI_RDATA[22]	1
PLL0_SE_DRI_RDATA[23]	1
PLL0_SE_DRI_RDATA[24]	1
PLL0_SE_DRI_RDATA[25]	1
PLL0_SE_DRI_RDATA[26]	1
PLL0_SE_DRI_RDATA[27]	1
PLL0_SE_DRI_RDATA[28]	1
PLL0_SE_DRI_RDATA[29]	1
PLL0_SE_DRI_RDATA[2]	1
PLL0_SE_DRI_RDATA[30]	1
PLL0_SE_DRI_RDATA[31]	1
PLL0_SE_DRI_RDATA[32]	1
PLL0_SE_DRI_RDATA[3]	1
PLL0_SE_DRI_RDATA[4]	1
PLL0_SE_DRI_RDATA[5]	1
PLL0_SE_DRI_RDATA[6]	1
PLL0_SE_DRI_RDATA[7]	1
PLL0_SE_DRI_RDATA[8]	1
PLL0_SE_DRI_RDATA[9]	1
PLL0_SW_DRI_INTERRUPT	1
PLL0_SW_DRI_RDATA[0]	1
PLL0_SW_DRI_RDATA[10]	1
PLL0_SW_DRI_RDATA[11]	1
PLL0_SW_DRI_RDATA[12]	1
PLL0_SW_DRI_RDATA[13]	1
PLL0_SW_DRI_RDATA[14]	1
PLL0_SW_DRI_RDATA[15]	1
PLL0_SW_DRI_RDATA[16]	1
PLL0_SW_DRI_RDATA[17]	1
PLL0_SW_DRI_RDATA[18]	1
PLL0_SW_DRI_RDATA[19]	1
PLL0_SW_DRI_RDATA[1]	1
PLL0_SW_DRI_RDATA[20]	1
PLL0_SW_DRI_RDATA[21]	1
PLL0_SW_DRI_RDATA[22]	1
PLL0_SW_DRI_RDATA[23]	1
PLL0_SW_DRI_RDATA[24]	1
PLL0_SW_DRI_RDATA[25]	1
PLL0_SW_DRI_RDATA[26]	1
PLL0_SW_DRI_RDATA[27]	1
PLL0_SW_DRI_RDATA[28]	1
PLL0_SW_DRI_RDATA[29]	1
PLL0_SW_DRI_RDATA[2]	1
PLL0_SW_DRI_RDATA[30]	1
PLL0_SW_DRI_RDATA[31]	1
PLL0_SW_DRI_RDATA[32]	1
PLL0_SW_DRI_RDATA[3]	1
PLL0_SW_DRI_RDATA[4]	1
PLL0_SW_DRI_RDATA[5]	1
PLL0_SW_DRI_RDATA[6]	1
PLL0_SW_DRI_RDATA[7]	1
PLL0_SW_DRI_RDATA[8]	1
PLL0_SW_DRI_RDATA[9]	1
PLL1_NE_DRI_INTERRUPT	1
PLL1_NE_DRI_RDATA[0]	1
PLL1_NE_DRI_RDATA[10]	1
PLL1_NE_DRI_RDATA[11]	1
PLL1_NE_DRI_RDATA[12]	1
PLL1_NE_DRI_RDATA[13]	1
PLL1_NE_DRI_RDATA[14]	1
PLL1_NE_DRI_RDATA[15]	1
PLL1_NE_DRI_RDATA[16]	1
PLL1_NE_DRI_RDATA[17]	1
PLL1_NE_DRI_RDATA[18]	1
PLL1_NE_DRI_RDATA[19]	1
PLL1_NE_DRI_RDATA[1]	1
PLL1_NE_DRI_RDATA[20]	1
PLL1_NE_DRI_RDATA[21]	1
PLL1_NE_DRI_RDATA[22]	1
PLL1_NE_DRI_RDATA[23]	1
PLL1_NE_DRI_RDATA[24]	1
PLL1_NE_DRI_RDATA[25]	1
PLL1_NE_DRI_RDATA[26]	1
PLL1_NE_DRI_RDATA[27]	1
PLL1_NE_DRI_RDATA[28]	1
PLL1_NE_DRI_RDATA[29]	1
PLL1_NE_DRI_RDATA[2]	1
PLL1_NE_DRI_RDATA[30]	1
PLL1_NE_DRI_RDATA[31]	1
PLL1_NE_DRI_RDATA[32]	1
PLL1_NE_DRI_RDATA[3]	1
PLL1_NE_DRI_RDATA[4]	1
PLL1_NE_DRI_RDATA[5]	1
PLL1_NE_DRI_RDATA[6]	1
PLL1_NE_DRI_RDATA[7]	1
PLL1_NE_DRI_RDATA[8]	1
PLL1_NE_DRI_RDATA[9]	1
PLL1_NW_DRI_INTERRUPT	1
PLL1_NW_DRI_RDATA[0]	1
PLL1_NW_DRI_RDATA[10]	1
PLL1_NW_DRI_RDATA[11]	1
PLL1_NW_DRI_RDATA[12]	1
PLL1_NW_DRI_RDATA[13]	1
PLL1_NW_DRI_RDATA[14]	1
PLL1_NW_DRI_RDATA[15]	1
PLL1_NW_DRI_RDATA[16]	1
PLL1_NW_DRI_RDATA[17]	1
PLL1_NW_DRI_RDATA[18]	1
PLL1_NW_DRI_RDATA[19]	1
PLL1_NW_DRI_RDATA[1]	1
PLL1_NW_DRI_RDATA[20]	1
PLL1_NW_DRI_RDATA[21]	1
PLL1_NW_DRI_RDATA[22]	1
PLL1_NW_DRI_RDATA[23]	1
PLL1_NW_DRI_RDATA[24]	1
PLL1_NW_DRI_RDATA[25]	1
PLL1_NW_DRI_RDATA[26]	1
PLL1_NW_DRI_RDATA[27]	1
PLL1_NW_DRI_RDATA[28]	1
PLL1_NW_DRI_RDATA[29]	1
PLL1_NW_DRI_RDATA[2]	1
PLL1_NW_DRI_RDATA[30]	1
PLL1_NW_DRI_RDATA[31]	1
PLL1_NW_DRI_RDATA[32]	1
PLL1_NW_DRI_RDATA[3]	1
PLL1_NW_DRI_RDATA[4]	1
PLL1_NW_DRI_RDATA[5]	1
PLL1_NW_DRI_RDATA[6]	1
PLL1_NW_DRI_RDATA[7]	1
PLL1_NW_DRI_RDATA[8]	1
PLL1_NW_DRI_RDATA[9]	1
PLL1_SE_DRI_INTERRUPT	1
PLL1_SE_DRI_RDATA[0]	1
PLL1_SE_DRI_RDATA[10]	1
PLL1_SE_DRI_RDATA[11]	1
PLL1_SE_DRI_RDATA[12]	1
PLL1_SE_DRI_RDATA[13]	1
PLL1_SE_DRI_RDATA[14]	1
PLL1_SE_DRI_RDATA[15]	1
PLL1_SE_DRI_RDATA[16]	1
PLL1_SE_DRI_RDATA[17]	1
PLL1_SE_DRI_RDATA[18]	1
PLL1_SE_DRI_RDATA[19]	1
PLL1_SE_DRI_RDATA[1]	1
PLL1_SE_DRI_RDATA[20]	1
PLL1_SE_DRI_RDATA[21]	1
PLL1_SE_DRI_RDATA[22]	1
PLL1_SE_DRI_RDATA[23]	1
PLL1_SE_DRI_RDATA[24]	1
PLL1_SE_DRI_RDATA[25]	1
PLL1_SE_DRI_RDATA[26]	1
PLL1_SE_DRI_RDATA[27]	1
PLL1_SE_DRI_RDATA[28]	1
PLL1_SE_DRI_RDATA[29]	1
PLL1_SE_DRI_RDATA[2]	1
PLL1_SE_DRI_RDATA[30]	1
PLL1_SE_DRI_RDATA[31]	1
PLL1_SE_DRI_RDATA[32]	1
PLL1_SE_DRI_RDATA[3]	1
PLL1_SE_DRI_RDATA[4]	1
PLL1_SE_DRI_RDATA[5]	1
PLL1_SE_DRI_RDATA[6]	1
PLL1_SE_DRI_RDATA[7]	1
PLL1_SE_DRI_RDATA[8]	1
PLL1_SE_DRI_RDATA[9]	1
PLL1_SW_DRI_INTERRUPT	1
PLL1_SW_DRI_RDATA[0]	1
PLL1_SW_DRI_RDATA[10]	1
PLL1_SW_DRI_RDATA[11]	1
PLL1_SW_DRI_RDATA[12]	1
PLL1_SW_DRI_RDATA[13]	1
PLL1_SW_DRI_RDATA[14]	1
PLL1_SW_DRI_RDATA[15]	1
PLL1_SW_DRI_RDATA[16]	1
PLL1_SW_DRI_RDATA[17]	1
PLL1_SW_DRI_RDATA[18]	1
PLL1_SW_DRI_RDATA[19]	1
PLL1_SW_DRI_RDATA[1]	1
PLL1_SW_DRI_RDATA[20]	1
PLL1_SW_DRI_RDATA[21]	1
PLL1_SW_DRI_RDATA[22]	1
PLL1_SW_DRI_RDATA[23]	1
PLL1_SW_DRI_RDATA[24]	1
PLL1_SW_DRI_RDATA[25]	1
PLL1_SW_DRI_RDATA[26]	1
PLL1_SW_DRI_RDATA[27]	1
PLL1_SW_DRI_RDATA[28]	1
PLL1_SW_DRI_RDATA[29]	1
PLL1_SW_DRI_RDATA[2]	1
PLL1_SW_DRI_RDATA[30]	1
PLL1_SW_DRI_RDATA[31]	1
PLL1_SW_DRI_RDATA[32]	1
PLL1_SW_DRI_RDATA[3]	1
PLL1_SW_DRI_RDATA[4]	1
PLL1_SW_DRI_RDATA[5]	1
PLL1_SW_DRI_RDATA[6]	1
PLL1_SW_DRI_RDATA[7]	1
PLL1_SW_DRI_RDATA[8]	1
PLL1_SW_DRI_RDATA[9]	1
PRESETN	1
PSEL	0
PSTRB[0]	1
PSTRB[1]	1
PSTRB[2]	1
PSTRB[3]	1
PWDATA[0]	1
PWDATA[10]	1
PWDATA[11]	1
PWDATA[12]	1
PWDATA[13]	1
PWDATA[14]	1
PWDATA[15]	1
PWDATA[16]	1
PWDATA[17]	1
PWDATA[18]	1
PWDATA[19]	1
PWDATA[1]	1
PWDATA[20]	1
PWDATA[21]	1
PWDATA[22]	1
PWDATA[23]	1
PWDATA[24]	1
PWDATA[25]	1
PWDATA[26]	1
PWDATA[27]	1
PWDATA[28]	1
PWDATA[29]	1
PWDATA[2]	1
PWDATA[30]	1
PWDATA[31]	1
PWDATA[3]	1
PWDATA[4]	1
PWDATA[5]	1
PWDATA[6]	1
PWDATA[7]	1
PWDATA[8]	1
PWDATA[9]	1
PWRITE	1
Q0_LANE0_DRI_INTERRUPT	1
Q0_LANE0_DRI_RDATA[0]	1
Q0_LANE0_DRI_RDATA[10]	1
Q0_LANE0_DRI_RDATA[11]	1
Q0_LANE0_DRI_RDATA[12]	1
Q0_LANE0_DRI_RDATA[13]	1
Q0_LANE0_DRI_RDATA[14]	1
Q0_LANE0_DRI_RDATA[15]	1
Q0_LANE0_DRI_RDATA[16]	1
Q0_LANE0_DRI_RDATA[17]	1
Q0_LANE0_DRI_RDATA[18]	1
Q0_LANE0_DRI_RDATA[19]	1
Q0_LANE0_DRI_RDATA[1]	1
Q0_LANE0_DRI_RDATA[20]	1
Q0_LANE0_DRI_RDATA[21]	1
Q0_LANE0_DRI_RDATA[22]	1
Q0_LANE0_DRI_RDATA[23]	1
Q0_LANE0_DRI_RDATA[24]	1
Q0_LANE0_DRI_RDATA[25]	1
Q0_LANE0_DRI_RDATA[26]	1
Q0_LANE0_DRI_RDATA[27]	1
Q0_LANE0_DRI_RDATA[28]	1
Q0_LANE0_DRI_RDATA[29]	1
Q0_LANE0_DRI_RDATA[2]	1
Q0_LANE0_DRI_RDATA[30]	1
Q0_LANE0_DRI_RDATA[31]	1
Q0_LANE0_DRI_RDATA[32]	1
Q0_LANE0_DRI_RDATA[3]	1
Q0_LANE0_DRI_RDATA[4]	1
Q0_LANE0_DRI_RDATA[5]	1
Q0_LANE0_DRI_RDATA[6]	1
Q0_LANE0_DRI_RDATA[7]	1
Q0_LANE0_DRI_RDATA[8]	1
Q0_LANE0_DRI_RDATA[9]	1
Q0_LANE1_DRI_INTERRUPT	1
Q0_LANE1_DRI_RDATA[0]	1
Q0_LANE1_DRI_RDATA[10]	1
Q0_LANE1_DRI_RDATA[11]	1
Q0_LANE1_DRI_RDATA[12]	1
Q0_LANE1_DRI_RDATA[13]	1
Q0_LANE1_DRI_RDATA[14]	1
Q0_LANE1_DRI_RDATA[15]	1
Q0_LANE1_DRI_RDATA[16]	1
Q0_LANE1_DRI_RDATA[17]	1
Q0_LANE1_DRI_RDATA[18]	1
Q0_LANE1_DRI_RDATA[19]	1
Q0_LANE1_DRI_RDATA[1]	1
Q0_LANE1_DRI_RDATA[20]	1
Q0_LANE1_DRI_RDATA[21]	1
Q0_LANE1_DRI_RDATA[22]	1
Q0_LANE1_DRI_RDATA[23]	1
Q0_LANE1_DRI_RDATA[24]	1
Q0_LANE1_DRI_RDATA[25]	1
Q0_LANE1_DRI_RDATA[26]	1
Q0_LANE1_DRI_RDATA[27]	1
Q0_LANE1_DRI_RDATA[28]	1
Q0_LANE1_DRI_RDATA[29]	1
Q0_LANE1_DRI_RDATA[2]	1
Q0_LANE1_DRI_RDATA[30]	1
Q0_LANE1_DRI_RDATA[31]	1
Q0_LANE1_DRI_RDATA[32]	1
Q0_LANE1_DRI_RDATA[3]	1
Q0_LANE1_DRI_RDATA[4]	1
Q0_LANE1_DRI_RDATA[5]	1
Q0_LANE1_DRI_RDATA[6]	1
Q0_LANE1_DRI_RDATA[7]	1
Q0_LANE1_DRI_RDATA[8]	1
Q0_LANE1_DRI_RDATA[9]	1
Q0_LANE2_DRI_INTERRUPT	1
Q0_LANE2_DRI_RDATA[0]	1
Q0_LANE2_DRI_RDATA[10]	1
Q0_LANE2_DRI_RDATA[11]	1
Q0_LANE2_DRI_RDATA[12]	1
Q0_LANE2_DRI_RDATA[13]	1
Q0_LANE2_DRI_RDATA[14]	1
Q0_LANE2_DRI_RDATA[15]	1
Q0_LANE2_DRI_RDATA[16]	1
Q0_LANE2_DRI_RDATA[17]	1
Q0_LANE2_DRI_RDATA[18]	1
Q0_LANE2_DRI_RDATA[19]	1
Q0_LANE2_DRI_RDATA[1]	1
Q0_LANE2_DRI_RDATA[20]	1
Q0_LANE2_DRI_RDATA[21]	1
Q0_LANE2_DRI_RDATA[22]	1
Q0_LANE2_DRI_RDATA[23]	1
Q0_LANE2_DRI_RDATA[24]	1
Q0_LANE2_DRI_RDATA[25]	1
Q0_LANE2_DRI_RDATA[26]	1
Q0_LANE2_DRI_RDATA[27]	1
Q0_LANE2_DRI_RDATA[28]	1
Q0_LANE2_DRI_RDATA[29]	1
Q0_LANE2_DRI_RDATA[2]	1
Q0_LANE2_DRI_RDATA[30]	1
Q0_LANE2_DRI_RDATA[31]	1
Q0_LANE2_DRI_RDATA[32]	1
Q0_LANE2_DRI_RDATA[3]	1
Q0_LANE2_DRI_RDATA[4]	1
Q0_LANE2_DRI_RDATA[5]	1
Q0_LANE2_DRI_RDATA[6]	1
Q0_LANE2_DRI_RDATA[7]	1
Q0_LANE2_DRI_RDATA[8]	1
Q0_LANE2_DRI_RDATA[9]	1
Q0_LANE3_DRI_INTERRUPT	1
Q0_LANE3_DRI_RDATA[0]	1
Q0_LANE3_DRI_RDATA[10]	1
Q0_LANE3_DRI_RDATA[11]	1
Q0_LANE3_DRI_RDATA[12]	1
Q0_LANE3_DRI_RDATA[13]	1
Q0_LANE3_DRI_RDATA[14]	1
Q0_LANE3_DRI_RDATA[15]	1
Q0_LANE3_DRI_RDATA[16]	1
Q0_LANE3_DRI_RDATA[17]	1
Q0_LANE3_DRI_RDATA[18]	1
Q0_LANE3_DRI_RDATA[19]	1
Q0_LANE3_DRI_RDATA[1]	1
Q0_LANE3_DRI_RDATA[20]	1
Q0_LANE3_DRI_RDATA[21]	1
Q0_LANE3_DRI_RDATA[22]	1
Q0_LANE3_DRI_RDATA[23]	1
Q0_LANE3_DRI_RDATA[24]	1
Q0_LANE3_DRI_RDATA[25]	1
Q0_LANE3_DRI_RDATA[26]	1
Q0_LANE3_DRI_RDATA[27]	1
Q0_LANE3_DRI_RDATA[28]	1
Q0_LANE3_DRI_RDATA[29]	1
Q0_LANE3_DRI_RDATA[2]	1
Q0_LANE3_DRI_RDATA[30]	1
Q0_LANE3_DRI_RDATA[31]	1
Q0_LANE3_DRI_RDATA[32]	1
Q0_LANE3_DRI_RDATA[3]	1
Q0_LANE3_DRI_RDATA[4]	1
Q0_LANE3_DRI_RDATA[5]	1
Q0_LANE3_DRI_RDATA[6]	1
Q0_LANE3_DRI_RDATA[7]	1
Q0_LANE3_DRI_RDATA[8]	1
Q0_LANE3_DRI_RDATA[9]	1
Q0_TXPLL0_DRI_INTERRUPT	1
Q0_TXPLL0_DRI_RDATA[0]	1
Q0_TXPLL0_DRI_RDATA[10]	1
Q0_TXPLL0_DRI_RDATA[11]	1
Q0_TXPLL0_DRI_RDATA[12]	1
Q0_TXPLL0_DRI_RDATA[13]	1
Q0_TXPLL0_DRI_RDATA[14]	1
Q0_TXPLL0_DRI_RDATA[15]	1
Q0_TXPLL0_DRI_RDATA[16]	1
Q0_TXPLL0_DRI_RDATA[17]	1
Q0_TXPLL0_DRI_RDATA[18]	1
Q0_TXPLL0_DRI_RDATA[19]	1
Q0_TXPLL0_DRI_RDATA[1]	1
Q0_TXPLL0_DRI_RDATA[20]	1
Q0_TXPLL0_DRI_RDATA[21]	1
Q0_TXPLL0_DRI_RDATA[22]	1
Q0_TXPLL0_DRI_RDATA[23]	1
Q0_TXPLL0_DRI_RDATA[24]	1
Q0_TXPLL0_DRI_RDATA[25]	1
Q0_TXPLL0_DRI_RDATA[26]	1
Q0_TXPLL0_DRI_RDATA[27]	1
Q0_TXPLL0_DRI_RDATA[28]	1
Q0_TXPLL0_DRI_RDATA[29]	1
Q0_TXPLL0_DRI_RDATA[2]	1
Q0_TXPLL0_DRI_RDATA[30]	1
Q0_TXPLL0_DRI_RDATA[31]	1
Q0_TXPLL0_DRI_RDATA[32]	1
Q0_TXPLL0_DRI_RDATA[3]	1
Q0_TXPLL0_DRI_RDATA[4]	1
Q0_TXPLL0_DRI_RDATA[5]	1
Q0_TXPLL0_DRI_RDATA[6]	1
Q0_TXPLL0_DRI_RDATA[7]	1
Q0_TXPLL0_DRI_RDATA[8]	1
Q0_TXPLL0_DRI_RDATA[9]	1
Q0_TXPLL1_DRI_INTERRUPT	1
Q0_TXPLL1_DRI_RDATA[0]	1
Q0_TXPLL1_DRI_RDATA[10]	1
Q0_TXPLL1_DRI_RDATA[11]	1
Q0_TXPLL1_DRI_RDATA[12]	1
Q0_TXPLL1_DRI_RDATA[13]	1
Q0_TXPLL1_DRI_RDATA[14]	1
Q0_TXPLL1_DRI_RDATA[15]	1
Q0_TXPLL1_DRI_RDATA[16]	1
Q0_TXPLL1_DRI_RDATA[17]	1
Q0_TXPLL1_DRI_RDATA[18]	1
Q0_TXPLL1_DRI_RDATA[19]	1
Q0_TXPLL1_DRI_RDATA[1]	1
Q0_TXPLL1_DRI_RDATA[20]	1
Q0_TXPLL1_DRI_RDATA[21]	1
Q0_TXPLL1_DRI_RDATA[22]	1
Q0_TXPLL1_DRI_RDATA[23]	1
Q0_TXPLL1_DRI_RDATA[24]	1
Q0_TXPLL1_DRI_RDATA[25]	1
Q0_TXPLL1_DRI_RDATA[26]	1
Q0_TXPLL1_DRI_RDATA[27]	1
Q0_TXPLL1_DRI_RDATA[28]	1
Q0_TXPLL1_DRI_RDATA[29]	1
Q0_TXPLL1_DRI_RDATA[2]	1
Q0_TXPLL1_DRI_RDATA[30]	1
Q0_TXPLL1_DRI_RDATA[31]	1
Q0_TXPLL1_DRI_RDATA[32]	1
Q0_TXPLL1_DRI_RDATA[3]	1
Q0_TXPLL1_DRI_RDATA[4]	1
Q0_TXPLL1_DRI_RDATA[5]	1
Q0_TXPLL1_DRI_RDATA[6]	1
Q0_TXPLL1_DRI_RDATA[7]	1
Q0_TXPLL1_DRI_RDATA[8]	1
Q0_TXPLL1_DRI_RDATA[9]	1
Q0_TXPLL_SSC_DRI_INTERRUPT	1
Q0_TXPLL_SSC_DRI_RDATA[0]	1
Q0_TXPLL_SSC_DRI_RDATA[10]	1
Q0_TXPLL_SSC_DRI_RDATA[11]	1
Q0_TXPLL_SSC_DRI_RDATA[12]	1
Q0_TXPLL_SSC_DRI_RDATA[13]	1
Q0_TXPLL_SSC_DRI_RDATA[14]	1
Q0_TXPLL_SSC_DRI_RDATA[15]	1
Q0_TXPLL_SSC_DRI_RDATA[16]	1
Q0_TXPLL_SSC_DRI_RDATA[17]	1
Q0_TXPLL_SSC_DRI_RDATA[18]	1
Q0_TXPLL_SSC_DRI_RDATA[19]	1
Q0_TXPLL_SSC_DRI_RDATA[1]	1
Q0_TXPLL_SSC_DRI_RDATA[20]	1
Q0_TXPLL_SSC_DRI_RDATA[21]	1
Q0_TXPLL_SSC_DRI_RDATA[22]	1
Q0_TXPLL_SSC_DRI_RDATA[23]	1
Q0_TXPLL_SSC_DRI_RDATA[24]	1
Q0_TXPLL_SSC_DRI_RDATA[25]	1
Q0_TXPLL_SSC_DRI_RDATA[26]	1
Q0_TXPLL_SSC_DRI_RDATA[27]	1
Q0_TXPLL_SSC_DRI_RDATA[28]	1
Q0_TXPLL_SSC_DRI_RDATA[29]	1
Q0_TXPLL_SSC_DRI_RDATA[2]	1
Q0_TXPLL_SSC_DRI_RDATA[30]	1
Q0_TXPLL_SSC_DRI_RDATA[31]	1
Q0_TXPLL_SSC_DRI_RDATA[32]	1
Q0_TXPLL_SSC_DRI_RDATA[3]	1
Q0_TXPLL_SSC_DRI_RDATA[4]	1
Q0_TXPLL_SSC_DRI_RDATA[5]	1
Q0_TXPLL_SSC_DRI_RDATA[6]	1
Q0_TXPLL_SSC_DRI_RDATA[7]	1
Q0_TXPLL_SSC_DRI_RDATA[8]	1
Q0_TXPLL_SSC_DRI_RDATA[9]	1
Q1_LANE0_DRI_INTERRUPT	1
Q1_LANE0_DRI_RDATA[0]	1
Q1_LANE0_DRI_RDATA[10]	1
Q1_LANE0_DRI_RDATA[11]	1
Q1_LANE0_DRI_RDATA[12]	1
Q1_LANE0_DRI_RDATA[13]	1
Q1_LANE0_DRI_RDATA[14]	1
Q1_LANE0_DRI_RDATA[15]	1
Q1_LANE0_DRI_RDATA[16]	1
Q1_LANE0_DRI_RDATA[17]	1
Q1_LANE0_DRI_RDATA[18]	1
Q1_LANE0_DRI_RDATA[19]	1
Q1_LANE0_DRI_RDATA[1]	1
Q1_LANE0_DRI_RDATA[20]	1
Q1_LANE0_DRI_RDATA[21]	1
Q1_LANE0_DRI_RDATA[22]	1
Q1_LANE0_DRI_RDATA[23]	1
Q1_LANE0_DRI_RDATA[24]	1
Q1_LANE0_DRI_RDATA[25]	1
Q1_LANE0_DRI_RDATA[26]	1
Q1_LANE0_DRI_RDATA[27]	1
Q1_LANE0_DRI_RDATA[28]	1
Q1_LANE0_DRI_RDATA[29]	1
Q1_LANE0_DRI_RDATA[2]	1
Q1_LANE0_DRI_RDATA[30]	1
Q1_LANE0_DRI_RDATA[31]	1
Q1_LANE0_DRI_RDATA[32]	1
Q1_LANE0_DRI_RDATA[3]	1
Q1_LANE0_DRI_RDATA[4]	1
Q1_LANE0_DRI_RDATA[5]	1
Q1_LANE0_DRI_RDATA[6]	1
Q1_LANE0_DRI_RDATA[7]	1
Q1_LANE0_DRI_RDATA[8]	1
Q1_LANE0_DRI_RDATA[9]	1
Q1_LANE1_DRI_INTERRUPT	1
Q1_LANE1_DRI_RDATA[0]	1
Q1_LANE1_DRI_RDATA[10]	1
Q1_LANE1_DRI_RDATA[11]	1
Q1_LANE1_DRI_RDATA[12]	1
Q1_LANE1_DRI_RDATA[13]	1
Q1_LANE1_DRI_RDATA[14]	1
Q1_LANE1_DRI_RDATA[15]	1
Q1_LANE1_DRI_RDATA[16]	1
Q1_LANE1_DRI_RDATA[17]	1
Q1_LANE1_DRI_RDATA[18]	1
Q1_LANE1_DRI_RDATA[19]	1
Q1_LANE1_DRI_RDATA[1]	1
Q1_LANE1_DRI_RDATA[20]	1
Q1_LANE1_DRI_RDATA[21]	1
Q1_LANE1_DRI_RDATA[22]	1
Q1_LANE1_DRI_RDATA[23]	1
Q1_LANE1_DRI_RDATA[24]	1
Q1_LANE1_DRI_RDATA[25]	1
Q1_LANE1_DRI_RDATA[26]	1
Q1_LANE1_DRI_RDATA[27]	1
Q1_LANE1_DRI_RDATA[28]	1
Q1_LANE1_DRI_RDATA[29]	1
Q1_LANE1_DRI_RDATA[2]	1
Q1_LANE1_DRI_RDATA[30]	1
Q1_LANE1_DRI_RDATA[31]	1
Q1_LANE1_DRI_RDATA[32]	1
Q1_LANE1_DRI_RDATA[3]	1
Q1_LANE1_DRI_RDATA[4]	1
Q1_LANE1_DRI_RDATA[5]	1
Q1_LANE1_DRI_RDATA[6]	1
Q1_LANE1_DRI_RDATA[7]	1
Q1_LANE1_DRI_RDATA[8]	1
Q1_LANE1_DRI_RDATA[9]	1
Q1_LANE2_DRI_INTERRUPT	1
Q1_LANE2_DRI_RDATA[0]	1
Q1_LANE2_DRI_RDATA[10]	1
Q1_LANE2_DRI_RDATA[11]	1
Q1_LANE2_DRI_RDATA[12]	1
Q1_LANE2_DRI_RDATA[13]	1
Q1_LANE2_DRI_RDATA[14]	1
Q1_LANE2_DRI_RDATA[15]	1
Q1_LANE2_DRI_RDATA[16]	1
Q1_LANE2_DRI_RDATA[17]	1
Q1_LANE2_DRI_RDATA[18]	1
Q1_LANE2_DRI_RDATA[19]	1
Q1_LANE2_DRI_RDATA[1]	1
Q1_LANE2_DRI_RDATA[20]	1
Q1_LANE2_DRI_RDATA[21]	1
Q1_LANE2_DRI_RDATA[22]	1
Q1_LANE2_DRI_RDATA[23]	1
Q1_LANE2_DRI_RDATA[24]	1
Q1_LANE2_DRI_RDATA[25]	1
Q1_LANE2_DRI_RDATA[26]	1
Q1_LANE2_DRI_RDATA[27]	1
Q1_LANE2_DRI_RDATA[28]	1
Q1_LANE2_DRI_RDATA[29]	1
Q1_LANE2_DRI_RDATA[2]	1
Q1_LANE2_DRI_RDATA[30]	1
Q1_LANE2_DRI_RDATA[31]	1
Q1_LANE2_DRI_RDATA[32]	1
Q1_LANE2_DRI_RDATA[3]	1
Q1_LANE2_DRI_RDATA[4]	1
Q1_LANE2_DRI_RDATA[5]	1
Q1_LANE2_DRI_RDATA[6]	1
Q1_LANE2_DRI_RDATA[7]	1
Q1_LANE2_DRI_RDATA[8]	1
Q1_LANE2_DRI_RDATA[9]	1
Q1_LANE3_DRI_INTERRUPT	1
Q1_LANE3_DRI_RDATA[0]	1
Q1_LANE3_DRI_RDATA[10]	1
Q1_LANE3_DRI_RDATA[11]	1
Q1_LANE3_DRI_RDATA[12]	1
Q1_LANE3_DRI_RDATA[13]	1
Q1_LANE3_DRI_RDATA[14]	1
Q1_LANE3_DRI_RDATA[15]	1
Q1_LANE3_DRI_RDATA[16]	1
Q1_LANE3_DRI_RDATA[17]	1
Q1_LANE3_DRI_RDATA[18]	1
Q1_LANE3_DRI_RDATA[19]	1
Q1_LANE3_DRI_RDATA[1]	1
Q1_LANE3_DRI_RDATA[20]	1
Q1_LANE3_DRI_RDATA[21]	1
Q1_LANE3_DRI_RDATA[22]	1
Q1_LANE3_DRI_RDATA[23]	1
Q1_LANE3_DRI_RDATA[24]	1
Q1_LANE3_DRI_RDATA[25]	1
Q1_LANE3_DRI_RDATA[26]	1
Q1_LANE3_DRI_RDATA[27]	1
Q1_LANE3_DRI_RDATA[28]	1
Q1_LANE3_DRI_RDATA[29]	1
Q1_LANE3_DRI_RDATA[2]	1
Q1_LANE3_DRI_RDATA[30]	1
Q1_LANE3_DRI_RDATA[31]	1
Q1_LANE3_DRI_RDATA[32]	1
Q1_LANE3_DRI_RDATA[3]	1
Q1_LANE3_DRI_RDATA[4]	1
Q1_LANE3_DRI_RDATA[5]	1
Q1_LANE3_DRI_RDATA[6]	1
Q1_LANE3_DRI_RDATA[7]	1
Q1_LANE3_DRI_RDATA[8]	1
Q1_LANE3_DRI_RDATA[9]	1
Q1_TXPLL0_DRI_INTERRUPT	1
Q1_TXPLL0_DRI_RDATA[0]	1
Q1_TXPLL0_DRI_RDATA[10]	1
Q1_TXPLL0_DRI_RDATA[11]	1
Q1_TXPLL0_DRI_RDATA[12]	1
Q1_TXPLL0_DRI_RDATA[13]	1
Q1_TXPLL0_DRI_RDATA[14]	1
Q1_TXPLL0_DRI_RDATA[15]	1
Q1_TXPLL0_DRI_RDATA[16]	1
Q1_TXPLL0_DRI_RDATA[17]	1
Q1_TXPLL0_DRI_RDATA[18]	1
Q1_TXPLL0_DRI_RDATA[19]	1
Q1_TXPLL0_DRI_RDATA[1]	1
Q1_TXPLL0_DRI_RDATA[20]	1
Q1_TXPLL0_DRI_RDATA[21]	1
Q1_TXPLL0_DRI_RDATA[22]	1
Q1_TXPLL0_DRI_RDATA[23]	1
Q1_TXPLL0_DRI_RDATA[24]	1
Q1_TXPLL0_DRI_RDATA[25]	1
Q1_TXPLL0_DRI_RDATA[26]	1
Q1_TXPLL0_DRI_RDATA[27]	1
Q1_TXPLL0_DRI_RDATA[28]	1
Q1_TXPLL0_DRI_RDATA[29]	1
Q1_TXPLL0_DRI_RDATA[2]	1
Q1_TXPLL0_DRI_RDATA[30]	1
Q1_TXPLL0_DRI_RDATA[31]	1
Q1_TXPLL0_DRI_RDATA[32]	1
Q1_TXPLL0_DRI_RDATA[3]	1
Q1_TXPLL0_DRI_RDATA[4]	1
Q1_TXPLL0_DRI_RDATA[5]	1
Q1_TXPLL0_DRI_RDATA[6]	1
Q1_TXPLL0_DRI_RDATA[7]	1
Q1_TXPLL0_DRI_RDATA[8]	1
Q1_TXPLL0_DRI_RDATA[9]	1
Q1_TXPLL1_DRI_INTERRUPT	1
Q1_TXPLL1_DRI_RDATA[0]	1
Q1_TXPLL1_DRI_RDATA[10]	1
Q1_TXPLL1_DRI_RDATA[11]	1
Q1_TXPLL1_DRI_RDATA[12]	1
Q1_TXPLL1_DRI_RDATA[13]	1
Q1_TXPLL1_DRI_RDATA[14]	1
Q1_TXPLL1_DRI_RDATA[15]	1
Q1_TXPLL1_DRI_RDATA[16]	1
Q1_TXPLL1_DRI_RDATA[17]	1
Q1_TXPLL1_DRI_RDATA[18]	1
Q1_TXPLL1_DRI_RDATA[19]	1
Q1_TXPLL1_DRI_RDATA[1]	1
Q1_TXPLL1_DRI_RDATA[20]	1
Q1_TXPLL1_DRI_RDATA[21]	1
Q1_TXPLL1_DRI_RDATA[22]	1
Q1_TXPLL1_DRI_RDATA[23]	1
Q1_TXPLL1_DRI_RDATA[24]	1
Q1_TXPLL1_DRI_RDATA[25]	1
Q1_TXPLL1_DRI_RDATA[26]	1
Q1_TXPLL1_DRI_RDATA[27]	1
Q1_TXPLL1_DRI_RDATA[28]	1
Q1_TXPLL1_DRI_RDATA[29]	1
Q1_TXPLL1_DRI_RDATA[2]	1
Q1_TXPLL1_DRI_RDATA[30]	1
Q1_TXPLL1_DRI_RDATA[31]	1
Q1_TXPLL1_DRI_RDATA[32]	1
Q1_TXPLL1_DRI_RDATA[3]	1
Q1_TXPLL1_DRI_RDATA[4]	1
Q1_TXPLL1_DRI_RDATA[5]	1
Q1_TXPLL1_DRI_RDATA[6]	1
Q1_TXPLL1_DRI_RDATA[7]	1
Q1_TXPLL1_DRI_RDATA[8]	1
Q1_TXPLL1_DRI_RDATA[9]	1
Q1_TXPLL_SSC_DRI_INTERRUPT	1
Q1_TXPLL_SSC_DRI_RDATA[0]	1
Q1_TXPLL_SSC_DRI_RDATA[10]	1
Q1_TXPLL_SSC_DRI_RDATA[11]	1
Q1_TXPLL_SSC_DRI_RDATA[12]	1
Q1_TXPLL_SSC_DRI_RDATA[13]	1
Q1_TXPLL_SSC_DRI_RDATA[14]	1
Q1_TXPLL_SSC_DRI_RDATA[15]	1
Q1_TXPLL_SSC_DRI_RDATA[16]	1
Q1_TXPLL_SSC_DRI_RDATA[17]	1
Q1_TXPLL_SSC_DRI_RDATA[18]	1
Q1_TXPLL_SSC_DRI_RDATA[19]	1
Q1_TXPLL_SSC_DRI_RDATA[1]	1
Q1_TXPLL_SSC_DRI_RDATA[20]	1
Q1_TXPLL_SSC_DRI_RDATA[21]	1
Q1_TXPLL_SSC_DRI_RDATA[22]	1
Q1_TXPLL_SSC_DRI_RDATA[23]	1
Q1_TXPLL_SSC_DRI_RDATA[24]	1
Q1_TXPLL_SSC_DRI_RDATA[25]	1
Q1_TXPLL_SSC_DRI_RDATA[26]	1
Q1_TXPLL_SSC_DRI_RDATA[27]	1
Q1_TXPLL_SSC_DRI_RDATA[28]	1
Q1_TXPLL_SSC_DRI_RDATA[29]	1
Q1_TXPLL_SSC_DRI_RDATA[2]	1
Q1_TXPLL_SSC_DRI_RDATA[30]	1
Q1_TXPLL_SSC_DRI_RDATA[31]	1
Q1_TXPLL_SSC_DRI_RDATA[32]	1
Q1_TXPLL_SSC_DRI_RDATA[3]	1
Q1_TXPLL_SSC_DRI_RDATA[4]	1
Q1_TXPLL_SSC_DRI_RDATA[5]	1
Q1_TXPLL_SSC_DRI_RDATA[6]	1
Q1_TXPLL_SSC_DRI_RDATA[7]	1
Q1_TXPLL_SSC_DRI_RDATA[8]	1
Q1_TXPLL_SSC_DRI_RDATA[9]	1
Q2_LANE0_DRI_INTERRUPT	1
Q2_LANE0_DRI_RDATA[0]	1
Q2_LANE0_DRI_RDATA[10]	1
Q2_LANE0_DRI_RDATA[11]	1
Q2_LANE0_DRI_RDATA[12]	1
Q2_LANE0_DRI_RDATA[13]	1
Q2_LANE0_DRI_RDATA[14]	1
Q2_LANE0_DRI_RDATA[15]	1
Q2_LANE0_DRI_RDATA[16]	1
Q2_LANE0_DRI_RDATA[17]	1
Q2_LANE0_DRI_RDATA[18]	1
Q2_LANE0_DRI_RDATA[19]	1
Q2_LANE0_DRI_RDATA[1]	1
Q2_LANE0_DRI_RDATA[20]	1
Q2_LANE0_DRI_RDATA[21]	1
Q2_LANE0_DRI_RDATA[22]	1
Q2_LANE0_DRI_RDATA[23]	1
Q2_LANE0_DRI_RDATA[24]	1
Q2_LANE0_DRI_RDATA[25]	1
Q2_LANE0_DRI_RDATA[26]	1
Q2_LANE0_DRI_RDATA[27]	1
Q2_LANE0_DRI_RDATA[28]	1
Q2_LANE0_DRI_RDATA[29]	1
Q2_LANE0_DRI_RDATA[2]	1
Q2_LANE0_DRI_RDATA[30]	1
Q2_LANE0_DRI_RDATA[31]	1
Q2_LANE0_DRI_RDATA[32]	1
Q2_LANE0_DRI_RDATA[3]	1
Q2_LANE0_DRI_RDATA[4]	1
Q2_LANE0_DRI_RDATA[5]	1
Q2_LANE0_DRI_RDATA[6]	1
Q2_LANE0_DRI_RDATA[7]	1
Q2_LANE0_DRI_RDATA[8]	1
Q2_LANE0_DRI_RDATA[9]	1
Q2_LANE1_DRI_INTERRUPT	1
Q2_LANE1_DRI_RDATA[0]	1
Q2_LANE1_DRI_RDATA[10]	1
Q2_LANE1_DRI_RDATA[11]	1
Q2_LANE1_DRI_RDATA[12]	1
Q2_LANE1_DRI_RDATA[13]	1
Q2_LANE1_DRI_RDATA[14]	1
Q2_LANE1_DRI_RDATA[15]	1
Q2_LANE1_DRI_RDATA[16]	1
Q2_LANE1_DRI_RDATA[17]	1
Q2_LANE1_DRI_RDATA[18]	1
Q2_LANE1_DRI_RDATA[19]	1
Q2_LANE1_DRI_RDATA[1]	1
Q2_LANE1_DRI_RDATA[20]	1
Q2_LANE1_DRI_RDATA[21]	1
Q2_LANE1_DRI_RDATA[22]	1
Q2_LANE1_DRI_RDATA[23]	1
Q2_LANE1_DRI_RDATA[24]	1
Q2_LANE1_DRI_RDATA[25]	1
Q2_LANE1_DRI_RDATA[26]	1
Q2_LANE1_DRI_RDATA[27]	1
Q2_LANE1_DRI_RDATA[28]	1
Q2_LANE1_DRI_RDATA[29]	1
Q2_LANE1_DRI_RDATA[2]	1
Q2_LANE1_DRI_RDATA[30]	1
Q2_LANE1_DRI_RDATA[31]	1
Q2_LANE1_DRI_RDATA[32]	1
Q2_LANE1_DRI_RDATA[3]	1
Q2_LANE1_DRI_RDATA[4]	1
Q2_LANE1_DRI_RDATA[5]	1
Q2_LANE1_DRI_RDATA[6]	1
Q2_LANE1_DRI_RDATA[7]	1
Q2_LANE1_DRI_RDATA[8]	1
Q2_LANE1_DRI_RDATA[9]	1
Q2_LANE2_DRI_INTERRUPT	1
Q2_LANE2_DRI_RDATA[0]	1
Q2_LANE2_DRI_RDATA[10]	1
Q2_LANE2_DRI_RDATA[11]	1
Q2_LANE2_DRI_RDATA[12]	1
Q2_LANE2_DRI_RDATA[13]	1
Q2_LANE2_DRI_RDATA[14]	1
Q2_LANE2_DRI_RDATA[15]	1
Q2_LANE2_DRI_RDATA[16]	1
Q2_LANE2_DRI_RDATA[17]	1
Q2_LANE2_DRI_RDATA[18]	1
Q2_LANE2_DRI_RDATA[19]	1
Q2_LANE2_DRI_RDATA[1]	1
Q2_LANE2_DRI_RDATA[20]	1
Q2_LANE2_DRI_RDATA[21]	1
Q2_LANE2_DRI_RDATA[22]	1
Q2_LANE2_DRI_RDATA[23]	1
Q2_LANE2_DRI_RDATA[24]	1
Q2_LANE2_DRI_RDATA[25]	1
Q2_LANE2_DRI_RDATA[26]	1
Q2_LANE2_DRI_RDATA[27]	1
Q2_LANE2_DRI_RDATA[28]	1
Q2_LANE2_DRI_RDATA[29]	1
Q2_LANE2_DRI_RDATA[2]	1
Q2_LANE2_DRI_RDATA[30]	1
Q2_LANE2_DRI_RDATA[31]	1
Q2_LANE2_DRI_RDATA[32]	1
Q2_LANE2_DRI_RDATA[3]	1
Q2_LANE2_DRI_RDATA[4]	1
Q2_LANE2_DRI_RDATA[5]	1
Q2_LANE2_DRI_RDATA[6]	1
Q2_LANE2_DRI_RDATA[7]	1
Q2_LANE2_DRI_RDATA[8]	1
Q2_LANE2_DRI_RDATA[9]	1
Q2_LANE3_DRI_INTERRUPT	1
Q2_LANE3_DRI_RDATA[0]	1
Q2_LANE3_DRI_RDATA[10]	1
Q2_LANE3_DRI_RDATA[11]	1
Q2_LANE3_DRI_RDATA[12]	1
Q2_LANE3_DRI_RDATA[13]	1
Q2_LANE3_DRI_RDATA[14]	1
Q2_LANE3_DRI_RDATA[15]	1
Q2_LANE3_DRI_RDATA[16]	1
Q2_LANE3_DRI_RDATA[17]	1
Q2_LANE3_DRI_RDATA[18]	1
Q2_LANE3_DRI_RDATA[19]	1
Q2_LANE3_DRI_RDATA[1]	1
Q2_LANE3_DRI_RDATA[20]	1
Q2_LANE3_DRI_RDATA[21]	1
Q2_LANE3_DRI_RDATA[22]	1
Q2_LANE3_DRI_RDATA[23]	1
Q2_LANE3_DRI_RDATA[24]	1
Q2_LANE3_DRI_RDATA[25]	1
Q2_LANE3_DRI_RDATA[26]	1
Q2_LANE3_DRI_RDATA[27]	1
Q2_LANE3_DRI_RDATA[28]	1
Q2_LANE3_DRI_RDATA[29]	1
Q2_LANE3_DRI_RDATA[2]	1
Q2_LANE3_DRI_RDATA[30]	1
Q2_LANE3_DRI_RDATA[31]	1
Q2_LANE3_DRI_RDATA[32]	1
Q2_LANE3_DRI_RDATA[3]	1
Q2_LANE3_DRI_RDATA[4]	1
Q2_LANE3_DRI_RDATA[5]	1
Q2_LANE3_DRI_RDATA[6]	1
Q2_LANE3_DRI_RDATA[7]	1
Q2_LANE3_DRI_RDATA[8]	1
Q2_LANE3_DRI_RDATA[9]	1
Q2_TXPLL0_DRI_INTERRUPT	1
Q2_TXPLL0_DRI_RDATA[0]	1
Q2_TXPLL0_DRI_RDATA[10]	1
Q2_TXPLL0_DRI_RDATA[11]	1
Q2_TXPLL0_DRI_RDATA[12]	1
Q2_TXPLL0_DRI_RDATA[13]	1
Q2_TXPLL0_DRI_RDATA[14]	1
Q2_TXPLL0_DRI_RDATA[15]	1
Q2_TXPLL0_DRI_RDATA[16]	1
Q2_TXPLL0_DRI_RDATA[17]	1
Q2_TXPLL0_DRI_RDATA[18]	1
Q2_TXPLL0_DRI_RDATA[19]	1
Q2_TXPLL0_DRI_RDATA[1]	1
Q2_TXPLL0_DRI_RDATA[20]	1
Q2_TXPLL0_DRI_RDATA[21]	1
Q2_TXPLL0_DRI_RDATA[22]	1
Q2_TXPLL0_DRI_RDATA[23]	1
Q2_TXPLL0_DRI_RDATA[24]	1
Q2_TXPLL0_DRI_RDATA[25]	1
Q2_TXPLL0_DRI_RDATA[26]	1
Q2_TXPLL0_DRI_RDATA[27]	1
Q2_TXPLL0_DRI_RDATA[28]	1
Q2_TXPLL0_DRI_RDATA[29]	1
Q2_TXPLL0_DRI_RDATA[2]	1
Q2_TXPLL0_DRI_RDATA[30]	1
Q2_TXPLL0_DRI_RDATA[31]	1
Q2_TXPLL0_DRI_RDATA[32]	1
Q2_TXPLL0_DRI_RDATA[3]	1
Q2_TXPLL0_DRI_RDATA[4]	1
Q2_TXPLL0_DRI_RDATA[5]	1
Q2_TXPLL0_DRI_RDATA[6]	1
Q2_TXPLL0_DRI_RDATA[7]	1
Q2_TXPLL0_DRI_RDATA[8]	1
Q2_TXPLL0_DRI_RDATA[9]	1
Q2_TXPLL1_DRI_INTERRUPT	1
Q2_TXPLL1_DRI_RDATA[0]	1
Q2_TXPLL1_DRI_RDATA[10]	1
Q2_TXPLL1_DRI_RDATA[11]	1
Q2_TXPLL1_DRI_RDATA[12]	1
Q2_TXPLL1_DRI_RDATA[13]	1
Q2_TXPLL1_DRI_RDATA[14]	1
Q2_TXPLL1_DRI_RDATA[15]	1
Q2_TXPLL1_DRI_RDATA[16]	1
Q2_TXPLL1_DRI_RDATA[17]	1
Q2_TXPLL1_DRI_RDATA[18]	1
Q2_TXPLL1_DRI_RDATA[19]	1
Q2_TXPLL1_DRI_RDATA[1]	1
Q2_TXPLL1_DRI_RDATA[20]	1
Q2_TXPLL1_DRI_RDATA[21]	1
Q2_TXPLL1_DRI_RDATA[22]	1
Q2_TXPLL1_DRI_RDATA[23]	1
Q2_TXPLL1_DRI_RDATA[24]	1
Q2_TXPLL1_DRI_RDATA[25]	1
Q2_TXPLL1_DRI_RDATA[26]	1
Q2_TXPLL1_DRI_RDATA[27]	1
Q2_TXPLL1_DRI_RDATA[28]	1
Q2_TXPLL1_DRI_RDATA[29]	1
Q2_TXPLL1_DRI_RDATA[2]	1
Q2_TXPLL1_DRI_RDATA[30]	1
Q2_TXPLL1_DRI_RDATA[31]	1
Q2_TXPLL1_DRI_RDATA[32]	1
Q2_TXPLL1_DRI_RDATA[3]	1
Q2_TXPLL1_DRI_RDATA[4]	1
Q2_TXPLL1_DRI_RDATA[5]	1
Q2_TXPLL1_DRI_RDATA[6]	1
Q2_TXPLL1_DRI_RDATA[7]	1
Q2_TXPLL1_DRI_RDATA[8]	1
Q2_TXPLL1_DRI_RDATA[9]	1
Q2_TXPLL_SSC_DRI_INTERRUPT	1
Q2_TXPLL_SSC_DRI_RDATA[0]	1
Q2_TXPLL_SSC_DRI_RDATA[10]	1
Q2_TXPLL_SSC_DRI_RDATA[11]	1
Q2_TXPLL_SSC_DRI_RDATA[12]	1
Q2_TXPLL_SSC_DRI_RDATA[13]	1
Q2_TXPLL_SSC_DRI_RDATA[14]	1
Q2_TXPLL_SSC_DRI_RDATA[15]	1
Q2_TXPLL_SSC_DRI_RDATA[16]	1
Q2_TXPLL_SSC_DRI_RDATA[17]	1
Q2_TXPLL_SSC_DRI_RDATA[18]	1
Q2_TXPLL_SSC_DRI_RDATA[19]	1
Q2_TXPLL_SSC_DRI_RDATA[1]	1
Q2_TXPLL_SSC_DRI_RDATA[20]	1
Q2_TXPLL_SSC_DRI_RDATA[21]	1
Q2_TXPLL_SSC_DRI_RDATA[22]	1
Q2_TXPLL_SSC_DRI_RDATA[23]	1
Q2_TXPLL_SSC_DRI_RDATA[24]	1
Q2_TXPLL_SSC_DRI_RDATA[25]	1
Q2_TXPLL_SSC_DRI_RDATA[26]	1
Q2_TXPLL_SSC_DRI_RDATA[27]	1
Q2_TXPLL_SSC_DRI_RDATA[28]	1
Q2_TXPLL_SSC_DRI_RDATA[29]	1
Q2_TXPLL_SSC_DRI_RDATA[2]	1
Q2_TXPLL_SSC_DRI_RDATA[30]	1
Q2_TXPLL_SSC_DRI_RDATA[31]	1
Q2_TXPLL_SSC_DRI_RDATA[32]	1
Q2_TXPLL_SSC_DRI_RDATA[3]	1
Q2_TXPLL_SSC_DRI_RDATA[4]	1
Q2_TXPLL_SSC_DRI_RDATA[5]	1
Q2_TXPLL_SSC_DRI_RDATA[6]	1
Q2_TXPLL_SSC_DRI_RDATA[7]	1
Q2_TXPLL_SSC_DRI_RDATA[8]	1
Q2_TXPLL_SSC_DRI_RDATA[9]	1
Q3_LANE0_DRI_INTERRUPT	1
Q3_LANE0_DRI_RDATA[0]	1
Q3_LANE0_DRI_RDATA[10]	1
Q3_LANE0_DRI_RDATA[11]	1
Q3_LANE0_DRI_RDATA[12]	1
Q3_LANE0_DRI_RDATA[13]	1
Q3_LANE0_DRI_RDATA[14]	1
Q3_LANE0_DRI_RDATA[15]	1
Q3_LANE0_DRI_RDATA[16]	1
Q3_LANE0_DRI_RDATA[17]	1
Q3_LANE0_DRI_RDATA[18]	1
Q3_LANE0_DRI_RDATA[19]	1
Q3_LANE0_DRI_RDATA[1]	1
Q3_LANE0_DRI_RDATA[20]	1
Q3_LANE0_DRI_RDATA[21]	1
Q3_LANE0_DRI_RDATA[22]	1
Q3_LANE0_DRI_RDATA[23]	1
Q3_LANE0_DRI_RDATA[24]	1
Q3_LANE0_DRI_RDATA[25]	1
Q3_LANE0_DRI_RDATA[26]	1
Q3_LANE0_DRI_RDATA[27]	1
Q3_LANE0_DRI_RDATA[28]	1
Q3_LANE0_DRI_RDATA[29]	1
Q3_LANE0_DRI_RDATA[2]	1
Q3_LANE0_DRI_RDATA[30]	1
Q3_LANE0_DRI_RDATA[31]	1
Q3_LANE0_DRI_RDATA[32]	1
Q3_LANE0_DRI_RDATA[3]	1
Q3_LANE0_DRI_RDATA[4]	1
Q3_LANE0_DRI_RDATA[5]	1
Q3_LANE0_DRI_RDATA[6]	1
Q3_LANE0_DRI_RDATA[7]	1
Q3_LANE0_DRI_RDATA[8]	1
Q3_LANE0_DRI_RDATA[9]	1
Q3_LANE1_DRI_INTERRUPT	1
Q3_LANE1_DRI_RDATA[0]	1
Q3_LANE1_DRI_RDATA[10]	1
Q3_LANE1_DRI_RDATA[11]	1
Q3_LANE1_DRI_RDATA[12]	1
Q3_LANE1_DRI_RDATA[13]	1
Q3_LANE1_DRI_RDATA[14]	1
Q3_LANE1_DRI_RDATA[15]	1
Q3_LANE1_DRI_RDATA[16]	1
Q3_LANE1_DRI_RDATA[17]	1
Q3_LANE1_DRI_RDATA[18]	1
Q3_LANE1_DRI_RDATA[19]	1
Q3_LANE1_DRI_RDATA[1]	1
Q3_LANE1_DRI_RDATA[20]	1
Q3_LANE1_DRI_RDATA[21]	1
Q3_LANE1_DRI_RDATA[22]	1
Q3_LANE1_DRI_RDATA[23]	1
Q3_LANE1_DRI_RDATA[24]	1
Q3_LANE1_DRI_RDATA[25]	1
Q3_LANE1_DRI_RDATA[26]	1
Q3_LANE1_DRI_RDATA[27]	1
Q3_LANE1_DRI_RDATA[28]	1
Q3_LANE1_DRI_RDATA[29]	1
Q3_LANE1_DRI_RDATA[2]	1
Q3_LANE1_DRI_RDATA[30]	1
Q3_LANE1_DRI_RDATA[31]	1
Q3_LANE1_DRI_RDATA[32]	1
Q3_LANE1_DRI_RDATA[3]	1
Q3_LANE1_DRI_RDATA[4]	1
Q3_LANE1_DRI_RDATA[5]	1
Q3_LANE1_DRI_RDATA[6]	1
Q3_LANE1_DRI_RDATA[7]	1
Q3_LANE1_DRI_RDATA[8]	1
Q3_LANE1_DRI_RDATA[9]	1
Q3_LANE2_DRI_INTERRUPT	1
Q3_LANE2_DRI_RDATA[0]	1
Q3_LANE2_DRI_RDATA[10]	1
Q3_LANE2_DRI_RDATA[11]	1
Q3_LANE2_DRI_RDATA[12]	1
Q3_LANE2_DRI_RDATA[13]	1
Q3_LANE2_DRI_RDATA[14]	1
Q3_LANE2_DRI_RDATA[15]	1
Q3_LANE2_DRI_RDATA[16]	1
Q3_LANE2_DRI_RDATA[17]	1
Q3_LANE2_DRI_RDATA[18]	1
Q3_LANE2_DRI_RDATA[19]	1
Q3_LANE2_DRI_RDATA[1]	1
Q3_LANE2_DRI_RDATA[20]	1
Q3_LANE2_DRI_RDATA[21]	1
Q3_LANE2_DRI_RDATA[22]	1
Q3_LANE2_DRI_RDATA[23]	1
Q3_LANE2_DRI_RDATA[24]	1
Q3_LANE2_DRI_RDATA[25]	1
Q3_LANE2_DRI_RDATA[26]	1
Q3_LANE2_DRI_RDATA[27]	1
Q3_LANE2_DRI_RDATA[28]	1
Q3_LANE2_DRI_RDATA[29]	1
Q3_LANE2_DRI_RDATA[2]	1
Q3_LANE2_DRI_RDATA[30]	1
Q3_LANE2_DRI_RDATA[31]	1
Q3_LANE2_DRI_RDATA[32]	1
Q3_LANE2_DRI_RDATA[3]	1
Q3_LANE2_DRI_RDATA[4]	1
Q3_LANE2_DRI_RDATA[5]	1
Q3_LANE2_DRI_RDATA[6]	1
Q3_LANE2_DRI_RDATA[7]	1
Q3_LANE2_DRI_RDATA[8]	1
Q3_LANE2_DRI_RDATA[9]	1
Q3_LANE3_DRI_INTERRUPT	1
Q3_LANE3_DRI_RDATA[0]	1
Q3_LANE3_DRI_RDATA[10]	1
Q3_LANE3_DRI_RDATA[11]	1
Q3_LANE3_DRI_RDATA[12]	1
Q3_LANE3_DRI_RDATA[13]	1
Q3_LANE3_DRI_RDATA[14]	1
Q3_LANE3_DRI_RDATA[15]	1
Q3_LANE3_DRI_RDATA[16]	1
Q3_LANE3_DRI_RDATA[17]	1
Q3_LANE3_DRI_RDATA[18]	1
Q3_LANE3_DRI_RDATA[19]	1
Q3_LANE3_DRI_RDATA[1]	1
Q3_LANE3_DRI_RDATA[20]	1
Q3_LANE3_DRI_RDATA[21]	1
Q3_LANE3_DRI_RDATA[22]	1
Q3_LANE3_DRI_RDATA[23]	1
Q3_LANE3_DRI_RDATA[24]	1
Q3_LANE3_DRI_RDATA[25]	1
Q3_LANE3_DRI_RDATA[26]	1
Q3_LANE3_DRI_RDATA[27]	1
Q3_LANE3_DRI_RDATA[28]	1
Q3_LANE3_DRI_RDATA[29]	1
Q3_LANE3_DRI_RDATA[2]	1
Q3_LANE3_DRI_RDATA[30]	1
Q3_LANE3_DRI_RDATA[31]	1
Q3_LANE3_DRI_RDATA[32]	1
Q3_LANE3_DRI_RDATA[3]	1
Q3_LANE3_DRI_RDATA[4]	1
Q3_LANE3_DRI_RDATA[5]	1
Q3_LANE3_DRI_RDATA[6]	1
Q3_LANE3_DRI_RDATA[7]	1
Q3_LANE3_DRI_RDATA[8]	1
Q3_LANE3_DRI_RDATA[9]	1
Q3_TXPLL_DRI_INTERRUPT	1
Q3_TXPLL_DRI_RDATA[0]	1
Q3_TXPLL_DRI_RDATA[10]	1
Q3_TXPLL_DRI_RDATA[11]	1
Q3_TXPLL_DRI_RDATA[12]	1
Q3_TXPLL_DRI_RDATA[13]	1
Q3_TXPLL_DRI_RDATA[14]	1
Q3_TXPLL_DRI_RDATA[15]	1
Q3_TXPLL_DRI_RDATA[16]	1
Q3_TXPLL_DRI_RDATA[17]	1
Q3_TXPLL_DRI_RDATA[18]	1
Q3_TXPLL_DRI_RDATA[19]	1
Q3_TXPLL_DRI_RDATA[1]	1
Q3_TXPLL_DRI_RDATA[20]	1
Q3_TXPLL_DRI_RDATA[21]	1
Q3_TXPLL_DRI_RDATA[22]	1
Q3_TXPLL_DRI_RDATA[23]	1
Q3_TXPLL_DRI_RDATA[24]	1
Q3_TXPLL_DRI_RDATA[25]	1
Q3_TXPLL_DRI_RDATA[26]	1
Q3_TXPLL_DRI_RDATA[27]	1
Q3_TXPLL_DRI_RDATA[28]	1
Q3_TXPLL_DRI_RDATA[29]	1
Q3_TXPLL_DRI_RDATA[2]	1
Q3_TXPLL_DRI_RDATA[30]	1
Q3_TXPLL_DRI_RDATA[31]	1
Q3_TXPLL_DRI_RDATA[32]	1
Q3_TXPLL_DRI_RDATA[3]	1
Q3_TXPLL_DRI_RDATA[4]	1
Q3_TXPLL_DRI_RDATA[5]	1
Q3_TXPLL_DRI_RDATA[6]	1
Q3_TXPLL_DRI_RDATA[7]	1
Q3_TXPLL_DRI_RDATA[8]	1
Q3_TXPLL_DRI_RDATA[9]	1
Q3_TXPLL_SSC_DRI_INTERRUPT	1
Q3_TXPLL_SSC_DRI_RDATA[0]	1
Q3_TXPLL_SSC_DRI_RDATA[10]	1
Q3_TXPLL_SSC_DRI_RDATA[11]	1
Q3_TXPLL_SSC_DRI_RDATA[12]	1
Q3_TXPLL_SSC_DRI_RDATA[13]	1
Q3_TXPLL_SSC_DRI_RDATA[14]	1
Q3_TXPLL_SSC_DRI_RDATA[15]	1
Q3_TXPLL_SSC_DRI_RDATA[16]	1
Q3_TXPLL_SSC_DRI_RDATA[17]	1
Q3_TXPLL_SSC_DRI_RDATA[18]	1
Q3_TXPLL_SSC_DRI_RDATA[19]	1
Q3_TXPLL_SSC_DRI_RDATA[1]	1
Q3_TXPLL_SSC_DRI_RDATA[20]	1
Q3_TXPLL_SSC_DRI_RDATA[21]	1
Q3_TXPLL_SSC_DRI_RDATA[22]	1
Q3_TXPLL_SSC_DRI_RDATA[23]	1
Q3_TXPLL_SSC_DRI_RDATA[24]	1
Q3_TXPLL_SSC_DRI_RDATA[25]	1
Q3_TXPLL_SSC_DRI_RDATA[26]	1
Q3_TXPLL_SSC_DRI_RDATA[27]	1
Q3_TXPLL_SSC_DRI_RDATA[28]	1
Q3_TXPLL_SSC_DRI_RDATA[29]	1
Q3_TXPLL_SSC_DRI_RDATA[2]	1
Q3_TXPLL_SSC_DRI_RDATA[30]	1
Q3_TXPLL_SSC_DRI_RDATA[31]	1
Q3_TXPLL_SSC_DRI_RDATA[32]	1
Q3_TXPLL_SSC_DRI_RDATA[3]	1
Q3_TXPLL_SSC_DRI_RDATA[4]	1
Q3_TXPLL_SSC_DRI_RDATA[5]	1
Q3_TXPLL_SSC_DRI_RDATA[6]	1
Q3_TXPLL_SSC_DRI_RDATA[7]	1
Q3_TXPLL_SSC_DRI_RDATA[8]	1
Q3_TXPLL_SSC_DRI_RDATA[9]	1
Q4_LANE0_DRI_INTERRUPT	1
Q4_LANE0_DRI_RDATA[0]	1
Q4_LANE0_DRI_RDATA[10]	1
Q4_LANE0_DRI_RDATA[11]	1
Q4_LANE0_DRI_RDATA[12]	1
Q4_LANE0_DRI_RDATA[13]	1
Q4_LANE0_DRI_RDATA[14]	1
Q4_LANE0_DRI_RDATA[15]	1
Q4_LANE0_DRI_RDATA[16]	1
Q4_LANE0_DRI_RDATA[17]	1
Q4_LANE0_DRI_RDATA[18]	1
Q4_LANE0_DRI_RDATA[19]	1
Q4_LANE0_DRI_RDATA[1]	1
Q4_LANE0_DRI_RDATA[20]	1
Q4_LANE0_DRI_RDATA[21]	1
Q4_LANE0_DRI_RDATA[22]	1
Q4_LANE0_DRI_RDATA[23]	1
Q4_LANE0_DRI_RDATA[24]	1
Q4_LANE0_DRI_RDATA[25]	1
Q4_LANE0_DRI_RDATA[26]	1
Q4_LANE0_DRI_RDATA[27]	1
Q4_LANE0_DRI_RDATA[28]	1
Q4_LANE0_DRI_RDATA[29]	1
Q4_LANE0_DRI_RDATA[2]	1
Q4_LANE0_DRI_RDATA[30]	1
Q4_LANE0_DRI_RDATA[31]	1
Q4_LANE0_DRI_RDATA[32]	1
Q4_LANE0_DRI_RDATA[3]	1
Q4_LANE0_DRI_RDATA[4]	1
Q4_LANE0_DRI_RDATA[5]	1
Q4_LANE0_DRI_RDATA[6]	1
Q4_LANE0_DRI_RDATA[7]	1
Q4_LANE0_DRI_RDATA[8]	1
Q4_LANE0_DRI_RDATA[9]	1
Q4_LANE1_DRI_INTERRUPT	1
Q4_LANE1_DRI_RDATA[0]	1
Q4_LANE1_DRI_RDATA[10]	1
Q4_LANE1_DRI_RDATA[11]	1
Q4_LANE1_DRI_RDATA[12]	1
Q4_LANE1_DRI_RDATA[13]	1
Q4_LANE1_DRI_RDATA[14]	1
Q4_LANE1_DRI_RDATA[15]	1
Q4_LANE1_DRI_RDATA[16]	1
Q4_LANE1_DRI_RDATA[17]	1
Q4_LANE1_DRI_RDATA[18]	1
Q4_LANE1_DRI_RDATA[19]	1
Q4_LANE1_DRI_RDATA[1]	1
Q4_LANE1_DRI_RDATA[20]	1
Q4_LANE1_DRI_RDATA[21]	1
Q4_LANE1_DRI_RDATA[22]	1
Q4_LANE1_DRI_RDATA[23]	1
Q4_LANE1_DRI_RDATA[24]	1
Q4_LANE1_DRI_RDATA[25]	1
Q4_LANE1_DRI_RDATA[26]	1
Q4_LANE1_DRI_RDATA[27]	1
Q4_LANE1_DRI_RDATA[28]	1
Q4_LANE1_DRI_RDATA[29]	1
Q4_LANE1_DRI_RDATA[2]	1
Q4_LANE1_DRI_RDATA[30]	1
Q4_LANE1_DRI_RDATA[31]	1
Q4_LANE1_DRI_RDATA[32]	1
Q4_LANE1_DRI_RDATA[3]	1
Q4_LANE1_DRI_RDATA[4]	1
Q4_LANE1_DRI_RDATA[5]	1
Q4_LANE1_DRI_RDATA[6]	1
Q4_LANE1_DRI_RDATA[7]	1
Q4_LANE1_DRI_RDATA[8]	1
Q4_LANE1_DRI_RDATA[9]	1
Q4_LANE2_DRI_INTERRUPT	1
Q4_LANE2_DRI_RDATA[0]	1
Q4_LANE2_DRI_RDATA[10]	1
Q4_LANE2_DRI_RDATA[11]	1
Q4_LANE2_DRI_RDATA[12]	1
Q4_LANE2_DRI_RDATA[13]	1
Q4_LANE2_DRI_RDATA[14]	1
Q4_LANE2_DRI_RDATA[15]	1
Q4_LANE2_DRI_RDATA[16]	1
Q4_LANE2_DRI_RDATA[17]	1
Q4_LANE2_DRI_RDATA[18]	1
Q4_LANE2_DRI_RDATA[19]	1
Q4_LANE2_DRI_RDATA[1]	1
Q4_LANE2_DRI_RDATA[20]	1
Q4_LANE2_DRI_RDATA[21]	1
Q4_LANE2_DRI_RDATA[22]	1
Q4_LANE2_DRI_RDATA[23]	1
Q4_LANE2_DRI_RDATA[24]	1
Q4_LANE2_DRI_RDATA[25]	1
Q4_LANE2_DRI_RDATA[26]	1
Q4_LANE2_DRI_RDATA[27]	1
Q4_LANE2_DRI_RDATA[28]	1
Q4_LANE2_DRI_RDATA[29]	1
Q4_LANE2_DRI_RDATA[2]	1
Q4_LANE2_DRI_RDATA[30]	1
Q4_LANE2_DRI_RDATA[31]	1
Q4_LANE2_DRI_RDATA[32]	1
Q4_LANE2_DRI_RDATA[3]	1
Q4_LANE2_DRI_RDATA[4]	1
Q4_LANE2_DRI_RDATA[5]	1
Q4_LANE2_DRI_RDATA[6]	1
Q4_LANE2_DRI_RDATA[7]	1
Q4_LANE2_DRI_RDATA[8]	1
Q4_LANE2_DRI_RDATA[9]	1
Q4_LANE3_DRI_INTERRUPT	1
Q4_LANE3_DRI_RDATA[0]	1
Q4_LANE3_DRI_RDATA[10]	1
Q4_LANE3_DRI_RDATA[11]	1
Q4_LANE3_DRI_RDATA[12]	1
Q4_LANE3_DRI_RDATA[13]	1
Q4_LANE3_DRI_RDATA[14]	1
Q4_LANE3_DRI_RDATA[15]	1
Q4_LANE3_DRI_RDATA[16]	1
Q4_LANE3_DRI_RDATA[17]	1
Q4_LANE3_DRI_RDATA[18]	1
Q4_LANE3_DRI_RDATA[19]	1
Q4_LANE3_DRI_RDATA[1]	1
Q4_LANE3_DRI_RDATA[20]	1
Q4_LANE3_DRI_RDATA[21]	1
Q4_LANE3_DRI_RDATA[22]	1
Q4_LANE3_DRI_RDATA[23]	1
Q4_LANE3_DRI_RDATA[24]	1
Q4_LANE3_DRI_RDATA[25]	1
Q4_LANE3_DRI_RDATA[26]	1
Q4_LANE3_DRI_RDATA[27]	1
Q4_LANE3_DRI_RDATA[28]	1
Q4_LANE3_DRI_RDATA[29]	1
Q4_LANE3_DRI_RDATA[2]	1
Q4_LANE3_DRI_RDATA[30]	1
Q4_LANE3_DRI_RDATA[31]	1
Q4_LANE3_DRI_RDATA[32]	1
Q4_LANE3_DRI_RDATA[3]	1
Q4_LANE3_DRI_RDATA[4]	1
Q4_LANE3_DRI_RDATA[5]	1
Q4_LANE3_DRI_RDATA[6]	1
Q4_LANE3_DRI_RDATA[7]	1
Q4_LANE3_DRI_RDATA[8]	1
Q4_LANE3_DRI_RDATA[9]	1
Q4_TXPLL_DRI_INTERRUPT	1
Q4_TXPLL_DRI_RDATA[0]	1
Q4_TXPLL_DRI_RDATA[10]	1
Q4_TXPLL_DRI_RDATA[11]	1
Q4_TXPLL_DRI_RDATA[12]	1
Q4_TXPLL_DRI_RDATA[13]	1
Q4_TXPLL_DRI_RDATA[14]	1
Q4_TXPLL_DRI_RDATA[15]	1
Q4_TXPLL_DRI_RDATA[16]	1
Q4_TXPLL_DRI_RDATA[17]	1
Q4_TXPLL_DRI_RDATA[18]	1
Q4_TXPLL_DRI_RDATA[19]	1
Q4_TXPLL_DRI_RDATA[1]	1
Q4_TXPLL_DRI_RDATA[20]	1
Q4_TXPLL_DRI_RDATA[21]	1
Q4_TXPLL_DRI_RDATA[22]	1
Q4_TXPLL_DRI_RDATA[23]	1
Q4_TXPLL_DRI_RDATA[24]	1
Q4_TXPLL_DRI_RDATA[25]	1
Q4_TXPLL_DRI_RDATA[26]	1
Q4_TXPLL_DRI_RDATA[27]	1
Q4_TXPLL_DRI_RDATA[28]	1
Q4_TXPLL_DRI_RDATA[29]	1
Q4_TXPLL_DRI_RDATA[2]	1
Q4_TXPLL_DRI_RDATA[30]	1
Q4_TXPLL_DRI_RDATA[31]	1
Q4_TXPLL_DRI_RDATA[32]	1
Q4_TXPLL_DRI_RDATA[3]	1
Q4_TXPLL_DRI_RDATA[4]	1
Q4_TXPLL_DRI_RDATA[5]	1
Q4_TXPLL_DRI_RDATA[6]	1
Q4_TXPLL_DRI_RDATA[7]	1
Q4_TXPLL_DRI_RDATA[8]	1
Q4_TXPLL_DRI_RDATA[9]	1
Q4_TXPLL_SSC_DRI_INTERRUPT	1
Q4_TXPLL_SSC_DRI_RDATA[0]	1
Q4_TXPLL_SSC_DRI_RDATA[10]	1
Q4_TXPLL_SSC_DRI_RDATA[11]	1
Q4_TXPLL_SSC_DRI_RDATA[12]	1
Q4_TXPLL_SSC_DRI_RDATA[13]	1
Q4_TXPLL_SSC_DRI_RDATA[14]	1
Q4_TXPLL_SSC_DRI_RDATA[15]	1
Q4_TXPLL_SSC_DRI_RDATA[16]	1
Q4_TXPLL_SSC_DRI_RDATA[17]	1
Q4_TXPLL_SSC_DRI_RDATA[18]	1
Q4_TXPLL_SSC_DRI_RDATA[19]	1
Q4_TXPLL_SSC_DRI_RDATA[1]	1
Q4_TXPLL_SSC_DRI_RDATA[20]	1
Q4_TXPLL_SSC_DRI_RDATA[21]	1
Q4_TXPLL_SSC_DRI_RDATA[22]	1
Q4_TXPLL_SSC_DRI_RDATA[23]	1
Q4_TXPLL_SSC_DRI_RDATA[24]	1
Q4_TXPLL_SSC_DRI_RDATA[25]	1
Q4_TXPLL_SSC_DRI_RDATA[26]	1
Q4_TXPLL_SSC_DRI_RDATA[27]	1
Q4_TXPLL_SSC_DRI_RDATA[28]	1
Q4_TXPLL_SSC_DRI_RDATA[29]	1
Q4_TXPLL_SSC_DRI_RDATA[2]	1
Q4_TXPLL_SSC_DRI_RDATA[30]	1
Q4_TXPLL_SSC_DRI_RDATA[31]	1
Q4_TXPLL_SSC_DRI_RDATA[32]	1
Q4_TXPLL_SSC_DRI_RDATA[3]	1
Q4_TXPLL_SSC_DRI_RDATA[4]	1
Q4_TXPLL_SSC_DRI_RDATA[5]	1
Q4_TXPLL_SSC_DRI_RDATA[6]	1
Q4_TXPLL_SSC_DRI_RDATA[7]	1
Q4_TXPLL_SSC_DRI_RDATA[8]	1
Q4_TXPLL_SSC_DRI_RDATA[9]	1
Q5_LANE0_DRI_INTERRUPT	1
Q5_LANE0_DRI_RDATA[0]	1
Q5_LANE0_DRI_RDATA[10]	1
Q5_LANE0_DRI_RDATA[11]	1
Q5_LANE0_DRI_RDATA[12]	1
Q5_LANE0_DRI_RDATA[13]	1
Q5_LANE0_DRI_RDATA[14]	1
Q5_LANE0_DRI_RDATA[15]	1
Q5_LANE0_DRI_RDATA[16]	1
Q5_LANE0_DRI_RDATA[17]	1
Q5_LANE0_DRI_RDATA[18]	1
Q5_LANE0_DRI_RDATA[19]	1
Q5_LANE0_DRI_RDATA[1]	1
Q5_LANE0_DRI_RDATA[20]	1
Q5_LANE0_DRI_RDATA[21]	1
Q5_LANE0_DRI_RDATA[22]	1
Q5_LANE0_DRI_RDATA[23]	1
Q5_LANE0_DRI_RDATA[24]	1
Q5_LANE0_DRI_RDATA[25]	1
Q5_LANE0_DRI_RDATA[26]	1
Q5_LANE0_DRI_RDATA[27]	1
Q5_LANE0_DRI_RDATA[28]	1
Q5_LANE0_DRI_RDATA[29]	1
Q5_LANE0_DRI_RDATA[2]	1
Q5_LANE0_DRI_RDATA[30]	1
Q5_LANE0_DRI_RDATA[31]	1
Q5_LANE0_DRI_RDATA[32]	1
Q5_LANE0_DRI_RDATA[3]	1
Q5_LANE0_DRI_RDATA[4]	1
Q5_LANE0_DRI_RDATA[5]	1
Q5_LANE0_DRI_RDATA[6]	1
Q5_LANE0_DRI_RDATA[7]	1
Q5_LANE0_DRI_RDATA[8]	1
Q5_LANE0_DRI_RDATA[9]	1
Q5_LANE1_DRI_INTERRUPT	1
Q5_LANE1_DRI_RDATA[0]	1
Q5_LANE1_DRI_RDATA[10]	1
Q5_LANE1_DRI_RDATA[11]	1
Q5_LANE1_DRI_RDATA[12]	1
Q5_LANE1_DRI_RDATA[13]	1
Q5_LANE1_DRI_RDATA[14]	1
Q5_LANE1_DRI_RDATA[15]	1
Q5_LANE1_DRI_RDATA[16]	1
Q5_LANE1_DRI_RDATA[17]	1
Q5_LANE1_DRI_RDATA[18]	1
Q5_LANE1_DRI_RDATA[19]	1
Q5_LANE1_DRI_RDATA[1]	1
Q5_LANE1_DRI_RDATA[20]	1
Q5_LANE1_DRI_RDATA[21]	1
Q5_LANE1_DRI_RDATA[22]	1
Q5_LANE1_DRI_RDATA[23]	1
Q5_LANE1_DRI_RDATA[24]	1
Q5_LANE1_DRI_RDATA[25]	1
Q5_LANE1_DRI_RDATA[26]	1
Q5_LANE1_DRI_RDATA[27]	1
Q5_LANE1_DRI_RDATA[28]	1
Q5_LANE1_DRI_RDATA[29]	1
Q5_LANE1_DRI_RDATA[2]	1
Q5_LANE1_DRI_RDATA[30]	1
Q5_LANE1_DRI_RDATA[31]	1
Q5_LANE1_DRI_RDATA[32]	1
Q5_LANE1_DRI_RDATA[3]	1
Q5_LANE1_DRI_RDATA[4]	1
Q5_LANE1_DRI_RDATA[5]	1
Q5_LANE1_DRI_RDATA[6]	1
Q5_LANE1_DRI_RDATA[7]	1
Q5_LANE1_DRI_RDATA[8]	1
Q5_LANE1_DRI_RDATA[9]	1
Q5_LANE2_DRI_INTERRUPT	1
Q5_LANE2_DRI_RDATA[0]	1
Q5_LANE2_DRI_RDATA[10]	1
Q5_LANE2_DRI_RDATA[11]	1
Q5_LANE2_DRI_RDATA[12]	1
Q5_LANE2_DRI_RDATA[13]	1
Q5_LANE2_DRI_RDATA[14]	1
Q5_LANE2_DRI_RDATA[15]	1
Q5_LANE2_DRI_RDATA[16]	1
Q5_LANE2_DRI_RDATA[17]	1
Q5_LANE2_DRI_RDATA[18]	1
Q5_LANE2_DRI_RDATA[19]	1
Q5_LANE2_DRI_RDATA[1]	1
Q5_LANE2_DRI_RDATA[20]	1
Q5_LANE2_DRI_RDATA[21]	1
Q5_LANE2_DRI_RDATA[22]	1
Q5_LANE2_DRI_RDATA[23]	1
Q5_LANE2_DRI_RDATA[24]	1
Q5_LANE2_DRI_RDATA[25]	1
Q5_LANE2_DRI_RDATA[26]	1
Q5_LANE2_DRI_RDATA[27]	1
Q5_LANE2_DRI_RDATA[28]	1
Q5_LANE2_DRI_RDATA[29]	1
Q5_LANE2_DRI_RDATA[2]	1
Q5_LANE2_DRI_RDATA[30]	1
Q5_LANE2_DRI_RDATA[31]	1
Q5_LANE2_DRI_RDATA[32]	1
Q5_LANE2_DRI_RDATA[3]	1
Q5_LANE2_DRI_RDATA[4]	1
Q5_LANE2_DRI_RDATA[5]	1
Q5_LANE2_DRI_RDATA[6]	1
Q5_LANE2_DRI_RDATA[7]	1
Q5_LANE2_DRI_RDATA[8]	1
Q5_LANE2_DRI_RDATA[9]	1
Q5_LANE3_DRI_INTERRUPT	1
Q5_LANE3_DRI_RDATA[0]	1
Q5_LANE3_DRI_RDATA[10]	1
Q5_LANE3_DRI_RDATA[11]	1
Q5_LANE3_DRI_RDATA[12]	1
Q5_LANE3_DRI_RDATA[13]	1
Q5_LANE3_DRI_RDATA[14]	1
Q5_LANE3_DRI_RDATA[15]	1
Q5_LANE3_DRI_RDATA[16]	1
Q5_LANE3_DRI_RDATA[17]	1
Q5_LANE3_DRI_RDATA[18]	1
Q5_LANE3_DRI_RDATA[19]	1
Q5_LANE3_DRI_RDATA[1]	1
Q5_LANE3_DRI_RDATA[20]	1
Q5_LANE3_DRI_RDATA[21]	1
Q5_LANE3_DRI_RDATA[22]	1
Q5_LANE3_DRI_RDATA[23]	1
Q5_LANE3_DRI_RDATA[24]	1
Q5_LANE3_DRI_RDATA[25]	1
Q5_LANE3_DRI_RDATA[26]	1
Q5_LANE3_DRI_RDATA[27]	1
Q5_LANE3_DRI_RDATA[28]	1
Q5_LANE3_DRI_RDATA[29]	1
Q5_LANE3_DRI_RDATA[2]	1
Q5_LANE3_DRI_RDATA[30]	1
Q5_LANE3_DRI_RDATA[31]	1
Q5_LANE3_DRI_RDATA[32]	1
Q5_LANE3_DRI_RDATA[3]	1
Q5_LANE3_DRI_RDATA[4]	1
Q5_LANE3_DRI_RDATA[5]	1
Q5_LANE3_DRI_RDATA[6]	1
Q5_LANE3_DRI_RDATA[7]	1
Q5_LANE3_DRI_RDATA[8]	1
Q5_LANE3_DRI_RDATA[9]	1
Q5_TXPLL_DRI_INTERRUPT	1
Q5_TXPLL_DRI_RDATA[0]	1
Q5_TXPLL_DRI_RDATA[10]	1
Q5_TXPLL_DRI_RDATA[11]	1
Q5_TXPLL_DRI_RDATA[12]	1
Q5_TXPLL_DRI_RDATA[13]	1
Q5_TXPLL_DRI_RDATA[14]	1
Q5_TXPLL_DRI_RDATA[15]	1
Q5_TXPLL_DRI_RDATA[16]	1
Q5_TXPLL_DRI_RDATA[17]	1
Q5_TXPLL_DRI_RDATA[18]	1
Q5_TXPLL_DRI_RDATA[19]	1
Q5_TXPLL_DRI_RDATA[1]	1
Q5_TXPLL_DRI_RDATA[20]	1
Q5_TXPLL_DRI_RDATA[21]	1
Q5_TXPLL_DRI_RDATA[22]	1
Q5_TXPLL_DRI_RDATA[23]	1
Q5_TXPLL_DRI_RDATA[24]	1
Q5_TXPLL_DRI_RDATA[25]	1
Q5_TXPLL_DRI_RDATA[26]	1
Q5_TXPLL_DRI_RDATA[27]	1
Q5_TXPLL_DRI_RDATA[28]	1
Q5_TXPLL_DRI_RDATA[29]	1
Q5_TXPLL_DRI_RDATA[2]	1
Q5_TXPLL_DRI_RDATA[30]	1
Q5_TXPLL_DRI_RDATA[31]	1
Q5_TXPLL_DRI_RDATA[32]	1
Q5_TXPLL_DRI_RDATA[3]	1
Q5_TXPLL_DRI_RDATA[4]	1
Q5_TXPLL_DRI_RDATA[5]	1
Q5_TXPLL_DRI_RDATA[6]	1
Q5_TXPLL_DRI_RDATA[7]	1
Q5_TXPLL_DRI_RDATA[8]	1
Q5_TXPLL_DRI_RDATA[9]	1
Q5_TXPLL_SSC_DRI_INTERRUPT	1
Q5_TXPLL_SSC_DRI_RDATA[0]	1
Q5_TXPLL_SSC_DRI_RDATA[10]	1
Q5_TXPLL_SSC_DRI_RDATA[11]	1
Q5_TXPLL_SSC_DRI_RDATA[12]	1
Q5_TXPLL_SSC_DRI_RDATA[13]	1
Q5_TXPLL_SSC_DRI_RDATA[14]	1
Q5_TXPLL_SSC_DRI_RDATA[15]	1
Q5_TXPLL_SSC_DRI_RDATA[16]	1
Q5_TXPLL_SSC_DRI_RDATA[17]	1
Q5_TXPLL_SSC_DRI_RDATA[18]	1
Q5_TXPLL_SSC_DRI_RDATA[19]	1
Q5_TXPLL_SSC_DRI_RDATA[1]	1
Q5_TXPLL_SSC_DRI_RDATA[20]	1
Q5_TXPLL_SSC_DRI_RDATA[21]	1
Q5_TXPLL_SSC_DRI_RDATA[22]	1
Q5_TXPLL_SSC_DRI_RDATA[23]	1
Q5_TXPLL_SSC_DRI_RDATA[24]	1
Q5_TXPLL_SSC_DRI_RDATA[25]	1
Q5_TXPLL_SSC_DRI_RDATA[26]	1
Q5_TXPLL_SSC_DRI_RDATA[27]	1
Q5_TXPLL_SSC_DRI_RDATA[28]	1
Q5_TXPLL_SSC_DRI_RDATA[29]	1
Q5_TXPLL_SSC_DRI_RDATA[2]	1
Q5_TXPLL_SSC_DRI_RDATA[30]	1
Q5_TXPLL_SSC_DRI_RDATA[31]	1
Q5_TXPLL_SSC_DRI_RDATA[32]	1
Q5_TXPLL_SSC_DRI_RDATA[3]	1
Q5_TXPLL_SSC_DRI_RDATA[4]	1
Q5_TXPLL_SSC_DRI_RDATA[5]	1
Q5_TXPLL_SSC_DRI_RDATA[6]	1
Q5_TXPLL_SSC_DRI_RDATA[7]	1
Q5_TXPLL_SSC_DRI_RDATA[8]	1
Q5_TXPLL_SSC_DRI_RDATA[9]	1

G5SOC_CONTROL_SPI (Unused pin tie-off)

Input Pin	Tie-Off
CLK_O	1
CLK_OE	0
DI	1
D_O	1
D_OE	0
FLASH	1
IFACE	1
SS_O	1
SS_OE	0

G5SOC_CONTROL_SYS_SERVICES (Unused pin tie-off)

Input Pin	Tie-Off
ABORT	0
CMD[0]	1
CMD[10]	1
CMD[11]	1
CMD[12]	1
CMD[13]	1
CMD[14]	1
CMD[15]	1
CMD[1]	1
CMD[2]	1
CMD[3]	1
CMD[4]	1
CMD[5]	1
CMD[6]	1
CMD[7]	1
CMD[8]	1
CMD[9]	1
MAILBOX_ADDR[0]	1
MAILBOX_ADDR[1]	1
MAILBOX_ADDR[2]	1
MAILBOX_ADDR[3]	1
MAILBOX_ADDR[4]	1
MAILBOX_ADDR[5]	1
MAILBOX_ADDR[6]	1
MAILBOX_ADDR[7]	1
MAILBOX_ADDR[8]	1
MAILBOX_CLK	0
MAILBOX_READ	0
MAILBOX_WDATA[0]	1
MAILBOX_WDATA[10]	1
MAILBOX_WDATA[11]	1
MAILBOX_WDATA[12]	1
MAILBOX_WDATA[13]	1
MAILBOX_WDATA[14]	1
MAILBOX_WDATA[15]	1
MAILBOX_WDATA[16]	1
MAILBOX_WDATA[17]	1
MAILBOX_WDATA[18]	1
MAILBOX_WDATA[19]	1
MAILBOX_WDATA[1]	1
MAILBOX_WDATA[20]	1
MAILBOX_WDATA[21]	1
MAILBOX_WDATA[22]	1
MAILBOX_WDATA[23]	1
MAILBOX_WDATA[24]	1
MAILBOX_WDATA[25]	1
MAILBOX_WDATA[26]	1
MAILBOX_WDATA[27]	1
MAILBOX_WDATA[28]	1
MAILBOX_WDATA[29]	1
MAILBOX_WDATA[2]	1
MAILBOX_WDATA[30]	1
MAILBOX_WDATA[31]	1
MAILBOX_WDATA[3]	1
MAILBOX_WDATA[4]	1
MAILBOX_WDATA[5]	1
MAILBOX_WDATA[6]	1
MAILBOX_WDATA[7]	1
MAILBOX_WDATA[8]	1
MAILBOX_WDATA[9]	1
MAILBOX_WRITE	0
REQ	0

G5SOC_CONTROL_TVS (Unused pin tie-off)

Input Pin	Tie-Off
EN[0]	1
EN[1]	1
EN[2]	1
EN[3]	1
TEMP_HIGH_CLEAR	1
TEMP_LOW_CLEAR	1

G5SOC_CONTROL_VOLTAGEDETECT (Unused pin tie-off)

Input Pin	Tie-Off
VOLT_DETECT_1P0_HIGH_CLEAR	1
VOLT_DETECT_1P0_LOW_CLEAR	1
VOLT_DETECT_1P8_HIGH_CLEAR	1
VOLT_DETECT_1P8_LOW_CLEAR	1
VOLT_DETECT_2P5_HIGH_CLEAR	1
VOLT_DETECT_2P5_LOW_CLEAR	1

TAMPER_G5C (Unused pin tie-off)

Input Pin	Tie-Off
CLEAR[0]	1
CLEAR[10]	1
CLEAR[11]	1
CLEAR[12]	1
CLEAR[13]	1
CLEAR[14]	1
CLEAR[15]	1
CLEAR[16]	1
CLEAR[17]	1
CLEAR[18]	1
CLEAR[19]	1
CLEAR[1]	1
CLEAR[20]	1
CLEAR[21]	1
CLEAR[22]	1
CLEAR[23]	1
CLEAR[24]	1
CLEAR[25]	1
CLEAR[26]	1
CLEAR[27]	1
CLEAR[28]	1
CLEAR[29]	1
CLEAR[2]	1
CLEAR[30]	1
CLEAR[31]	1
CLEAR[3]	1
CLEAR[4]	1
CLEAR[5]	1
CLEAR[6]	1
CLEAR[7]	1
CLEAR[8]	1
CLEAR[9]	1
IO_DISABLE	0
LOCKDOWN	0
RESET_DEVICE	0
ZEROIZE	0

UJTAG_G5C (Unused pin tie-off)

Input Pin	Tie-Off
EN_SEC	0
TCK	1
TDI	1
TDI_SEC	1
TMS	1
TRSTB	1
UTDO	1
UTRSTB_SEC	1

UPROM (Unused pin tie-off)

Input Pin	Tie-Off
ADDR[0]	1
ADDR[10]	1
ADDR[11]	1
ADDR[12]	1
ADDR[13]	1
ADDR[14]	1
ADDR[15]	1
ADDR[1]	1
ADDR[2]	1
ADDR[3]	1
ADDR[4]	1
ADDR[5]	1
ADDR[6]	1
ADDR[7]	1
ADDR[8]	1
ADDR[9]	1
BLK	0