Microchip Technology Inc. - Microchip Libero Software Release v2022.2 (Version 2022.2.0.10)

Date      :  Mon Nov 21 15:20:26 2022
Project   :  D:\Delme\SEV_PFSoC_OpenVX
Component :  CORERXIODBITALIGN_C2
Family    :  PolarFireSoC


HDL source files for all Synthesis and Simulation tools:
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/core/CoreRxIODBitAlign.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/core/CoreRxIODBitAlign_top.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2.v

Stimulus files for all Simulation tools:
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/prbscheck_parallel_fab_x4.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/prbsgen_parallel_fab_x4.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/rev_bits_x4.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/CCC_COMP_CCC_COMP_0_PF_CCC.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/CCC_COMP.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/CORERXIODBITALIGN_C0.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_PF_CLK_DIV_FIFO_PF_CLK_DIV_DELAY.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_PF_CLK_DIV_RXCLK_PF_CLK_DIV_DELAY.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_PF_IOD_CLK_TRAINING_PF_IOD.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_PF_IOD_RX_PF_IOD.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/PF_LANECTRL_PAUSE_SYNC.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_PF_LANECTRL_0_PF_LANECTRL.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/PLL_BclkSclkAlign.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/ICB_BclkSclkAlign.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/CoreBclkSclkAlign.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP_TR.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/RXIOD_COMP.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/PF_LANECTRL_PAUSE_SYNC1.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/TXIOD_COMP_LANECTRL_ADDR_CMD_0_PF_LANECTRL.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/TXIOD_COMP_PF_IOD_TX_CLK_PF_IOD.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/TXIOD_COMP_PF_IOD_TX_PF_IOD.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/TXIOD_COMP.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/CoreRxIODBitAlign_SD_wrap.v
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2/CORERXIODBITALIGN_C2_0/rtl/vlog/test/user/testbench.v

Constraint files:
    D:/Delme/SEV_PFSoC_OpenVX/component/work/CORERXIODBITALIGN_C2\CORERXIODBITALIGN_C2_0\CORERXIODBITALIGN_C2.sdc
