#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020
#install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
#OS: Windows 8 6.2
#Hostname: HYD-LT-I52881
# Mon Jan 11 21:10:00 2021
#Implementation: synthesis
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2
Hostname: HYD-LT-I52881
Implementation : synthesis
Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @
@N: : | Running in 64-bit mode
###########################################################[
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2
Hostname: HYD-LT-I52881
Implementation : synthesis
Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @
@N: : | Running in 64-bit mode
@N:CG1349 : | Running Verilog Compiler in System Verilog mode
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v" (library work)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\polarfire_syn_comps.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreAPB3_0\CoreAPB3_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Clock_gen.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Rx_async.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\fifo_256x8_g5.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\rtl\vlog\core_encrypted\CortexM1DbgIntegration_PF.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\ccortexm1_ujtag_wrapper.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\ccortexm1_uj_jtag.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\CORECORTEXM1.v" (library work)
@N:CG334 : CORECORTEXM1.v(737) | Read directive translate_off.
@N:CG333 : CORECORTEXM1.v(784) | Read directive translate_on.
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoretxM1_0\CoretxM1_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_CCC_0\PF_CCC_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\PF_TPSRAM_AHB_AXI_0\PF_SRAM_PF_TPSRAM_AHB_AXI_0_PF_TPSRAM.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram_ECC.v" (library work)
@N:CG334 : CoreAHBLSRAM_AHBLSram_ECC.v(610) | Read directive translate_off.
@N:CG333 : CoreAHBLSRAM_AHBLSram_ECC.v(613) | Read directive translate_on.
@N:CG334 : CoreAHBLSRAM_AHBLSram_ECC.v(616) | Read directive translate_off.
@N:CG333 : CoreAHBLSRAM_AHBLSram_ECC.v(625) | Read directive translate_on.
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v" (library work)
@N:CG334 : CoreAHBLSRAM_AHBLSram.v(472) | Read directive translate_off.
@N:CG333 : CoreAHBLSRAM_AHBLSram.v(475) | Read directive translate_on.
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_PF.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\PF_SRAM.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_ahbtoapbsm.v" (library COREAHBTOAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_apbaddrdata.v" (library COREAHBTOAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_penablescheduler.v" (library COREAHBTOAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3.v" (library COREAHBTOAPB3_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\core_ahb_to_apb3\core_ahb_to_apb3.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavearbiter.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_defaultslavesm.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_addrdec.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v" (library COREAHBLITE_LIB)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\pf_reset\pf_reset_0\core\corereset_pf.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\pf_reset\pf_reset.v" (library work)
@I::"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\top\top.v" (library work)
Verilog syntax check successful!
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\polarfire_syn_comps.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_ahbtoapbsm.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_apbaddrdata.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3_penablescheduler.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.1.100\rtl\vlog\core\coreahbtoapb3.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\core_ahb_to_apb3\core_ahb_to_apb3.v changed - recompiling
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\top\top.v changed - recompiling
Selecting top level module top
@N:CG775 : coreahbtoapb3.v(25) | Component COREAHBTOAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAHBTOAPB3_LIB
@N:CG364 : coreahbtoapb3_ahbtoapbsm.v(26) | Synthesizing module CoreAHBtoAPB3_AhbToApbSM in library COREAHBTOAPB3_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
RSP_OKAY=2'b00
RSP_ERROR=2'b01
IDLE=3'b000
WRITE0=3'b001
WRITE1=3'b010
READ0=3'b011
WAIT=3'b100
Generated name = CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4
Running optimization stage 1 on CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4 .......
@N:CG364 : coreahbtoapb3_penablescheduler.v(26) | Synthesizing module CoreAHBtoAPB3_PenableScheduler in library COREAHBTOAPB3_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
IDLE=2'b00
WAIT=2'b01
WAITCLR=2'b10
Generated name = CoreAHBtoAPB3_PenableScheduler_0s_0_1_2
Running optimization stage 1 on CoreAHBtoAPB3_PenableScheduler_0s_0_1_2 .......
@N:CG364 : coreahbtoapb3_apbaddrdata.v(27) | Synthesizing module CoreAHBtoAPB3_ApbAddrData in library COREAHBTOAPB3_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreAHBtoAPB3_ApbAddrData_0s
Running optimization stage 1 on CoreAHBtoAPB3_ApbAddrData_0s .......
@N:CG364 : coreahbtoapb3.v(25) | Synthesizing module COREAHBTOAPB3 in library COREAHBTOAPB3_LIB.
FAMILY=32'b00000000000000000000000000010001
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = COREAHBTOAPB3_17s_0s
Running optimization stage 1 on COREAHBTOAPB3_17s_0s .......
@N:CG364 : core_ahb_to_apb3.v(21) | Synthesizing module core_ahb_to_apb3 in library work.
Running optimization stage 1 on core_ahb_to_apb3 .......
@N:CG775 : coreahblite.v(23) | Component coreahblite_0_coreahblite_0_0_CoreAHBLite not found in library "work" or "__hyper__lib__", but found in library COREAHBLITE_LIB
@W:CG1283 : coreahblite.v(568) | Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite.v(568) | Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite.v(568) | Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite.v(568) | Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite_matrix4x16.v(2813) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite_masterstage.v(217) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC=16'b0000000000000000
M_AHBSLOTENABLE=17'b00000000000010001
MSB_ADDR=32'b00000000000000000000000000010011
SLAVE_0=16'b0000000000000001
SLAVE_1=16'b0000000000000010
SLAVE_2=16'b0000000000000100
SLAVE_3=16'b0000000000001000
SLAVE_4=16'b0000000000010000
SLAVE_5=16'b0000000000100000
SLAVE_6=16'b0000000001000000
SLAVE_7=16'b0000000010000000
SLAVE_8=16'b0000000100000000
SLAVE_9=16'b0000001000000000
SLAVE_10=16'b0000010000000000
SLAVE_11=16'b0000100000000000
SLAVE_12=16'b0001000000000000
SLAVE_13=16'b0010000000000000
SLAVE_14=16'b0100000000000000
SLAVE_15=16'b1000000000000000
NONE=16'b0000000000000000
Generated name = COREAHBLITE_ADDRDEC_Z1
Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z1 .......
@N:CG364 : coreahblite_defaultslavesm.v(20) | Synthesizing module COREAHBLITE_DEFAULTSLAVESM in library COREAHBLITE_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
IDLE=1'b0
HRESPEXTEND=1'b1
Generated name = COREAHBLITE_DEFAULTSLAVESM_0s_0_1
Running optimization stage 1 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 .......
@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC=16'b0000000000000000
M_AHBSLOTENABLE=17'b00000000000010001
SYNC_RESET=32'b00000000000000000000000000000000
IDLE=1'b0
REGISTERED=1'b1
SLAVE_NONE=17'b00000000000000000
Generated name = COREAHBLITE_MASTERSTAGE_4_1_0_17_0s_0_1_0
Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_4_1_0_17_0s_0_1_0 .......
@W:CL177 : coreahblite_masterstage.v(633) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W:CG1283 : coreahblite_matrix4x16.v(2879) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite_masterstage.v(217) | Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@N:CG364 : coreahblite_addrdec.v(20) | Synthesizing module COREAHBLITE_ADDRDEC in library COREAHBLITE_LIB.
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC=16'b0000000000000000
M_AHBSLOTENABLE=17'b00000000000000000
MSB_ADDR=32'b00000000000000000000000000010011
SLAVE_0=16'b0000000000000001
SLAVE_1=16'b0000000000000010
SLAVE_2=16'b0000000000000100
SLAVE_3=16'b0000000000001000
SLAVE_4=16'b0000000000010000
SLAVE_5=16'b0000000000100000
SLAVE_6=16'b0000000001000000
SLAVE_7=16'b0000000010000000
SLAVE_8=16'b0000000100000000
SLAVE_9=16'b0000001000000000
SLAVE_10=16'b0000010000000000
SLAVE_11=16'b0000100000000000
SLAVE_12=16'b0001000000000000
SLAVE_13=16'b0010000000000000
SLAVE_14=16'b0100000000000000
SLAVE_15=16'b1000000000000000
NONE=16'b0000000000000000
Generated name = COREAHBLITE_ADDRDEC_Z2
Running optimization stage 1 on COREAHBLITE_ADDRDEC_Z2 .......
@N:CG364 : coreahblite_masterstage.v(22) | Synthesizing module COREAHBLITE_MASTERSTAGE in library COREAHBLITE_LIB.
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC=16'b0000000000000000
M_AHBSLOTENABLE=17'b00000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
IDLE=1'b0
REGISTERED=1'b1
SLAVE_NONE=17'b00000000000000000
Generated name = COREAHBLITE_MASTERSTAGE_4_1_0_0_0s_0_1_0
Running optimization stage 1 on COREAHBLITE_MASTERSTAGE_4_1_0_0_0s_0_1_0 .......
@W:CL177 : coreahblite_masterstage.v(633) | Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W:CG1283 : coreahblite_matrix4x16.v(2945) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : coreahblite_matrix4x16.v(3011) | Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@N:CG364 : coreahblite_slavearbiter.v(20) | Synthesizing module COREAHBLITE_SLAVEARBITER in library COREAHBLITE_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
M0EXTEND=4'b0000
M0DONE=4'b0001
M0LOCK=4'b0010
M0LOCKEXTEND=4'b0011
M1EXTEND=4'b0100
M1DONE=4'b0101
M1LOCK=4'b0110
M1LOCKEXTEND=4'b0111
M2EXTEND=4'b1000
M2DONE=4'b1001
M2LOCK=4'b1010
M2LOCKEXTEND=4'b1011
M3EXTEND=4'b1100
M3DONE=4'b1101
M3LOCK=4'b1110
M3LOCKEXTEND=4'b1111
MASTER_0=4'b0001
MASTER_1=4'b0010
MASTER_2=4'b0100
MASTER_3=4'b1000
MASTER_NONE=4'b0000
Generated name = COREAHBLITE_SLAVEARBITER_Z3
Running optimization stage 1 on COREAHBLITE_SLAVEARBITER_Z3 .......
@N:CG364 : coreahblite_slavestage.v(22) | Synthesizing module COREAHBLITE_SLAVESTAGE in library COREAHBLITE_LIB.
SYNC_RESET=32'b00000000000000000000000000000000
TRN_IDLE=1'b0
MASTER_NONE=4'b0000
Generated name = COREAHBLITE_SLAVESTAGE_0s_0_0
Running optimization stage 1 on COREAHBLITE_SLAVESTAGE_0s_0_0 .......
@N:CG364 : coreahblite_matrix4x16.v(23) | Synthesizing module COREAHBLITE_MATRIX4X16 in library COREAHBLITE_LIB.
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC=16'b0000000000000000
M0_AHBSLOTENABLE=17'b00000000000010001
M1_AHBSLOTENABLE=17'b00000000000000000
M2_AHBSLOTENABLE=17'b00000000000000000
M3_AHBSLOTENABLE=17'b00000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s
Running optimization stage 1 on COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s .......
@N:CG364 : coreahblite.v(23) | Synthesizing module coreahblite_0_coreahblite_0_0_CoreAHBLite in library COREAHBLITE_LIB.
FAMILY=6'b011010
MEMSPACE=3'b100
HADDR_SHG_CFG=1'b1
SC_0=1'b0
SC_1=1'b0
SC_2=1'b0
SC_3=1'b0
SC_4=1'b0
SC_5=1'b0
SC_6=1'b0
SC_7=1'b0
SC_8=1'b0
SC_9=1'b0
SC_10=1'b0
SC_11=1'b0
SC_12=1'b0
SC_13=1'b0
SC_14=1'b0
SC_15=1'b0
M0_AHBSLOT0ENABLE=1'b1
M0_AHBSLOT1ENABLE=1'b0
M0_AHBSLOT2ENABLE=1'b0
M0_AHBSLOT3ENABLE=1'b0
M0_AHBSLOT4ENABLE=1'b1
M0_AHBSLOT5ENABLE=1'b0
M0_AHBSLOT6ENABLE=1'b0
M0_AHBSLOT7ENABLE=1'b0
M0_AHBSLOT8ENABLE=1'b0
M0_AHBSLOT9ENABLE=1'b0
M0_AHBSLOT10ENABLE=1'b0
M0_AHBSLOT11ENABLE=1'b0
M0_AHBSLOT12ENABLE=1'b0
M0_AHBSLOT13ENABLE=1'b0
M0_AHBSLOT14ENABLE=1'b0
M0_AHBSLOT15ENABLE=1'b0
M0_AHBSLOT16ENABLE=1'b0
M1_AHBSLOT0ENABLE=1'b0
M1_AHBSLOT1ENABLE=1'b0
M1_AHBSLOT2ENABLE=1'b0
M1_AHBSLOT3ENABLE=1'b0
M1_AHBSLOT4ENABLE=1'b0
M1_AHBSLOT5ENABLE=1'b0
M1_AHBSLOT6ENABLE=1'b0
M1_AHBSLOT7ENABLE=1'b0
M1_AHBSLOT8ENABLE=1'b0
M1_AHBSLOT9ENABLE=1'b0
M1_AHBSLOT10ENABLE=1'b0
M1_AHBSLOT11ENABLE=1'b0
M1_AHBSLOT12ENABLE=1'b0
M1_AHBSLOT13ENABLE=1'b0
M1_AHBSLOT14ENABLE=1'b0
M1_AHBSLOT15ENABLE=1'b0
M1_AHBSLOT16ENABLE=1'b0
M2_AHBSLOT0ENABLE=1'b0
M2_AHBSLOT1ENABLE=1'b0
M2_AHBSLOT2ENABLE=1'b0
M2_AHBSLOT3ENABLE=1'b0
M2_AHBSLOT4ENABLE=1'b0
M2_AHBSLOT5ENABLE=1'b0
M2_AHBSLOT6ENABLE=1'b0
M2_AHBSLOT7ENABLE=1'b0
M2_AHBSLOT8ENABLE=1'b0
M2_AHBSLOT9ENABLE=1'b0
M2_AHBSLOT10ENABLE=1'b0
M2_AHBSLOT11ENABLE=1'b0
M2_AHBSLOT12ENABLE=1'b0
M2_AHBSLOT13ENABLE=1'b0
M2_AHBSLOT14ENABLE=1'b0
M2_AHBSLOT15ENABLE=1'b0
M2_AHBSLOT16ENABLE=1'b0
M3_AHBSLOT0ENABLE=1'b0
M3_AHBSLOT1ENABLE=1'b0
M3_AHBSLOT2ENABLE=1'b0
M3_AHBSLOT3ENABLE=1'b0
M3_AHBSLOT4ENABLE=1'b0
M3_AHBSLOT5ENABLE=1'b0
M3_AHBSLOT6ENABLE=1'b0
M3_AHBSLOT7ENABLE=1'b0
M3_AHBSLOT8ENABLE=1'b0
M3_AHBSLOT9ENABLE=1'b0
M3_AHBSLOT10ENABLE=1'b0
M3_AHBSLOT11ENABLE=1'b0
M3_AHBSLOT12ENABLE=1'b0
M3_AHBSLOT13ENABLE=1'b0
M3_AHBSLOT14ENABLE=1'b0
M3_AHBSLOT15ENABLE=1'b0
M3_AHBSLOT16ENABLE=1'b0
MASTER0_INTERFACE=1'b1
MASTER1_INTERFACE=1'b1
MASTER2_INTERFACE=1'b1
MASTER3_INTERFACE=1'b1
SLAVE0_INTERFACE=1'b1
SLAVE1_INTERFACE=1'b1
SLAVE2_INTERFACE=1'b1
SLAVE3_INTERFACE=1'b1
SLAVE4_INTERFACE=1'b1
SLAVE5_INTERFACE=1'b1
SLAVE6_INTERFACE=1'b1
SLAVE7_INTERFACE=1'b1
SLAVE8_INTERFACE=1'b1
SLAVE9_INTERFACE=1'b1
SLAVE10_INTERFACE=1'b1
SLAVE11_INTERFACE=1'b1
SLAVE12_INTERFACE=1'b1
SLAVE13_INTERFACE=1'b1
SLAVE14_INTERFACE=1'b1
SLAVE15_INTERFACE=1'b1
SLAVE16_INTERFACE=1'b1
SYNC_RESET=32'b00000000000000000000000000000000
M0_AHBSLOTENABLE=17'b00000000000010001
M1_AHBSLOTENABLE=17'b00000000000000000
M2_AHBSLOTENABLE=17'b00000000000000000
M3_AHBSLOTENABLE=17'b00000000000000000
SC=16'b0000000000000000
Generated name = coreahblite_0_coreahblite_0_0_CoreAHBLite_Z4
Running optimization stage 1 on coreahblite_0_coreahblite_0_0_CoreAHBLite_Z4 .......
@N:CG364 : coreahblite_0.v(128) | Synthesizing module coreahblite_0 in library work.
Running optimization stage 1 on coreahblite_0 .......
@N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB
@N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB.
Running optimization stage 1 on COREAPB3_MUXPTOB3 .......
@N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB.
APB_DWIDTH=6'b100000
IADDR_OPTION=32'b00000000000000000000000000000000
APBSLOT0ENABLE=1'b1
APBSLOT1ENABLE=1'b1
APBSLOT2ENABLE=1'b0
APBSLOT3ENABLE=1'b0
APBSLOT4ENABLE=1'b0
APBSLOT5ENABLE=1'b0
APBSLOT6ENABLE=1'b0
APBSLOT7ENABLE=1'b0
APBSLOT8ENABLE=1'b0
APBSLOT9ENABLE=1'b0
APBSLOT10ENABLE=1'b0
APBSLOT11ENABLE=1'b0
APBSLOT12ENABLE=1'b0
APBSLOT13ENABLE=1'b0
APBSLOT14ENABLE=1'b0
APBSLOT15ENABLE=1'b0
SC_0=1'b0
SC_1=1'b0
SC_2=1'b0
SC_3=1'b0
SC_4=1'b0
SC_5=1'b0
SC_6=1'b0
SC_7=1'b0
SC_8=1'b0
SC_9=1'b0
SC_10=1'b0
SC_11=1'b0
SC_12=1'b0
SC_13=1'b0
SC_14=1'b0
SC_15=1'b0
MADDR_BITS=6'b010000
UPR_NIBBLE_POSN=4'b0110
FAMILY=32'b00000000000000000000000000011010
SYNC_RESET=32'b00000000000000000000000000000000
IADDR_NOTINUSE=32'b00000000000000000000000000000000
IADDR_EXTERNAL=32'b00000000000000000000000000000001
IADDR_SLOT0=32'b00000000000000000000000000000010
IADDR_SLOT1=32'b00000000000000000000000000000011
IADDR_SLOT2=32'b00000000000000000000000000000100
IADDR_SLOT3=32'b00000000000000000000000000000101
IADDR_SLOT4=32'b00000000000000000000000000000110
IADDR_SLOT5=32'b00000000000000000000000000000111
IADDR_SLOT6=32'b00000000000000000000000000001000
IADDR_SLOT7=32'b00000000000000000000000000001001
IADDR_SLOT8=32'b00000000000000000000000000001010
IADDR_SLOT9=32'b00000000000000000000000000001011
IADDR_SLOT10=32'b00000000000000000000000000001100
IADDR_SLOT11=32'b00000000000000000000000000001101
IADDR_SLOT12=32'b00000000000000000000000000001110
IADDR_SLOT13=32'b00000000000000000000000000001111
IADDR_SLOT14=32'b00000000000000000000000000010000
IADDR_SLOT15=32'b00000000000000000000000000010001
SL0=16'b0000000000000001
SL1=16'b0000000000000010
SL2=16'b0000000000000000
SL3=16'b0000000000000000
SL4=16'b0000000000000000
SL5=16'b0000000000000000
SL6=16'b0000000000000000
SL7=16'b0000000000000000
SL8=16'b0000000000000000
SL9=16'b0000000000000000
SL10=16'b0000000000000000
SL11=16'b0000000000000000
SL12=16'b0000000000000000
SL13=16'b0000000000000000
SL14=16'b0000000000000000
SL15=16'b0000000000000000
SC=16'b0000000000000000
SC_qual=16'b0000000000000000
Generated name = CoreAPB3_Z5
@W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it.
Running optimization stage 1 on CoreAPB3_Z5 .......
@N:CG364 : CoreAPB3_0.v(57) | Synthesizing module CoreAPB3_0 in library work.
Running optimization stage 1 on CoreAPB3_0 .......
@N:CG364 : coregpio.v(23) | Synthesizing module CoreGPIO_0_CoreGPIO_0_0_CoreGPIO in library work.
IO_NUM=32'b00000000000000000000000000000100
APB_WIDTH=32'b00000000000000000000000000100000
OE_TYPE=1'b1
INT_BUS=1'b0
FIXED_CONFIG_0=1'b1
FIXED_CONFIG_1=1'b1
FIXED_CONFIG_2=1'b1
FIXED_CONFIG_3=1'b1
FIXED_CONFIG_4=1'b0
FIXED_CONFIG_5=1'b0
FIXED_CONFIG_6=1'b0
FIXED_CONFIG_7=1'b0
FIXED_CONFIG_8=1'b0
FIXED_CONFIG_9=1'b0
FIXED_CONFIG_10=1'b0
FIXED_CONFIG_11=1'b0
FIXED_CONFIG_12=1'b0
FIXED_CONFIG_13=1'b0
FIXED_CONFIG_14=1'b0
FIXED_CONFIG_15=1'b0
FIXED_CONFIG_16=1'b0
FIXED_CONFIG_17=1'b0
FIXED_CONFIG_18=1'b0
FIXED_CONFIG_19=1'b0
FIXED_CONFIG_20=1'b0
FIXED_CONFIG_21=1'b0
FIXED_CONFIG_22=1'b0
FIXED_CONFIG_23=1'b0
FIXED_CONFIG_24=1'b0
FIXED_CONFIG_25=1'b0
FIXED_CONFIG_26=1'b0
FIXED_CONFIG_27=1'b0
FIXED_CONFIG_28=1'b0
FIXED_CONFIG_29=1'b0
FIXED_CONFIG_30=1'b0
FIXED_CONFIG_31=1'b0
IO_TYPE_0=2'b01
IO_TYPE_1=2'b01
IO_TYPE_2=2'b01
IO_TYPE_3=2'b01
IO_TYPE_4=2'b00
IO_TYPE_5=2'b00
IO_TYPE_6=2'b00
IO_TYPE_7=2'b00
IO_TYPE_8=2'b00
IO_TYPE_9=2'b00
IO_TYPE_10=2'b00
IO_TYPE_11=2'b00
IO_TYPE_12=2'b00
IO_TYPE_13=2'b00
IO_TYPE_14=2'b00
IO_TYPE_15=2'b00
IO_TYPE_16=2'b00
IO_TYPE_17=2'b00
IO_TYPE_18=2'b00
IO_TYPE_19=2'b00
IO_TYPE_20=2'b00
IO_TYPE_21=2'b00
IO_TYPE_22=2'b00
IO_TYPE_23=2'b00
IO_TYPE_24=2'b00
IO_TYPE_25=2'b00
IO_TYPE_26=2'b00
IO_TYPE_27=2'b00
IO_TYPE_28=2'b00
IO_TYPE_29=2'b00
IO_TYPE_30=2'b00
IO_TYPE_31=2'b00
IO_INT_TYPE_0=3'b111
IO_INT_TYPE_1=3'b111
IO_INT_TYPE_2=3'b111
IO_INT_TYPE_3=3'b111
IO_INT_TYPE_4=3'b111
IO_INT_TYPE_5=3'b111
IO_INT_TYPE_6=3'b111
IO_INT_TYPE_7=3'b111
IO_INT_TYPE_8=3'b111
IO_INT_TYPE_9=3'b111
IO_INT_TYPE_10=3'b111
IO_INT_TYPE_11=3'b111
IO_INT_TYPE_12=3'b111
IO_INT_TYPE_13=3'b111
IO_INT_TYPE_14=3'b111
IO_INT_TYPE_15=3'b111
IO_INT_TYPE_16=3'b111
IO_INT_TYPE_17=3'b111
IO_INT_TYPE_18=3'b111
IO_INT_TYPE_19=3'b111
IO_INT_TYPE_20=3'b111
IO_INT_TYPE_21=3'b111
IO_INT_TYPE_22=3'b111
IO_INT_TYPE_23=3'b111
IO_INT_TYPE_24=3'b111
IO_INT_TYPE_25=3'b111
IO_INT_TYPE_26=3'b111
IO_INT_TYPE_27=3'b111
IO_INT_TYPE_28=3'b111
IO_INT_TYPE_29=3'b111
IO_INT_TYPE_30=3'b111
IO_INT_TYPE_31=3'b111
IO_VAL_0=1'b0
IO_VAL_1=1'b0
IO_VAL_2=1'b0
IO_VAL_3=1'b0
IO_VAL_4=1'b0
IO_VAL_5=1'b0
IO_VAL_6=1'b0
IO_VAL_7=1'b0
IO_VAL_8=1'b0
IO_VAL_9=1'b0
IO_VAL_10=1'b0
IO_VAL_11=1'b0
IO_VAL_12=1'b0
IO_VAL_13=1'b0
IO_VAL_14=1'b0
IO_VAL_15=1'b0
IO_VAL_16=1'b0
IO_VAL_17=1'b0
IO_VAL_18=1'b0
IO_VAL_19=1'b0
IO_VAL_20=1'b0
IO_VAL_21=1'b0
IO_VAL_22=1'b0
IO_VAL_23=1'b0
IO_VAL_24=1'b0
IO_VAL_25=1'b0
IO_VAL_26=1'b0
IO_VAL_27=1'b0
IO_VAL_28=1'b0
IO_VAL_29=1'b0
IO_VAL_30=1'b0
IO_VAL_31=1'b0
FIXED_CONFIG=32'b11110000000000000000000000000000
IO_INT_TYPE=96'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111
IO_TYPE=64'b0101010100000000000000000000000000000000000000000000000000000000
IO_VAL=32'b00000000000000000000000000000000
Generated name = CoreGPIO_0_CoreGPIO_0_0_CoreGPIO_Z6
@N:CG179 : coregpio.v(512) | Removing redundant assignment.
@N:CG179 : coregpio.v(515) | Removing redundant assignment.
Running optimization stage 1 on CoreGPIO_0_CoreGPIO_0_0_CoreGPIO_Z6 .......
@W:CL169 : coregpio.v(464) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_both[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(444) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_neg[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(424) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_pos[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(317) | Pruning unused register xhdl1.GEN_BITS[3].gpin3[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[3].gpin1[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[3].gpin2[3]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(464) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_both[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(444) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_neg[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(424) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_pos[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(317) | Pruning unused register xhdl1.GEN_BITS[2].gpin3[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[2].gpin1[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[2].gpin2[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(464) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_both[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(444) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_neg[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(424) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_pos[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(317) | Pruning unused register xhdl1.GEN_BITS[1].gpin3[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[1].gpin1[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[1].gpin2[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(464) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_both[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(444) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_neg[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(424) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_pos[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(317) | Pruning unused register xhdl1.GEN_BITS[0].gpin3[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[0].gpin1[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(304) | Pruning unused register xhdl1.GEN_BITS[0].gpin2[0]. Make sure that there are no unused intermediate registers.
@W:CL190 : coregpio.v(484) | Optimizing register bit xhdl1.GEN_BITS[0].APB_32.INTR_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : coregpio.v(484) | Optimizing register bit xhdl1.GEN_BITS[1].APB_32.INTR_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : coregpio.v(484) | Optimizing register bit xhdl1.GEN_BITS[2].APB_32.INTR_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL190 : coregpio.v(484) | Optimizing register bit xhdl1.GEN_BITS[3].APB_32.INTR_reg[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : coregpio.v(484) | Pruning unused register xhdl1.GEN_BITS[0].APB_32.INTR_reg[0]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(484) | Pruning unused register xhdl1.GEN_BITS[1].APB_32.INTR_reg[1]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(484) | Pruning unused register xhdl1.GEN_BITS[2].APB_32.INTR_reg[2]. Make sure that there are no unused intermediate registers.
@W:CL169 : coregpio.v(484) | Pruning unused register xhdl1.GEN_BITS[3].APB_32.INTR_reg[3]. Make sure that there are no unused intermediate registers.
@N:CG364 : CoreGPIO_0.v(153) | Synthesizing module CoreGPIO_0 in library work.
Running optimization stage 1 on CoreGPIO_0 .......
@N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work.
Running optimization stage 1 on CLKINT .......
@N:CG364 : CORECORTEXM1.v(14) | Synthesizing module CORECORTEXM1 in library work.
FAMILY=32'b00000000000000000000000000011010
NUM_IRQ_TOP=32'b00000000000000000000000000100000
USE_BFM=32'b00000000000000000000000000000000
ENABLE_ECC=32'b00000000000000000000000000000000
DEBUG_INCL=32'b00000000000000000000000000000001
DEBUG_IF=32'b00000000000000000000000000000000
INCL_RESET_CTRL=32'b00000000000000000000000000000001
DEBUG_CONFIG=32'b00000000000000000000000000000010
DEBUG_RESET=32'b00000000000000000000000000000000
UJ_RST_ON_GLOBAL=32'b00000000000000000000000000000001
UJ_CLK_ON_GLOBAL=32'b00000000000000000000000000000001
ITCM_SZ=32'b00000000000000000000000000100000
DTCM_SZ=32'b00000000000000000000000000100000
NUM_IRQ=32'b00000000000000000000000000100000
OS=32'b00000000000000000000000000000001
SMALL_MUL=32'b00000000000000000000000000000000
BE8=32'b00000000000000000000000000000000
ITCM_SIZE=4'b0110
DTCM_SIZE=4'b0110
ITCM_LA_EN=32'b00000000000000000000000000000000
ITCM_UA_EN=32'b00000000000000000000000000000001
SMALL_DEBUG=1'b0
JTAG=1'b1
SW=1'b0
uj_jtag_ircode=8'b00110011
Generated name = CORECORTEXM1_Z7
@N:CG364 : acg5.v(1442) | Synthesizing module UJTAG in library work.
Running optimization stage 1 on UJTAG .......
@N:CG364 : ccortexm1_ujtag_wrapper.v(39) | Synthesizing module ccortexm1_UJTAG_WRAPPER in library work.
Running optimization stage 1 on ccortexm1_UJTAG_WRAPPER .......
@N:CG364 : ccortexm1_uj_jtag.v(6) | Synthesizing module ccortexm1_uj_jtag in library work.
uj_jtag_ircode=8'b00110011
Generated name = ccortexm1_uj_jtag_51
Running optimization stage 1 on ccortexm1_uj_jtag_51 .......
Running optimization stage 1 on CFG1 .......
Running optimization stage 1 on SLE .......
Running optimization stage 1 on ARI1 .......
Running optimization stage 1 on CFG4 .......
Running optimization stage 1 on CFG3 .......
Running optimization stage 1 on CFG2 .......
Running optimization stage 1 on GND .......
Running optimization stage 1 on VCC .......
Running optimization stage 1 on CCORTEXM1lOII_1s_32s_1s_0s .......
Running optimization stage 1 on CCORTEXM1IIII_1s_1s .......
Running optimization stage 1 on CCORTEXM1lOIl_32s .......
Running optimization stage 1 on CCORTEXM1OlIl_32s .......
Running optimization stage 1 on CCORTEXM1lOIl_4s .......
Running optimization stage 1 on CCORTEXM1OlII_32s .......
Running optimization stage 1 on CCORTEXM1llII_1s .......
Running optimization stage 1 on CCORTEXM1O1l_1s_32s_1s_0s .......
Running optimization stage 1 on CCORTEXM1lOl1lI .......
Running optimization stage 1 on CCORTEXM1OIlO0I .......
Running optimization stage 1 on CCORTEXM1I1OI0I .......
Running optimization stage 1 on CCORTEXM1IlOOlI .......
Running optimization stage 1 on CCORTEXM1O11OlI .......
Running optimization stage 1 on CCORTEXM1llIOlI_0s .......
Running optimization stage 1 on CCORTEXM1I0lllI_0s .......
Running optimization stage 1 on CCORTEXM1l000lI .......
Running optimization stage 1 on CCORTEXM1I100lI .......
Running optimization stage 1 on CCORTEXM1Oll0lI_0s .......
Running optimization stage 1 on CCORTEXM1OlOlI .......
Running optimization stage 1 on CCORTEXM1l1O1l_1s_0s .......
Running optimization stage 1 on CCORTEXM1IOI1l .......
Running optimization stage 1 on CCORTEXM1llI1l_1s_1s_32s .......
Running optimization stage 1 on CCORTEXM1llOlI_1s_1s_0s_32s .......
Running optimization stage 1 on RAM64x12 .......
Running optimization stage 1 on CCORTEXM1OOOI1 .......
Running optimization stage 1 on CCORTEXM1ll1I0I .......
Running optimization stage 1 on CCORTEXM1lOOI1 .......
Running optimization stage 1 on CCORTEXM1OlIl1 .......
Running optimization stage 1 on MACC_PA .......
Running optimization stage 1 on CCORTEXM1IOIl1_0s .......
Running optimization stage 1 on CCORTEXM1IIOI1_0s .......
Running optimization stage 1 on CCORTEXM1l101I .......
Running optimization stage 1 on CCORTEXM1IlOI1_32s_0 .......
Only the first 100 messages of id 'CG360' are reported. To see all messages use 'report_messages -log C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\synlog\top_compiler.srr -id CG360' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG360} -count unlimited' in the Tcl shell.
Running optimization stage 1 on CCORTEXM1I0OlI_0s_0s .......
Running optimization stage 1 on CCORTEXM1IIIOI_1s_1s_0s_0s_32s .......
Running optimization stage 1 on CCORTEXM1I0IlI_0s .......
Running optimization stage 1 on CCORTEXM1I0I11 .......
Running optimization stage 1 on CCORTEXM1O1I11 .......
Running optimization stage 1 on CCORTEXM1lIl11_4 .......
Running optimization stage 1 on CCORTEXM1lIl11 .......
Running optimization stage 1 on CCORTEXM1lIl11_0 .......
Running optimization stage 1 on CCORTEXM1lIl11_2 .......
Running optimization stage 1 on CCORTEXM1l1I11 .......
Running optimization stage 1 on CCORTEXM1lIl11_1 .......
Running optimization stage 1 on CCORTEXM1lIl11_3 .......
Running optimization stage 1 on CCORTEXM1lIl11_6 .......
Running optimization stage 1 on CCORTEXM1lIl11_7 .......
Running optimization stage 1 on CCORTEXM1IOl11 .......
Running optimization stage 1 on CCORTEXM1I0001 .......
Running optimization stage 1 on CCORTEXM1lllI0I_32s_1s_0s_0s_0s .......
Running optimization stage 1 on RAM1K20 .......
Running optimization stage 1 on CCORTEXM1IO1I0I_8_ITCM_image_1s_15_0_32s_0_131071_400000s_Z1 .......
Running optimization stage 1 on CCORTEXM1lO1I0I_8_DTCM_image_1s_15_0_32s_536870912_537001983_400000s_Z2 .......
Running optimization stage 1 on CCORTEXM1O0l0OI .......
Running optimization stage 1 on CCORTEXM1OOIlOI .......
Running optimization stage 1 on CCORTEXM1I1IOII .......
Running optimization stage 1 on CCORTEXM1IlOlOI .......
Running optimization stage 1 on CCORTEXM1IlOlOI_0 .......
Running optimization stage 1 on CCORTEXM1lOOlOI .......
Running optimization stage 1 on CCORTEXM1Il1lOI .......
Running optimization stage 1 on CCORTEXM1Il1lOI_0 .......
Running optimization stage 1 on CCORTEXM1Il1lOI_1 .......
Running optimization stage 1 on CCORTEXM1l1IOII .......
Running optimization stage 1 on CCORTEXM1II1lOI_1s_0s .......
Running optimization stage 1 on CCORTEXM1O11IOI .......
Running optimization stage 1 on CortexM1DbgIntegration .......
Running optimization stage 1 on CORECORTEXM1_Z7 .......
@N:CG364 : CoretxM1_0.v(27) | Synthesizing module CoretxM1_0 in library work.
Running optimization stage 1 on CoretxM1_0 .......
Only the first 100 messages of id 'CG364' are reported. To see all messages use 'report_messages -log C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\synlog\top_compiler.srr -id CG364' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG364} -count unlimited' in the Tcl shell.
BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s .......
SYNC_RESET=32'b00000000000000000000000000000000
TX_FIFO=32'b00000000000000000000000000000000
CUARTI1ll=32'b00000000000000000000000000000000
CUARTl1ll=32'b00000000000000000000000000000001
CUARTOO0l=32'b00000000000000000000000000000010
CUARTIO0l=32'b00000000000000000000000000000011
CUARTlO0l=32'b00000000000000000000000000000100
CUARTOI0l=32'b00000000000000000000000000000101
CUARTII0l=32'b00000000000000000000000000000110
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s
@W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@N:CG179 : Tx_async.v(870) | Removing redundant assignment.
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s .......
@W:CL190 : Tx_async.v(301) | Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W:CL169 : Tx_async.v(301) | Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers.
SYNC_RESET=32'b00000000000000000000000000000000
RX_FIFO=32'b00000000000000000000000000000000
CUARTOIIl=32'b00000000000000000000000000000000
CUARTIIIl=32'b00000000000000000000000000000001
CUARTlIIl=32'b00000000000000000000000000000010
CUARTOlIl=32'b00000000000000000000000000000011
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s
@N:CG179 : Rx_async.v(750) | Removing redundant assignment.
@N:CG179 : Rx_async.v(857) | Removing redundant assignment.
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s .......
@W:CL177 : Rx_async.v(1613) | Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
TX_FIFO=32'b00000000000000000000000000000000
RX_FIFO=32'b00000000000000000000000000000000
RX_LEGACY_MODE=32'b00000000000000000000000000000000
FAMILY=32'b00000000000000000000000000011010
BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s
@N:CG179 : CoreUART.v(1338) | Removing redundant assignment.
@W:CG133 : CoreUART.v(333) | Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s .......
@W:CL169 : CoreUART.v(1268) | Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(1106) | Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(984) | Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(936) | Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(936) | Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(888) | Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(888) | Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreUART.v(405) | Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers.
FAMILY=32'b00000000000000000000000000011010
TX_FIFO=32'b00000000000000000000000000000000
RX_FIFO=32'b00000000000000000000000000000000
BAUD_VALUE=32'b00000000000000000000000000000001
FIXEDMODE=32'b00000000000000000000000000000000
PRG_BIT8=32'b00000000000000000000000000000000
PRG_PARITY=32'b00000000000000000000000000000000
RX_LEGACY_MODE=32'b00000000000000000000000000000000
BAUD_VAL_FRCTN=32'b00000000000000000000000000000000
BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
Generated name = CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z8
@N:CG179 : CoreUARTapb.v(785) | Removing redundant assignment.
@N:CG179 : CoreUARTapb.v(868) | Removing redundant assignment.
@W:CG133 : CoreUARTapb.v(283) | Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z8 .......
Running optimization stage 1 on CoreUARTapb_0 .......
@W:CG1283 : PF_CCC_0_PF_CCC_0_0_PF_CCC.v(39) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
Running optimization stage 1 on PLL .......
Running optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC .......
Running optimization stage 1 on PF_CCC_0 .......
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(40) | Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(40) | Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(40) | Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(40) | Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(40) | Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
Running optimization stage 1 on INIT .......
@W:CG1283 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(50) | Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type
Running optimization stage 1 on BANKEN .......
Running optimization stage 1 on PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR .......
@W:CL168 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(52) | Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W:CL168 : PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v(51) | Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
Running optimization stage 1 on PF_INIT_MONITOR_0 .......
Running optimization stage 1 on pf_reset_pf_reset_0_CORERESET_PF .......
Running optimization stage 1 on pf_reset .......
FAMILY=32'b00000000000000000000000000011010
MEM_DEPTH=32'b00000000000000010000000000000000
SEL_SRAM_TYPE=32'b00000000000000000000000000000000
SYNC_RESET=32'b00000000000000000000000000000000
ECC=32'b00000000000000000000000000000000
PIPE=32'b00000000000000000000000000000001
MEM_AWIDTH=32'b00000000000000000000000000010000
AHB_DWIDTH=32'b00000000000000000000000000100000
AHB_AWIDTH=32'b00000000000000000000000000100000
Generated name = PF_SRAM_COREAHBLSRAM_PF_0_COREAHBLSRAM_PF_26s_65536s_0s_0s_0s_1s_16_32s_32s
SYNC_RESET=32'b00000000000000000000000000000000
MEM_AWIDTH=32'b00000000000000000000000000010000
PIPE=32'b00000000000000000000000000000001
SEL_SRAM_TYPE=32'b00000000000000000000000000000000
MEM_DEPTH=32'b00000000000000010000000000000000
IDLE=2'b00
AHB_WR=2'b01
AHB_RD=2'b10
AHB_DWIDTH=32'b00000000000000000000000000100000
AHB_AWIDTH=32'b00000000000000000000000000100000
RESP_OKAY=2'b00
RESP_ERROR=2'b01
TRN_IDLE=2'b00
TRN_BUSY=2'b01
TRN_SEQ=2'b11
TRN_NONSEQ=2'b10
SINGLE=3'b000
INCR=3'b001
WRAP4=3'b010
INCR4=3'b011
WRAP8=3'b100
INCR8=3'b101
WRAP16=3'b110
INCR16=3'b111
Generated name = PF_SRAM_COREAHBLSRAM_PF_0_CoreAHBLSRAM_AHBLSram_Z9
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(139) | Object latchahbcmd is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(141) | Object ahbsram_wdata_usram is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(142) | Object ahbsram_wdata_usram_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(146) | Object count is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(151) | Object sramahb_ack_int is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(152) | Object sram_ren_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(153) | Object sram_ren_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(154) | Object sram_ren_d3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(155) | Object sram_done is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(156) | Object sramahb_rdata is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(158) | Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(159) | Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(162) | Object raddr_c_r is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(201) | Object ahb_write_d is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(202) | Object ahb_write_det is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(203) | Object ahb_write_det_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(204) | Object ahb_write_det_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(205) | Object ahb_write_det_d3 is declared but not assigned. Either assign a value or remove the declaration.
@W:CG133 : CoreAHBLSRAM_AHBLSram.v(206) | Object ram_rdata_d is declared but not assigned. Either assign a value or remove the declaration.
Running optimization stage 1 on PF_SRAM_COREAHBLSRAM_PF_0_CoreAHBLSRAM_AHBLSram_Z9 .......
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(607) | Pruning unused register genblk1.beat_cnt_dec_en. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(590) | Pruning unused register genblk1.beat_cnt[4:0]. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(491) | Pruning unused register busy_detect_d. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(480) | Pruning unused register busy_detect. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(420) | Pruning unused register first_busy_det. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(411) | Pruning unused register single_beat_d. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(396) | Pruning unused register newreadtrans_d2. Make sure that there are no unused intermediate registers.
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(351) | Pruning unused register burst_count_reg[4:0]. Make sure that there are no unused intermediate registers.
Running optimization stage 1 on PF_SRAM_COREAHBLSRAM_PF_0_COREAHBLSRAM_PF_26s_65536s_0s_0s_0s_1s_16_32s_32s .......
Running optimization stage 1 on OR4 .......
Running optimization stage 1 on OR2 .......
Running optimization stage 1 on INV .......
Running optimization stage 1 on PF_SRAM_PF_TPSRAM_AHB_AXI_0_PF_TPSRAM .......
Running optimization stage 1 on PF_SRAM .......
Running optimization stage 1 on top .......
Running optimization stage 2 on top .......
Running optimization stage 2 on PF_SRAM .......
Running optimization stage 2 on PF_SRAM_PF_TPSRAM_AHB_AXI_0_PF_TPSRAM .......
Running optimization stage 2 on INV .......
Running optimization stage 2 on OR2 .......
Running optimization stage 2 on OR4 .......
Running optimization stage 2 on PF_SRAM_COREAHBLSRAM_PF_0_CoreAHBLSRAM_AHBLSram_Z9 .......
@W:CL169 : CoreAHBLSRAM_AHBLSram.v(386) | Pruning unused register newreadtrans_d. Make sure that there are no unused intermediate registers.
@N:CL201 : CoreAHBLSRAM_AHBLSram.v(258) | Trying to extract state machine for register ahbcurr_state.
Extracted state machine for register ahbcurr_state
State machine has 3 reachable states with original encodings of:
00
01
10
@W:CL246 : CoreAHBLSRAM_AHBLSram.v(109) | Input port bits 31 to 16 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on PF_SRAM_COREAHBLSRAM_PF_0_COREAHBLSRAM_PF_26s_65536s_0s_0s_0s_1s_16_32s_32s .......
Running optimization stage 2 on pf_reset .......
Running optimization stage 2 on pf_reset_pf_reset_0_CORERESET_PF .......
@N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1.
Running optimization stage 2 on PF_INIT_MONITOR_0 .......
Running optimization stage 2 on PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR .......
Running optimization stage 2 on BANKEN .......
Running optimization stage 2 on INIT .......
Running optimization stage 2 on PF_CCC_0 .......
Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC .......
Running optimization stage 2 on PLL .......
Running optimization stage 2 on CoreUARTapb_0 .......
Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z8 .......
@W:CL246 : CoreUARTapb.v(126) | Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
@A:CL153 : CoreUARTapb.v(283) | *Unassigned bits of CUARTI1OI[2:0] are referenced and tied to 0 -- simulation mismatch possible.
Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s .......
Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s .......
@N:CL201 : Rx_async.v(871) | Trying to extract state machine for register CUARTll0.
Extracted state machine for register CUARTll0
State machine has 4 reachable states with original encodings of:
00
01
10
11
Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s .......
@N:CL201 : Tx_async.v(301) | Trying to extract state machine for register CUARTlI0l.
Extracted state machine for register CUARTlI0l
State machine has 6 reachable states with original encodings of:
00000000000000000000000000000000
00000000000000000000000000000001
00000000000000000000000000000010
00000000000000000000000000000011
00000000000000000000000000000100
00000000000000000000000000000101
@N:CL159 : Tx_async.v(81) | Input CUARTI1I is unused.
@N:CL159 : Tx_async.v(84) | Input CUARTlO1 is unused.
@N:CL159 : Tx_async.v(87) | Input CUARTOI1 is unused.
Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s .......
@N:CL159 : Clock_gen.v(75) | Input BAUD_VAL_FRACTION is unused.
Running optimization stage 2 on CoretxM1_0 .......
Running optimization stage 2 on CortexM1DbgIntegration .......
Running optimization stage 2 on CCORTEXM1O11IOI .......
Running optimization stage 2 on CCORTEXM1II1lOI_1s_0s .......
Running optimization stage 2 on CCORTEXM1l1IOII .......
Running optimization stage 2 on CCORTEXM1Il1lOI_1 .......
Running optimization stage 2 on CCORTEXM1Il1lOI_0 .......
Running optimization stage 2 on CCORTEXM1Il1lOI .......
Running optimization stage 2 on CCORTEXM1lOOlOI .......
Running optimization stage 2 on CCORTEXM1IlOlOI_0 .......
Running optimization stage 2 on CCORTEXM1IlOlOI .......
Running optimization stage 2 on CCORTEXM1I1IOII .......
Running optimization stage 2 on CCORTEXM1OOIlOI .......
Running optimization stage 2 on CCORTEXM1O0l0OI .......
Running optimization stage 2 on CCORTEXM1lO1I0I_8_DTCM_image_1s_15_0_32s_536870912_537001983_400000s_Z2 .......
Running optimization stage 2 on CCORTEXM1IO1I0I_8_ITCM_image_1s_15_0_32s_0_131071_400000s_Z1 .......
Running optimization stage 2 on RAM1K20 .......
Running optimization stage 2 on CCORTEXM1lllI0I_32s_1s_0s_0s_0s .......
Running optimization stage 2 on CCORTEXM1I0001 .......
Running optimization stage 2 on CCORTEXM1IOl11 .......
Running optimization stage 2 on CCORTEXM1lIl11_7 .......
Running optimization stage 2 on CCORTEXM1lIl11_6 .......
Running optimization stage 2 on CCORTEXM1lIl11_3 .......
Running optimization stage 2 on CCORTEXM1lIl11_1 .......
Running optimization stage 2 on CCORTEXM1l1I11 .......
Running optimization stage 2 on CCORTEXM1lIl11_2 .......
Running optimization stage 2 on CCORTEXM1lIl11_0 .......
Running optimization stage 2 on CCORTEXM1lIl11 .......
Running optimization stage 2 on CCORTEXM1lIl11_4 .......
Running optimization stage 2 on CCORTEXM1O1I11 .......
Running optimization stage 2 on CCORTEXM1I0I11 .......
Running optimization stage 2 on CCORTEXM1I0IlI_0s .......
Running optimization stage 2 on CCORTEXM1IIIOI_1s_1s_0s_0s_32s .......
Running optimization stage 2 on CCORTEXM1I0OlI_0s_0s .......
Running optimization stage 2 on CCORTEXM1IlOI1_32s_0 .......
Running optimization stage 2 on CCORTEXM1l101I .......
Running optimization stage 2 on CCORTEXM1IIOI1_0s .......
Running optimization stage 2 on CCORTEXM1IOIl1_0s .......
Running optimization stage 2 on MACC_PA .......
Running optimization stage 2 on CCORTEXM1OlIl1 .......
Running optimization stage 2 on CCORTEXM1lOOI1 .......
Running optimization stage 2 on CCORTEXM1ll1I0I .......
Running optimization stage 2 on CCORTEXM1OOOI1 .......
Running optimization stage 2 on RAM64x12 .......
Running optimization stage 2 on CCORTEXM1llOlI_1s_1s_0s_32s .......
Running optimization stage 2 on CCORTEXM1llI1l_1s_1s_32s .......
Running optimization stage 2 on CCORTEXM1IOI1l .......
Running optimization stage 2 on CCORTEXM1l1O1l_1s_0s .......
Running optimization stage 2 on CCORTEXM1OlOlI .......
Running optimization stage 2 on CCORTEXM1Oll0lI_0s .......
Running optimization stage 2 on CCORTEXM1I100lI .......
Running optimization stage 2 on CCORTEXM1l000lI .......
Running optimization stage 2 on CCORTEXM1I0lllI_0s .......
Running optimization stage 2 on CCORTEXM1llIOlI_0s .......
Running optimization stage 2 on CCORTEXM1O11OlI .......
Running optimization stage 2 on CCORTEXM1IlOOlI .......
Running optimization stage 2 on CCORTEXM1I1OI0I .......
Running optimization stage 2 on CCORTEXM1OIlO0I .......
Running optimization stage 2 on CCORTEXM1lOl1lI .......
Running optimization stage 2 on CCORTEXM1O1l_1s_32s_1s_0s .......
Running optimization stage 2 on CCORTEXM1llII_1s .......
Running optimization stage 2 on CCORTEXM1OlII_32s .......
Running optimization stage 2 on CCORTEXM1lOIl_4s .......
Running optimization stage 2 on CCORTEXM1OlIl_32s .......
Running optimization stage 2 on CCORTEXM1lOIl_32s .......
Running optimization stage 2 on CCORTEXM1IIII_1s_1s .......
Running optimization stage 2 on CCORTEXM1lOII_1s_32s_1s_0s .......
Running optimization stage 2 on VCC .......
Running optimization stage 2 on GND .......
Running optimization stage 2 on CFG2 .......
Running optimization stage 2 on CFG3 .......
Running optimization stage 2 on CFG4 .......
Running optimization stage 2 on ARI1 .......
Running optimization stage 2 on SLE .......
Running optimization stage 2 on CFG1 .......
Running optimization stage 2 on ccortexm1_uj_jtag_51 .......
Running optimization stage 2 on ccortexm1_UJTAG_WRAPPER .......
Running optimization stage 2 on UJTAG .......
Running optimization stage 2 on CORECORTEXM1_Z7 .......
@N:CL135 : CORECORTEXM1.v(469) | Found sequential shift genblk1.merged_sysresetn_q4 with address depth of 4 words and data bit width of 1.
@N:CL135 : CORECORTEXM1.v(497) | Found sequential shift genblk1.dbgresetn_q4 with address depth of 4 words and data bit width of 1.
@N:CL135 : CORECORTEXM1.v(532) | Found sequential shift genblk1.merged_wdogresn_q4 with address depth of 4 words and data bit width of 1.
@W:CL247 : CORECORTEXM1.v(244) | Input port bit 1 of HRESP[1:0] is unused
Running optimization stage 2 on CLKINT .......
Running optimization stage 2 on CoreGPIO_0 .......
Running optimization stage 2 on CoreGPIO_0_CoreGPIO_0_0_CoreGPIO_Z6 .......
@W:CL246 : coregpio.v(182) | Input port bits 31 to 4 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : coregpio.v(186) | Input GPIO_IN is unused.
Running optimization stage 2 on CoreAPB3_0 .......
Running optimization stage 2 on CoreAPB3_Z5 .......
@W:CL246 : coreapb3.v(75) | Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@N:CL159 : coreapb3.v(72) | Input IADDR is unused.
@N:CL159 : coreapb3.v(73) | Input PRESETN is unused.
@N:CL159 : coreapb3.v(74) | Input PCLK is unused.
@N:CL159 : coreapb3.v(106) | Input PRDATAS2 is unused.
@N:CL159 : coreapb3.v(107) | Input PRDATAS3 is unused.
@N:CL159 : coreapb3.v(108) | Input PRDATAS4 is unused.
@N:CL159 : coreapb3.v(109) | Input PRDATAS5 is unused.
@N:CL159 : coreapb3.v(110) | Input PRDATAS6 is unused.
@N:CL159 : coreapb3.v(111) | Input PRDATAS7 is unused.
@N:CL159 : coreapb3.v(112) | Input PRDATAS8 is unused.
@N:CL159 : coreapb3.v(113) | Input PRDATAS9 is unused.
@N:CL159 : coreapb3.v(114) | Input PRDATAS10 is unused.
@N:CL159 : coreapb3.v(115) | Input PRDATAS11 is unused.
@N:CL159 : coreapb3.v(116) | Input PRDATAS12 is unused.
@N:CL159 : coreapb3.v(117) | Input PRDATAS13 is unused.
@N:CL159 : coreapb3.v(118) | Input PRDATAS14 is unused.
@N:CL159 : coreapb3.v(119) | Input PRDATAS15 is unused.
@N:CL159 : coreapb3.v(123) | Input PREADYS2 is unused.
@N:CL159 : coreapb3.v(124) | Input PREADYS3 is unused.
@N:CL159 : coreapb3.v(125) | Input PREADYS4 is unused.
@N:CL159 : coreapb3.v(126) | Input PREADYS5 is unused.
@N:CL159 : coreapb3.v(127) | Input PREADYS6 is unused.
@N:CL159 : coreapb3.v(128) | Input PREADYS7 is unused.
@N:CL159 : coreapb3.v(129) | Input PREADYS8 is unused.
@N:CL159 : coreapb3.v(130) | Input PREADYS9 is unused.
@N:CL159 : coreapb3.v(131) | Input PREADYS10 is unused.
@N:CL159 : coreapb3.v(132) | Input PREADYS11 is unused.
@N:CL159 : coreapb3.v(133) | Input PREADYS12 is unused.
@N:CL159 : coreapb3.v(134) | Input PREADYS13 is unused.
@N:CL159 : coreapb3.v(135) | Input PREADYS14 is unused.
@N:CL159 : coreapb3.v(136) | Input PREADYS15 is unused.
@N:CL159 : coreapb3.v(140) | Input PSLVERRS2 is unused.
@N:CL159 : coreapb3.v(141) | Input PSLVERRS3 is unused.
@N:CL159 : coreapb3.v(142) | Input PSLVERRS4 is unused.
@N:CL159 : coreapb3.v(143) | Input PSLVERRS5 is unused.
@N:CL159 : coreapb3.v(144) | Input PSLVERRS6 is unused.
@N:CL159 : coreapb3.v(145) | Input PSLVERRS7 is unused.
@N:CL159 : coreapb3.v(146) | Input PSLVERRS8 is unused.
@N:CL159 : coreapb3.v(147) | Input PSLVERRS9 is unused.
@N:CL159 : coreapb3.v(148) | Input PSLVERRS10 is unused.
@N:CL159 : coreapb3.v(149) | Input PSLVERRS11 is unused.
@N:CL159 : coreapb3.v(150) | Input PSLVERRS12 is unused.
@N:CL159 : coreapb3.v(151) | Input PSLVERRS13 is unused.
@N:CL159 : coreapb3.v(152) | Input PSLVERRS14 is unused.
@N:CL159 : coreapb3.v(153) | Input PSLVERRS15 is unused.
Running optimization stage 2 on COREAPB3_MUXPTOB3 .......
Running optimization stage 2 on coreahblite_0 .......
Running optimization stage 2 on coreahblite_0_coreahblite_0_0_CoreAHBLite_Z4 .......
@W:CL247 : coreahblite.v(184) | Input port bit 1 of HRESP_S0[1:0] is unused
@W:CL247 : coreahblite.v(197) | Input port bit 1 of HRESP_S1[1:0] is unused
@W:CL247 : coreahblite.v(210) | Input port bit 1 of HRESP_S2[1:0] is unused
@W:CL247 : coreahblite.v(223) | Input port bit 1 of HRESP_S3[1:0] is unused
@W:CL247 : coreahblite.v(236) | Input port bit 1 of HRESP_S4[1:0] is unused
@W:CL247 : coreahblite.v(249) | Input port bit 1 of HRESP_S5[1:0] is unused
@W:CL247 : coreahblite.v(262) | Input port bit 1 of HRESP_S6[1:0] is unused
@W:CL247 : coreahblite.v(275) | Input port bit 1 of HRESP_S7[1:0] is unused
@W:CL247 : coreahblite.v(288) | Input port bit 1 of HRESP_S8[1:0] is unused
@W:CL247 : coreahblite.v(301) | Input port bit 1 of HRESP_S9[1:0] is unused
@W:CL247 : coreahblite.v(314) | Input port bit 1 of HRESP_S10[1:0] is unused
@W:CL247 : coreahblite.v(327) | Input port bit 1 of HRESP_S11[1:0] is unused
@W:CL247 : coreahblite.v(340) | Input port bit 1 of HRESP_S12[1:0] is unused
@W:CL247 : coreahblite.v(353) | Input port bit 1 of HRESP_S13[1:0] is unused
@W:CL247 : coreahblite.v(366) | Input port bit 1 of HRESP_S14[1:0] is unused
@W:CL247 : coreahblite.v(379) | Input port bit 1 of HRESP_S15[1:0] is unused
@W:CL247 : coreahblite.v(392) | Input port bit 1 of HRESP_S16[1:0] is unused
@N:CL159 : coreahblite.v(145) | Input HPROT_M0 is unused.
@N:CL159 : coreahblite.v(156) | Input HPROT_M1 is unused.
@N:CL159 : coreahblite.v(167) | Input HPROT_M2 is unused.
@N:CL159 : coreahblite.v(178) | Input HPROT_M3 is unused.
Running optimization stage 2 on COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s .......
@N:CL159 : coreahblite_matrix4x16.v(53) | Input HWDATA_M1 is unused.
@N:CL159 : coreahblite_matrix4x16.v(63) | Input HWDATA_M2 is unused.
@N:CL159 : coreahblite_matrix4x16.v(73) | Input HWDATA_M3 is unused.
@N:CL159 : coreahblite_matrix4x16.v(89) | Input HRDATA_S1 is unused.
@N:CL159 : coreahblite_matrix4x16.v(90) | Input HREADYOUT_S1 is unused.
@N:CL159 : coreahblite_matrix4x16.v(91) | Input HRESP_S1 is unused.
@N:CL159 : coreahblite_matrix4x16.v(101) | Input HRDATA_S2 is unused.
@N:CL159 : coreahblite_matrix4x16.v(102) | Input HREADYOUT_S2 is unused.
@N:CL159 : coreahblite_matrix4x16.v(103) | Input HRESP_S2 is unused.
@N:CL159 : coreahblite_matrix4x16.v(113) | Input HRDATA_S3 is unused.
@N:CL159 : coreahblite_matrix4x16.v(114) | Input HREADYOUT_S3 is unused.
@N:CL159 : coreahblite_matrix4x16.v(115) | Input HRESP_S3 is unused.
@N:CL159 : coreahblite_matrix4x16.v(137) | Input HRDATA_S5 is unused.
@N:CL159 : coreahblite_matrix4x16.v(138) | Input HREADYOUT_S5 is unused.
@N:CL159 : coreahblite_matrix4x16.v(139) | Input HRESP_S5 is unused.
@N:CL159 : coreahblite_matrix4x16.v(149) | Input HRDATA_S6 is unused.
@N:CL159 : coreahblite_matrix4x16.v(150) | Input HREADYOUT_S6 is unused.
@N:CL159 : coreahblite_matrix4x16.v(151) | Input HRESP_S6 is unused.
@N:CL159 : coreahblite_matrix4x16.v(161) | Input HRDATA_S7 is unused.
@N:CL159 : coreahblite_matrix4x16.v(162) | Input HREADYOUT_S7 is unused.
@N:CL159 : coreahblite_matrix4x16.v(163) | Input HRESP_S7 is unused.
@N:CL159 : coreahblite_matrix4x16.v(173) | Input HRDATA_S8 is unused.
@N:CL159 : coreahblite_matrix4x16.v(174) | Input HREADYOUT_S8 is unused.
@N:CL159 : coreahblite_matrix4x16.v(175) | Input HRESP_S8 is unused.
@N:CL159 : coreahblite_matrix4x16.v(185) | Input HRDATA_S9 is unused.
@N:CL159 : coreahblite_matrix4x16.v(186) | Input HREADYOUT_S9 is unused.
@N:CL159 : coreahblite_matrix4x16.v(187) | Input HRESP_S9 is unused.
@N:CL159 : coreahblite_matrix4x16.v(197) | Input HRDATA_S10 is unused.
@N:CL159 : coreahblite_matrix4x16.v(198) | Input HREADYOUT_S10 is unused.
@N:CL159 : coreahblite_matrix4x16.v(199) | Input HRESP_S10 is unused.
@N:CL159 : coreahblite_matrix4x16.v(209) | Input HRDATA_S11 is unused.
@N:CL159 : coreahblite_matrix4x16.v(210) | Input HREADYOUT_S11 is unused.
@N:CL159 : coreahblite_matrix4x16.v(211) | Input HRESP_S11 is unused.
@N:CL159 : coreahblite_matrix4x16.v(221) | Input HRDATA_S12 is unused.
@N:CL159 : coreahblite_matrix4x16.v(222) | Input HREADYOUT_S12 is unused.
@N:CL159 : coreahblite_matrix4x16.v(223) | Input HRESP_S12 is unused.
@N:CL159 : coreahblite_matrix4x16.v(233) | Input HRDATA_S13 is unused.
@N:CL159 : coreahblite_matrix4x16.v(234) | Input HREADYOUT_S13 is unused.
@N:CL159 : coreahblite_matrix4x16.v(235) | Input HRESP_S13 is unused.
@N:CL159 : coreahblite_matrix4x16.v(245) | Input HRDATA_S14 is unused.
@N:CL159 : coreahblite_matrix4x16.v(246) | Input HREADYOUT_S14 is unused.
@N:CL159 : coreahblite_matrix4x16.v(247) | Input HRESP_S14 is unused.
@N:CL159 : coreahblite_matrix4x16.v(257) | Input HRDATA_S15 is unused.
@N:CL159 : coreahblite_matrix4x16.v(258) | Input HREADYOUT_S15 is unused.
@N:CL159 : coreahblite_matrix4x16.v(259) | Input HRESP_S15 is unused.
@N:CL159 : coreahblite_matrix4x16.v(269) | Input HRDATA_S16 is unused.
Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell.
Running optimization stage 2 on COREAHBLITE_SLAVESTAGE_0s_0_0 .......
Running optimization stage 2 on COREAHBLITE_SLAVEARBITER_Z3 .......
@N:CL201 : coreahblite_slavearbiter.v(449) | Trying to extract state machine for register arbRegSMCurrentState.
Extracted state machine for register arbRegSMCurrentState
State machine has 16 reachable states with original encodings of:
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_4_1_0_0_0s_0_1_0 .......
Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z2 .......
Running optimization stage 2 on COREAHBLITE_MASTERSTAGE_4_1_0_17_0s_0_1_0 .......
@W:CL246 : coreahblite_masterstage.v(43) | Input port bits 16 to 5 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : coreahblite_masterstage.v(43) | Input port bits 3 to 1 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : coreahblite_masterstage.v(44) | Input port bits 16 to 5 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W:CL246 : coreahblite_masterstage.v(44) | Input port bits 3 to 1 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
Running optimization stage 2 on COREAHBLITE_DEFAULTSLAVESM_0s_0_1 .......
Running optimization stage 2 on COREAHBLITE_ADDRDEC_Z1 .......
Running optimization stage 2 on core_ahb_to_apb3 .......
Running optimization stage 2 on COREAHBTOAPB3_17s_0s .......
@W:CL247 : coreahbtoapb3.v(33) | Input port bit 0 of HTRANS[1:0] is unused
Running optimization stage 2 on CoreAHBtoAPB3_ApbAddrData_0s .......
Running optimization stage 2 on CoreAHBtoAPB3_PenableScheduler_0s_0_1_2 .......
@N:CL201 : coreahbtoapb3_penablescheduler.v(111) | Trying to extract state machine for register penableSchedulerState.
Extracted state machine for register penableSchedulerState
State machine has 3 reachable states with original encodings of:
00
01
10
Running optimization stage 2 on CoreAHBtoAPB3_AhbToApbSM_0s_0_1_0_1_2_3_4 .......
@N:CL201 : coreahbtoapb3_ahbtoapbsm.v(265) | Trying to extract state machine for register ahbToApbSMState.
Extracted state machine for register ahbToApbSMState
State machine has 5 reachable states with original encodings of:
000
001
010
011
100
For a summary of runtime and memory usage per design unit, please see file:
==========================================================
Linked File: layer0.rt.csv
At c_ver Exit (Real Time elapsed 0h:00m:46s; CPU Time elapsed 0h:00m:41s; Memory used current: 188MB peak: 193MB)
Process took 0h:00m:46s realtime, 0h:00m:41s cputime
Process completed successfully.
# Mon Jan 11 21:10:47 2021
###########################################################]
###########################################################[
Copyright (C) 1994-2020 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: Q-2020.03M-SP1
Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro
OS: Windows 6.2
Hostname: HYD-LT-I52881
Implementation : synthesis
Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @
@N: : | Running in 64-bit mode
File C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling
At syn_nfilter Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 125MB peak: 125MB)
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
Process completed successfully.
# Mon Jan 11 21:10:49 2021
###########################################################]
For a summary of runtime and memory usage for all design units, please see file:
==========================================================
Linked File: top_comp.rt.csv
@END
At c_hdl Exit (Real Time elapsed 0h:00m:49s; CPU Time elapsed 0h:00m:43s; Memory used current: 23MB peak: 23MB)
Process took 0h:00m:49s realtime, 0h:00m:43s cputime
Process completed successfully.
# Mon Jan 11 21:10:49 2021
###########################################################]