| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip PolarFire : MPF300T |
| Implementation Name | synthesis | Top Module | top |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
159 |
126 |
0 |
- |
00m:49s |
- |
11-01-2021
21:10:49 |
| (premap) | Complete |
22 |
17 |
0 |
0m:11s |
0m:13s |
222MB |
11-01-2021
21:11:07 |
| (fpga_mapper) | Complete |
115 |
55 |
0 |
0m:41s |
0m:46s |
243MB |
11-01-2021
21:11:54 |
| Multi-srs Generator |
Complete | | | | 00m:03s | | | 11-01-2021
21:10:53 |
| Area Summary |
|---|
| |
| Carry Cells | 582 |
Sequential Cells | 2324 |
| DSP Blocks
(dsp_used) | 3 |
I/O Cells | 8 |
| Global Clock Buffers | 6 |
RAM1K20
(v_ram) | 160 |
| RAM64x12
(v_ram) | 6 |
LUTs
(total_luts) | 5514 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| CORECORTEXM1_Z7|UDRCK | 100.0 MHz | 171.1 MHz | 2.077 |
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 80.0 MHz | 112.1 MHz | 3.578 |
| REF_CLK_0 | 50.0 MHz | NA | NA |
| System | 100.0 MHz | 281.1 MHz | 6.442 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 2 / 2 |
| |
|