@N: MF916 |Option synthesis_strategy=base is enabled. 
@N: MF248 |Running in 64-bit mode.
@N: MF667 |Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.)
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":647:4:647:19|Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_0(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_2(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_0(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":647:4:647:19|Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_1(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_1(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":647:4:647:19|Removing instance default_slave_sm (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_DEFAULTSLAVESM_0s_0_1_1_2(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Removing instance address_decode (in view: COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_0(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_ADDRDEC_Z2_2(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2879:2:2879:14|Removing instance masterstage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_2(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2945:2:2945:14|Removing instance masterstage_2 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_1(verilog) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":3011:2:3011:14|Removing instance masterstage_3 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_MASTERSTAGE_4_1_0_0s_0_1_0_0(verilog) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core_obfuscated\rx_async.v":1613:0:1613:5|Removing sequential instance CUARTI0I (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core_obfuscated\rx_async.v":1613:0:1613:5|Removing sequential instance CUARTIO0 (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":3123:2:3123:13|Removing instance slavestage_1 (in view: COREAHBLITE_LIB.COREAHBLITE_MATRIX4X16_4_1_0_17_0_0_0_0s(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v":84:4:84:9|Removing sequential instance masterDataInProg[3:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances.
@N: BN115 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v":92:56:92:68|Removing instance slave_arbiter (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVESTAGE_0s_0_0_1(verilog)) of type view:COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog) because it does not drive other instances.
@N: BN362 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\actel\directcore\coreahblite\5.5.101\rtl\vlog\core\coreahblite_slavearbiter.v":449:4:449:9|Removing sequential instance arbRegSMCurrentState[15:0] (in view: COREAHBLITE_LIB.COREAHBLITE_SLAVEARBITER_Z3_1(verilog)) of type view:PrimLib.statemachine(prim) because it does not drive other instances.
@N: FX1184 |Applying syn_allowed_resources blockrams=952 on top level netlist top 
@N: FX1143 |Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized.
@N: BN225 |Writing default property annotation file C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\top.sap.
@N: MO225 :"c:\wfh_tasks\rtg4_v12.6_updates\pf_v12.6\tu0778_cm1\libero_project\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core_obfuscated\rx_async.v":871:0:871:5|There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required.
