@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M0_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M1_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M2_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":568:2:568:11|Type of parameter M3_AHBSLOTENABLE on the instance matrix4x16 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2813:2:2813:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":633:0:633:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2879:2:2879:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_1 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":217:2:217:15|Type of parameter M_AHBSLOTENABLE on the instance address_decode is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL177 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":633:0:633:5|Sharing sequential element addrRegSMCurrentState. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":2945:2:2945:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_2 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v":3011:2:3011:14|Type of parameter M_AHBSLOTENABLE on the instance masterstage_3 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG360 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_both[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_neg[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.edge_pos[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":317:12:317:17|Pruning unused register xhdl1.GEN_BITS[3].gpin3[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[3].gpin1[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[3].gpin2[3]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_both[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_neg[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.edge_pos[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":317:12:317:17|Pruning unused register xhdl1.GEN_BITS[2].gpin3[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[2].gpin1[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[2].gpin2[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_both[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_neg[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.edge_pos[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":317:12:317:17|Pruning unused register xhdl1.GEN_BITS[1].gpin3[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[1].gpin1[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[1].gpin2[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":464:0:464:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_both[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":444:0:444:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_neg[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":424:0:424:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.edge_pos[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":317:12:317:17|Pruning unused register xhdl1.GEN_BITS[0].gpin3[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[0].gpin1[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":304:12:304:17|Pruning unused register xhdl1.GEN_BITS[0].gpin2[0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[0].APB_32.INTR_reg[0] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[1].APB_32.INTR_reg[1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[2].APB_32.INTR_reg[2] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Optimizing register bit xhdl1.GEN_BITS[3].APB_32.INTR_reg[3] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[0].APB_32.INTR_reg[0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[1].APB_32.INTR_reg[1]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[2].APB_32.INTR_reg[2]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":484:0:484:5|Pruning unused register xhdl1.GEN_BITS[3].APB_32.INTR_reg[3]. Make sure that there are no unused intermediate registers.
@W: CG1340 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CL190 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":333:0:333:7|Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1268:0:1268:5|Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1106:0:1106:5|Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":984:0:984:5|Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":405:0:405:5|Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":283:0:283:8|Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v":39:12:39:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":50:12:50:18|Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL168 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":52:8:52:15|Removing instance gnd_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v":51:8:51:15|Removing instance vcc_inst because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":139:26:139:36|Object latchahbcmd is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":141:26:141:44|Object ahbsram_wdata_usram is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":142:26:142:46|Object ahbsram_wdata_usram_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":146:14:146:18|Object count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":151:31:151:45|Object sramahb_ack_int is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":152:31:152:40|Object sram_ren_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":153:31:153:41|Object sram_ren_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":154:31:154:41|Object sram_ren_d3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":155:31:155:39|Object sram_done is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":156:31:156:43|Object sramahb_rdata is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":158:31:158:49|Object ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":159:31:159:51|Object u_ahbsram_wdata_upd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":162:26:162:34|Object raddr_c_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":201:31:201:41|Object ahb_write_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":202:31:202:43|Object ahb_write_det is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":203:31:203:46|Object ahb_write_det_d1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":204:31:204:46|Object ahb_write_det_d2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":205:31:205:46|Object ahb_write_det_d3 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":206:31:206:41|Object ram_rdata_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":607:8:607:13|Pruning unused register genblk1.beat_cnt_dec_en. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":590:9:590:14|Pruning unused register genblk1.beat_cnt[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":491:3:491:8|Pruning unused register busy_detect_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":480:3:480:8|Pruning unused register busy_detect. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":420:0:420:5|Pruning unused register first_busy_det. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":411:0:411:5|Pruning unused register single_beat_d. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":396:0:396:5|Pruning unused register newreadtrans_d2. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":351:0:351:5|Pruning unused register burst_count_reg[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":386:0:386:5|Pruning unused register newreadtrans_d. Make sure that there are no unused intermediate registers.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v":109:28:109:32|Input port bits 31 to 16 of HADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":126:0:126:4|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\CORECORTEXM1.v":244:20:244:24|Input port bit 1 of HRESP[1:0] is unused
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v":182:26:182:31|Input port bits 31 to 4 of PWDATA[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":184:15:184:22|Input port bit 1 of HRESP_S0[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":197:15:197:22|Input port bit 1 of HRESP_S1[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":210:15:210:22|Input port bit 1 of HRESP_S2[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":223:15:223:22|Input port bit 1 of HRESP_S3[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":236:15:236:22|Input port bit 1 of HRESP_S4[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":249:15:249:22|Input port bit 1 of HRESP_S5[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":262:15:262:22|Input port bit 1 of HRESP_S6[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":275:15:275:22|Input port bit 1 of HRESP_S7[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":288:15:288:22|Input port bit 1 of HRESP_S8[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":301:15:301:22|Input port bit 1 of HRESP_S9[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":314:15:314:23|Input port bit 1 of HRESP_S10[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":327:15:327:23|Input port bit 1 of HRESP_S11[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":340:15:340:23|Input port bit 1 of HRESP_S12[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":353:15:353:23|Input port bit 1 of HRESP_S13[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":366:15:366:23|Input port bit 1 of HRESP_S14[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":379:15:379:23|Input port bit 1 of HRESP_S15[1:0] is unused
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v":392:15:392:23|Input port bit 1 of HRESP_S16[1:0] is unused
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:25|Input port bits 16 to 5 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":43:16:43:25|Input port bits 3 to 1 of SDATAREADY[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":44:16:44:21|Input port bits 16 to 5 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v":44:16:44:21|Input port bits 3 to 1 of SHRESP[16:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3.v":33:28:33:33|Input port bit 0 of HTRANS[1:0] is unused

