SmartTime Version 12.900.20.24
Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)
Date: Mon Jan 11 21:22:22 2021
| Design | top |
| Family | PolarFire |
| Die | MPF300TS |
| Package | FCG1152 |
| Temperature Range | -40 - 100 C |
| Voltage Range | 1.0185 - 1.0815 V |
| Speed Grade | -1 |
| Design State | Post-Layout |
| Data source | Production |
| Multi Corner Report Operating Conditions | slow_lv_ht, slow_lv_lt, fast_hv_lt |
| Scenario for Timing Analysis | timing_analysis |
*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.
| Clock Domain | Required Period (ns) | Required Frequency (MHz) | Worst Slack (ns) | Operating Conditions |
|---|---|---|---|---|
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 | 80.000 | 6.361 | slow_lv_ht |
| REF_CLK_0 | 20.000 | 50.000 | ||
| SWCLKTCK | N/A | N/A |
| Worst Slack (ns) | Operating Conditions | |
|---|---|---|
| Input to Output |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_1_inst:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | 5.334 | 6.361 | 8.547 | 14.908 | 0.830 | 6.139 | slow_lv_ht |
| Path 2 | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_0_inst:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | 5.332 | 6.363 | 8.545 | 14.908 | 0.830 | 6.137 | slow_lv_ht |
| Path 3 | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_3_inst:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | 5.330 | 6.365 | 8.543 | 14.908 | 0.830 | 6.135 | slow_lv_ht |
| Path 4 | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_2_inst:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | 5.329 | 6.366 | 8.542 | 14.908 | 0.830 | 6.134 | slow_lv_ht |
| Path 5 | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1IlOl0I_CCORTEXM1IlOl0I_0_0/R_ADDR_1_inst:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | 5.309 | 6.385 | 8.523 | 14.908 | 0.830 | 6.115 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_1_inst:CLK | ||||||||
| To: CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | ||||||||
| data required time | 14.908 | |||||||
| data arrival time | - | 8.547 | ||||||
| slack | 6.361 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 1.384 | 1.384 | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.158 | 1.542 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.152 | 1.694 | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.377 | 2.071 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.151 | 2.222 | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.371 | 2.593 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:Y | cell | ADLIB:RGB | + | 0.052 | 2.645 | 1348 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_1_inst:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6_rgb_net_1 | + | 0.568 | 3.213 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_1_inst:Q | cell | ADLIB:SLE | + | 0.179 | 3.392 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/RAM64x12_PHYS_0/CFG_9:D | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/R_ADDR_1_inst_Q | + | 0.036 | 3.428 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/RAM64x12_PHYS_0/CFG_9:IPD | cell | ADLIB:CFG4_IP_ABCD | + | 0.030 | 3.458 | 1 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_ADDR[1] | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/RAM64x12_PHYS_0/R_ADDR_net[1] | + | 0.089 | 3.547 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_26/CCORTEXM1OlOl0I_CCORTEXM1OlOl0I_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:R_DATA[2] | cell | ADLIB:RAM64x12_IP | + | 0.733 | 4.280 | 11 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/CCORTEXM1O1IO1_0_m2[2]:B | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_net_607 | + | 0.504 | 4.784 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/CCORTEXM1O1IO1_0_m2[2]:Y | cell | ADLIB:CFG4 | + | 0.048 | 4.832 | 2 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_2:C | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_net_938 | + | 0.111 | 4.943 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_2:Y | cell | ADLIB:CFG3 | + | 0.048 | 4.991 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_2_RNIB5TI3:C | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/MSC_net_1323 | + | 0.388 | 5.379 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_2_RNIB5TI3:P | cell | ADLIB:ARI1_CC | + | 0.081 | 5.460 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_cry_0_cy_CC_0:P[3] | net | NET_CC_CONFIG423 | + | 0.012 | 5.472 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_cry_0_cy_CC_0:CO | cell | ADLIB:CC_CONFIG | + | 0.201 | 5.673 | 1 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_cry_0_cy_CC_1:CI | net | CI_TO_CO409 | + | 0.000 | 5.673 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_cry_0_cy_CC_1:CC[5] | cell | ADLIB:CC_CONFIG | + | 0.149 | 5.822 | 1 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_16_RNI8SENI:CC | net | NET_CC_CONFIG482 | + | 0.000 | 5.822 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1IOOI0_axb_16_RNI8SENI:S | cell | ADLIB:ARI1_CC | + | 0.044 | 5.866 | 4 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1l011I[16]:A | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_net_648 | + | 0.332 | 6.198 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_24/MSC_i_27/MSC_i_28/CCORTEXM1l011I[16]:Y | cell | ADLIB:CFG3 | + | 0.047 | 6.245 | 19 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/g0_0:D | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_net_282 | + | 0.374 | 6.619 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/g0_0:Y | cell | ADLIB:CFG4 | + | 0.045 | 6.664 | 8 | r | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | net | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/MSC_net_2709 | + | 1.883 | 8.547 | r | ||
| data arrival time | 8.547 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Clock Constraint | 12.500 | 12.500 | |||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 12.500 | r | |||
| Clock generation | + | 1.254 | 13.754 | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.144 | 13.898 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 14.029 | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_GB0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.343 | 14.372 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_GB0:Y | cell | ADLIB:GB | + | 0.138 | 14.510 | 6 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB13:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_gbs_1 | + | 0.338 | 14.848 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB13:Y | cell | ADLIB:RGB | + | 0.047 | 14.895 | 6 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB13_rgb_net_1 | + | 0.644 | 15.539 | r | ||
| clock reconvergence pessimism | + | 0.199 | 15.738 | |||||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_1/CCORTEXM1l0ll0I_1_CCORTEXM1l0ll0I_1_0_0/INST_RAM1K20_IP:A_WEN[0] | Library setup time | ADLIB:RAM1K20_IP | - | 0.830 | 14.908 | |||
| data required time | 14.908 | |||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | External Setup (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RX | CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D | 4.837 | 4.837 | 0.000 | 2.006 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RX | ||||||||
| To: CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 4.837 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RX | 0.000 | 0.000 | f | |||||
| RX_ibuf/U_IOPAD:PAD | net | RX | + | 0.000 | 0.000 | f | ||
| RX_ibuf/U_IOPAD:Y | cell | ADLIB:IOPAD_IN | + | 0.731 | 0.731 | 1 | f | |
| RX_ibuf/U_IOIN:YIN | net | RX_ibuf/YIN | + | 0.000 | 0.731 | f | ||
| RX_ibuf/U_IOIN:Y | cell | ADLIB:IOIN_IB_E | + | 0.338 | 1.069 | 1 | f | |
| CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D | net | RX_c | + | 3.768 | 4.837 | f | ||
| data arrival time | 4.837 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | N/C | N/C | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 1.254 | N/C | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.144 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | N/C | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.343 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.138 | N/C | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB8:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.329 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB8:Y | cell | ADLIB:RGB | + | 0.047 | N/C | 35 | f | |
| CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB8_rgb_net_1 | + | 0.445 | N/C | r | ||
| CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D | Library setup time | ADLIB:SLE | - | 0.000 | N/C | |||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Clock to Out (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|
| Path 1 | CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:CLK | GPIO_OUT[3] | 8.926 | 12.098 | 12.098 | slow_lv_ht | ||
| Path 2 | CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[2].APB_32.GPOUT_reg[2]:CLK | GPIO_OUT[2] | 8.817 | 11.989 | 11.989 | slow_lv_ht | ||
| Path 3 | CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[1].APB_32.GPOUT_reg[1]:CLK | GPIO_OUT[1] | 8.649 | 11.821 | 11.821 | slow_lv_ht | ||
| Path 4 | CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[0].APB_32.GPOUT_reg[0]:CLK | GPIO_OUT[0] | 8.528 | 11.700 | 11.700 | slow_lv_ht | ||
| Path 5 | CoreUARTapb_0_0/CoreUARTapb_0_0/CUARTlOlI/CUARTIO1/CUARTll1:CLK | TX | 6.828 | 9.994 | 9.994 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:CLK | ||||||||
| To: GPIO_OUT[3] | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 12.098 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 1.384 | 1.384 | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.158 | 1.542 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.152 | 1.694 | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.377 | 2.071 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.151 | 2.222 | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.363 | 2.585 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5:Y | cell | ADLIB:RGB | + | 0.052 | 2.637 | 315 | f | |
| CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5_rgb_net_1 | + | 0.535 | 3.172 | r | ||
| CoreGPIO_0_0/CoreGPIO_0_0/xhdl1.GEN_BITS[3].APB_32.GPOUT_reg[3]:Q | cell | ADLIB:SLE | + | 0.170 | 3.342 | 2 | f | |
| GPIO_OUT_obuf[3]/U_IOTRI:D | net | GPIO_OUT_c[3] | + | 5.804 | 9.146 | f | ||
| GPIO_OUT_obuf[3]/U_IOTRI:DOUT | cell | ADLIB:IOTRI_OB_EB | + | 0.918 | 10.064 | 1 | f | |
| GPIO_OUT_obuf[3]/U_IOPAD:D | net | GPIO_OUT_obuf[3]/DOUT | + | 0.000 | 10.064 | f | ||
| GPIO_OUT_obuf[3]/U_IOPAD:PAD | cell | ADLIB:IOPAD_TRI | + | 2.034 | 12.098 | 0 | f | |
| GPIO_OUT[3] | net | GPIO_OUT[3] | + | 0.000 | 12.098 | f | ||
| data arrival time | 12.098 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | N/C | N/C | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 1.254 | N/C | |||||
| GPIO_OUT[3] | N/C | f | ||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[0]:ALn | 2.645 | 9.575 | 5.833 | 15.408 | 0.183 | 2.925 | 0.097 | slow_lv_ht |
| Path 2 | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l01II_Z[1]:ALn | 2.642 | 9.576 | 5.830 | 15.406 | 0.183 | 2.924 | 0.099 | slow_lv_ht |
| Path 3 | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[1]:ALn | 2.644 | 9.576 | 5.832 | 15.408 | 0.183 | 2.924 | 0.097 | slow_lv_ht |
| Path 4 | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1OIlll[8]:ALn | 2.647 | 9.576 | 5.835 | 15.411 | 0.183 | 2.924 | 0.094 | slow_lv_ht |
| Path 5 | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1Il0II_Z[1]:ALn | 2.641 | 9.576 | 5.829 | 15.405 | 0.183 | 2.924 | 0.100 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | ||||||||
| To: CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[0]:ALn | ||||||||
| data required time | 15.408 | |||||||
| data arrival time | - | 5.833 | ||||||
| slack | 9.575 | |||||||
| Data arrival time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 0.000 | 0.000 | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 0.000 | r | |||
| Clock generation | + | 1.384 | 1.384 | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.158 | 1.542 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.152 | 1.694 | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.377 | 2.071 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.151 | 2.222 | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.371 | 2.593 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:Y | cell | ADLIB:RGB | + | 0.052 | 2.645 | 1348 | f | |
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6_rgb_net_1 | + | 0.543 | 3.188 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:Q | cell | ADLIB:SLE | + | 0.179 | 3.367 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE_net | + | 1.367 | 4.734 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA:Y | cell | ADLIB:GB | + | 0.112 | 4.846 | 5 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_RGB1_RGB3:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_Y | + | 0.370 | 5.216 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_RGB1_RGB3:Y | cell | ADLIB:RGB | + | 0.052 | 5.268 | 455 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[0]:ALn | net | CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_RGB1_RGB3_rgb_net_1 | + | 0.565 | 5.833 | r | ||
| data arrival time | 5.833 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Clock Constraint | 12.500 | 12.500 | |||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | 12.500 | r | |||
| Clock generation | + | 1.254 | 13.754 | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.144 | 13.898 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | 14.029 | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.343 | 14.372 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.138 | 14.510 | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB9:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.336 | 14.846 | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB9:Y | cell | ADLIB:RGB | + | 0.047 | 14.893 | 495 | f | |
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[0]:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB9_rgb_net_1 | + | 0.480 | 15.373 | r | ||
| clock reconvergence pessimism | + | 0.218 | 15.591 | |||||
| CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_4/MSC_i_19/MSC_i_20/CCORTEXM1l00Ol[0]:ALn | Library recovery time | ADLIB:SLE | - | 0.183 | 15.408 | |||
| data required time | 15.408 | |||||||
| Operating Conditions | slow_lv_ht |
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | External Recovery (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | RESETN | pf_reset_0/pf_reset_0/dff_15:ALn | 5.202 | 5.202 | 0.183 | 2.491 | slow_lv_ht | ||
| Path 2 | RESETN | pf_reset_0/pf_reset_0/dff_12:ALn | 5.201 | 5.201 | 0.183 | 2.490 | slow_lv_ht | ||
| Path 3 | RESETN | pf_reset_0/pf_reset_0/dff_14:ALn | 5.200 | 5.200 | 0.183 | 2.489 | slow_lv_ht | ||
| Path 4 | RESETN | pf_reset_0/pf_reset_0/dff_13:ALn | 5.200 | 5.200 | 0.183 | 2.489 | slow_lv_ht | ||
| Path 5 | RESETN | pf_reset_0/pf_reset_0/dff_11:ALn | 5.200 | 5.200 | 0.183 | 2.489 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: RESETN | ||||||||
| To: pf_reset_0/pf_reset_0/dff_15:ALn | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 5.202 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| RESETN | 0.000 | 0.000 | r | |||||
| RESETN_ibuf/U_IOPAD:PAD | net | RESETN | + | 0.000 | 0.000 | r | ||
| RESETN_ibuf/U_IOPAD:Y | cell | ADLIB:IOPAD_IN | + | 0.599 | 0.599 | 1 | r | |
| RESETN_ibuf/U_IOIN:YIN | net | RESETN_ibuf/YIN | + | 0.000 | 0.599 | r | ||
| RESETN_ibuf/U_IOIN:Y | cell | ADLIB:IOIN_IB_E | + | 0.336 | 0.935 | 1 | r | |
| pf_reset_0/pf_reset_0/un1_D:A | net | RESETN_c | + | 1.551 | 2.486 | r | ||
| pf_reset_0/pf_reset_0/un1_D:Y | cell | ADLIB:CFG4 | + | 0.145 | 2.631 | 16 | r | |
| pf_reset_0/pf_reset_0/dff_15:ALn | net | pf_reset_0/pf_reset_0/un1_INTERNAL_RST_i | + | 2.571 | 5.202 | r | ||
| data arrival time | 5.202 | |||||||
| Data required time calculation | ||||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | N/C | N/C | ||||||
| PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 | Clock source | + | 0.000 | N/C | r | |||
| Clock generation | + | 1.254 | N/C | |||||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A | net | PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 | + | 0.144 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.131 | N/C | 2 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET | + | 0.343 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y | cell | ADLIB:GB | + | 0.138 | N/C | 10 | r | |
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:A | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y | + | 0.334 | N/C | r | ||
| PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6:Y | cell | ADLIB:RGB | + | 0.047 | N/C | 1348 | f | |
| pf_reset_0/pf_reset_0/dff_15:CLK | net | PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB6_rgb_net_1 | + | 0.503 | N/C | r | ||
| pf_reset_0/pf_reset_0/dff_15:ALn | Library recovery time | ADLIB:SLE | - | 0.183 | N/C | |||
| Operating Conditions | slow_lv_ht |
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin REF_CLK_0_ibuf/U_IOPAD:PAD
No Path
No Path
No Path
No Path
No Path
No Path
Info: The maximum frequency of this clock domain is limited by the period of pin CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Setup (ns) | Minimum Period (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[3]:D | 13.151 | 13.151 | 0.000 | 19.548 | slow_lv_ht | ||
| Path 2 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[4]:D | 13.055 | 13.055 | 0.000 | 19.368 | slow_lv_ht | ||
| Path 3 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[0]:D | 12.953 | 12.953 | 0.000 | 19.150 | slow_lv_ht | ||
| Path 4 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[1]:D | 12.948 | 12.948 | 0.000 | 19.142 | slow_lv_ht | ||
| Path 5 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[2]:D | 12.731 | 12.731 | 0.000 | 18.722 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | ||||||||
| To: CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[3]:D | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 13.151 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| SWCLKTCK | 0.000 | 0.000 | ||||||
| SWCLKTCK | Clock source | + | 0.000 | 0.000 | f | |||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | net | SWCLKTCK | + | 0.000 | 0.000 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:UTDI | cell | ADLIB:UJTAG_SEC | + | 8.220 | 8.220 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_UTDI:A | net | CoretxM1_0_0/CoretxM1_0_0/UTDI_UTDI | + | 1.497 | 9.717 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_UTDI:Y | cell | ADLIB:CFG1D | + | 0.204 | 9.921 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_2_UTDI:A | net | CoretxM1_0_0/CoretxM1_0_0/UTDI_UTDI_2 | + | 0.158 | 10.079 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_2_UTDI:Y | cell | ADLIB:CFG1D | + | 0.204 | 10.283 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_3_UTDI:A | net | CoretxM1_0_0/CoretxM1_0_0/UTDI_UTDI_3 | + | 0.144 | 10.427 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_3_UTDI:Y | cell | ADLIB:CFG1D | + | 0.204 | 10.631 | 8 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4_1_2:B | net | CoretxM1_0_0/CoretxM1_0_0/UTDI | + | 0.162 | 10.793 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4_1_2:Y | cell | ADLIB:CFG4 | + | 0.204 | 10.997 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4:C | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4_1_2_Z | + | 0.136 | 11.133 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4:Y | cell | ADLIB:CFG4 | + | 0.132 | 11.265 | 1 | f | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m6:C | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m4_Z | + | 0.145 | 11.410 | f | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m6:Y | cell | ADLIB:CFG3 | + | 0.145 | 11.555 | 7 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m6_RNIBREI1:B | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI | + | 0.514 | 12.069 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1O0IIOI_m6_RNIBREI1:Y | cell | ADLIB:CFG3 | + | 0.140 | 12.209 | 3 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_0[3]:C | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/un1_CCORTEXM1OlIIOI_0_sqmuxa_5_s3 | + | 0.354 | 12.563 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_0[3]:Y | cell | ADLIB:CFG3 | + | 0.185 | 12.748 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_2[3]:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_0_Z[3] | + | 0.109 | 12.857 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_2[3]:Y | cell | ADLIB:CFG3 | + | 0.081 | 12.938 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv[3]:C | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv_2_Z[3] | + | 0.111 | 13.049 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20_1_iv[3]:Y | cell | ADLIB:CFG4 | + | 0.081 | 13.130 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[3]:D | net | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI_20[3] | + | 0.021 | 13.151 | r | ||
| data arrival time | 13.151 | |||||||
| Data required time calculation | ||||||||
| SWCLKTCK | N/C | N/C | ||||||
| SWCLKTCK | Clock source | + | 0.000 | N/C | r | |||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | net | SWCLKTCK | + | 0.000 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:UDRCK | cell | ADLIB:UJTAG_SEC | + | 1.698 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_1:A | net | CoretxM1_0_0/CoretxM1_0_0/UDRCK | + | 0.146 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.160 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_NET | + | 0.416 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint:Y | cell | ADLIB:GB | + | 0.138 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_RGB1:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_Y | + | 0.333 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | N/C | 26 | f | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[3]:CLK | net | CoretxM1_0_0/CoretxM1_0_0/UDRCK_BUF | + | 0.439 | N/C | r | ||
| clock reconvergence pessimism | + | 0.000 | N/C | |||||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1OlIIOI[3]:D | Library setup time | ADLIB:SLE | - | 0.000 | N/C | |||
| Operating Conditions | slow_lv_ht |
No Path
No Path
| From | To | Delay (ns) | Slack (ns) | Arrival (ns) | Required (ns) | Recovery (ns) | Minimum Period (ns) | Skew (ns) | Operating Conditions | |
|---|---|---|---|---|---|---|---|---|---|---|
| Path 1 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[2]:ALn | 9.991 | 9.991 | 0.183 | 6.781 | -3.393 | slow_lv_ht | ||
| Path 2 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[1]:ALn | 9.992 | 9.992 | 0.183 | 6.781 | -3.394 | slow_lv_ht | ||
| Path 3 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1IlIIOI[2]:ALn | 9.991 | 9.991 | 0.183 | 6.781 | -3.393 | slow_lv_ht | ||
| Path 4 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1IlIIOI[3]:ALn | 9.987 | 9.987 | 0.183 | 6.780 | -3.390 | slow_lv_ht | ||
| Path 5 | CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1IlIIOI[0]:ALn | 9.990 | 9.990 | 0.183 | 6.780 | -3.393 | slow_lv_ht |
| Pin Name | Type | Net Name | Cell Name | Op | Delay (ns) | Total (ns) | Fanout | Edge |
|---|---|---|---|---|---|---|---|---|
| From: CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | ||||||||
| To: CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[2]:ALn | ||||||||
| data required time | N/C | |||||||
| data arrival time | - | 9.991 | ||||||
| slack | N/C | |||||||
| Data arrival time calculation | ||||||||
| SWCLKTCK | 0.000 | 0.000 | ||||||
| SWCLKTCK | Clock source | + | 0.000 | 0.000 | r | |||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | net | SWCLKTCK | + | 0.000 | 0.000 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:URSTB | cell | ADLIB:UJTAG_SEC | + | 3.274 | 3.274 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_URSTB:A | net | CoretxM1_0_0/CoretxM1_0_0/URSTB_URSTB | + | 0.733 | 4.007 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_URSTB:Y | cell | ADLIB:CFG1D | + | 0.204 | 4.211 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_2_URSTB:A | net | CoretxM1_0_0/CoretxM1_0_0/URSTB_URSTB_2 | + | 0.254 | 4.465 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_2_URSTB:Y | cell | ADLIB:CFG1D | + | 0.204 | 4.669 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_3_URSTB:A | net | CoretxM1_0_0/CoretxM1_0_0/URSTB_URSTB_3 | + | 0.150 | 4.819 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_3_URSTB:Y | cell | ADLIB:CFG1D | + | 0.204 | 5.023 | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint:A | net | CoretxM1_0_0/CoretxM1_0_0/URSTB | + | 3.916 | 8.939 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint:Y | cell | ADLIB:GB | + | 0.115 | 9.054 | 2 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_RGB1_RGB0:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_Y | + | 0.366 | 9.420 | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_RGB1_RGB0:Y | cell | ADLIB:RGB | + | 0.052 | 9.472 | 25 | f | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[2]:ALn | net | CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_RGB1_RGB0_rgb_net_1 | + | 0.519 | 9.991 | r | ||
| data arrival time | 9.991 | |||||||
| Data required time calculation | ||||||||
| SWCLKTCK | N/C | N/C | ||||||
| SWCLKTCK | Clock source | + | 0.000 | N/C | r | |||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:TCK | net | SWCLKTCK | + | 0.000 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:UDRCK | cell | ADLIB:UJTAG_SEC | + | 1.698 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_1:A | net | CoretxM1_0_0/CoretxM1_0_0/UDRCK | + | 0.146 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_1:Y | cell | ADLIB:ICB_CLKINT | + | 0.160 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint_NET | + | 0.416 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint:Y | cell | ADLIB:GB | + | 0.138 | N/C | 1 | r | |
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_RGB1:A | net | CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_Y | + | 0.333 | N/C | r | ||
| CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_RGB1:Y | cell | ADLIB:RGB | + | 0.047 | N/C | 26 | f | |
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[2]:CLK | net | CoretxM1_0_0/CoretxM1_0_0/UDRCK_BUF | + | 0.455 | N/C | r | ||
| clock reconvergence pessimism | + | 0.000 | N/C | |||||
| CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/CCORTEXM1l1IIOI[2]:ALn | Library recovery time | ADLIB:SLE | - | 0.183 | N/C | |||
| Operating Conditions | slow_lv_ht |
No Path
No Path
No Path
No Path