Global Net Report

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Mon Jan 11 21:17:19 2021

Global Nets Information

From GB Location Net Name Fanout
1 PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0 (1153, 162) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y 2437
2 CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0 (1152, 162) CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_Y 1378
3 CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4_RNIIF47/U0 (1153, 163) CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4_RNIIF47/U0_Y 879
4 CoretxM1_0_0/CoretxM1_0_0/tck_clkint/U0 (1156, 162) CoretxM1_0_0/CoretxM1_0_0/tck_clkint/U0_Y 136
5 PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_GB0 (1165, 163) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_gbs_1 79
6 CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0 (1154, 162) CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_Y 37
7 CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0 (1155, 162) CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_Y 26

I/O to GB Connections

(none)

Fabric to GB Connections

From From Location To Net Name Net Type Fanout
1 CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE:Q (1032, 103) CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0 CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_GB_DEMOTE_net ROUTED 1
2 CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4:Q (1023, 97) CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4_RNIIF47/U0 CoretxM1_0_0/CoretxM1_0_0/dbgresetn_q4_0 ROUTED 1
3 CoretxM1_0_0/CoretxM1_0_0/genblk4.ujjtag/un1_duttck:Y (537, 42) CoretxM1_0_0/CoretxM1_0_0/tck_clkint/U0 CoretxM1_0_0/CoretxM1_0_0/un1_duttck ROUTED 2
4 CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst_3_URSTB:Y (434, 3) CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0 CoretxM1_0_0/CoretxM1_0_0/URSTB ROUTED 1
5 CoretxM1_0_0/CoretxM1_0_0/genblk4.UJ/UJTAG_inst:UDRCK (504, 2) CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0 CoretxM1_0_0/CoretxM1_0_0/UDRCK HARDWIRED 1

CCC to GB Connections

From From Location To Net Name Net Type Fanout
1 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 (2460, 5) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 HARDWIRED 1
2 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 (2460, 5) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_GB0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 HARDWIRED 1

CCC Input Connections

Port Name Pin Number I/O Function From From Location To CCC Location Net Name Net Type Fanout
1 REF_CLK_0 E25 HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 REF_CLK_0_ibuf/U_IOPAD:Y (2256, 1) PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:REF_CLK_0 (2460, 5) REF_CLK_0_c HARDWIRED 2

Local Nets to RGB Connections

(none)

Global Nets to RGB Connections

From From Location Net Name Fanout RGB Location Local Fanout
1 PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0 (1153, 162) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y 2437 1 (579, 39) 2
2 (579, 66) 35
3 (579, 93) 315
4 (579, 120) 33
5 (585, 39) 30
6 (585, 66) 495
7 (585, 93) 1348
8 (585, 120) 135
9 (585, 147) 32
10 (585, 177) 12
2 CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0 (1152, 162) CoretxM1_0_0/CoretxM1_0_0/genblk1.merged_sysresetn_q4_RNIN4VA/U0_Y 1378 1 (576, 66) 9
2 (576, 93) 248
3 (582, 66) 455
4 (582, 93) 635
5 (582, 120) 31
3 CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4_RNIIF47/U0 (1153, 163) CoretxM1_0_0/CoretxM1_0_0/genblk1.dbgresetn_q4_RNIIF47/U0_Y 879 1 (580, 39) 1
2 (580, 93) 146
3 (580, 120) 24
4 (586, 66) 8
5 (586, 93) 628
6 (586, 120) 72
4 CoretxM1_0_0/CoretxM1_0_0/tck_clkint/U0 (1156, 162) CoretxM1_0_0/CoretxM1_0_0/tck_clkint/U0_Y 136 1 (576, 94) 119
2 (576, 121) 17
5 PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_GB0 (1165, 163) PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_gbs_1 79 1 (1744, 12) 11
2 (1744, 39) 6
3 (1744, 66) 14
4 (1744, 93) 24
5 (1744, 120) 18
6 (1744, 147) 6
6 CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0 (1154, 162) CoretxM1_0_0/CoretxM1_0_0/genblk2.uj_rst_clkint/U0_Y 37 1 (577, 41) 25
2 (577, 95) 12
7 CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0 (1155, 162) CoretxM1_0_0/CoretxM1_0_0/genblk3.uj_clk_clkint/U0_Y 26 (580, 41) 26

Clock Signals Summary

The number of clock signals through H-Chip Global resources 4
The number of clock signals through Row Global resources 19
The number of clock signals through Sector Global resources 88
The number of clock signals through Cluster Global resources 551

Warning: Local Clock Nets

The following clocks are routed using regular routing resources instead of dedicated global resources. Clocks using regular routing are more susceptible to noise than those using dedicated global resources. Microchip recommends promoting these signals to dedicated global resources.

From Driving Net To
1 CoretxM1_0_0/CoretxM1_0_0/tck_clkint_RNI4L7E:Y CoretxM1_0_0/CoretxM1_0_0/M1_SWCLKTCK_BUF CoretxM1_0_0/CoretxM1_0_0/MSC_i_0/MSC_i_52/MSC_i_54/CCORTEXM1I110OI:CLK