#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\synthesis\run_options.txt
#--  Written on Mon Jan 11 21:10:00 2021


#project files
add_file -verilog "../component/polarfire_syn_comps.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreAPB3_0/CoreAPB3_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreGPIO_0/CoreGPIO_0_0/rtl/vlog/core/coregpio.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreGPIO_0/CoreGPIO_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Clock_gen.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Rx_async.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Tx_async.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/fifo_256x8_g5.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/CoreUART.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/CoreUARTapb.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CORECORTEXM1/4.0.100/rtl/vlog/core_encrypted/CortexM1DbgIntegration_PF.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CORECORTEXM1/4.0.100/core_encrypted/ccortexm1_ujtag_wrapper.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CORECORTEXM1/4.0.100/core_encrypted/ccortexm1_uj_jtag.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CORECORTEXM1/4.0.100/core_encrypted/CORECORTEXM1.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/CoretxM1_0/CoretxM1_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_CCC_0/PF_CCC_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_INIT_MONITOR_0/PF_INIT_MONITOR_0_0/PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_INIT_MONITOR_0/PF_INIT_MONITOR_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_SRAM/PF_TPSRAM_AHB_AXI_0/PF_SRAM_PF_TPSRAM_AHB_AXI_0_PF_TPSRAM.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_SRAM/COREAHBLSRAM_PF_0/rtl/vlog/core/CoreAHBLSRAM_AHBLSram_ECC.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_SRAM/COREAHBLSRAM_PF_0/rtl/vlog/core/CoreAHBLSRAM_AHBLSram.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_SRAM/COREAHBLSRAM_PF_0/rtl/vlog/core/CoreAHBLSRAM_PF.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/PF_SRAM/PF_SRAM.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.2.101/rtl/vlog/core/coreahbtoapb3_ahbtoapbsm.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.2.101/rtl/vlog/core/coreahbtoapb3_apbaddrdata.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.2.101/rtl/vlog/core/coreahbtoapb3_penablescheduler.v"
add_file -verilog -lib COREAHBTOAPB3_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/COREAHBTOAPB3/3.2.101/rtl/vlog/core/coreahbtoapb3.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/core_ahb_to_apb3/core_ahb_to_apb3.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_slavearbiter.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_slavestage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_defaultslavesm.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_addrdec.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_masterstage.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/Actel/DirectCore/CoreAHBLite/5.5.101/rtl/vlog/core/coreahblite_matrix4x16.v"
add_file -verilog -lib COREAHBLITE_LIB "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/coreahblite_0/coreahblite_0_0/rtl/vlog/core/coreahblite.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/coreahblite_0/coreahblite_0.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/pf_reset/pf_reset_0/core/corereset_pf.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/pf_reset/pf_reset.v"
add_file -verilog "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/WFH_Tasks/RTG4_v12.6_Updates/PF_v12.6/TU0778_CM1/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
