set_device -family {PolarFire} -die {MPF300TS} -speed {-1}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v}
read_verilog -mode system_verilog -lib COREAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreAPB3_0\CoreAPB3_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0_0\rtl\vlog\core\coregpio.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreGPIO_0\CoreGPIO_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Clock_gen.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Rx_async.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\fifo_256x8_g5.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\rtl\vlog\core_encrypted\CortexM1DbgIntegration_PF.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\ccortexm1_ujtag_wrapper.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\ccortexm1_uj_jtag.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CORECORTEXM1\4.0.100\core_encrypted\CORECORTEXM1.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\CoretxM1_0\CoretxM1_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_CCC_0\PF_CCC_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0_0\PF_INIT_MONITOR_0_PF_INIT_MONITOR_0_0_PF_INIT_MONITOR.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_INIT_MONITOR_0\PF_INIT_MONITOR_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\PF_TPSRAM_AHB_AXI_0\PF_SRAM_PF_TPSRAM_AHB_AXI_0_PF_TPSRAM.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram_ECC.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_AHBLSram.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\COREAHBLSRAM_PF_0\rtl\vlog\core\CoreAHBLSRAM_PF.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\PF_SRAM\PF_SRAM.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_ahbtoapbsm.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_apbaddrdata.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3_penablescheduler.v}
read_verilog -mode system_verilog -lib COREAHBTOAPB3_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\COREAHBTOAPB3\3.2.101\rtl\vlog\core\coreahbtoapb3.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\core_ahb_to_apb3\core_ahb_to_apb3.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavearbiter.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_slavestage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_defaultslavesm.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_addrdec.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_masterstage.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\Actel\DirectCore\CoreAHBLite\5.5.101\rtl\vlog\core\coreahblite_matrix4x16.v}
read_verilog -mode system_verilog -lib COREAHBLITE_LIB {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0_0\rtl\vlog\core\coreahblite.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\coreahblite_0\coreahblite_0.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\pf_reset\pf_reset_0\core\corereset_pf.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\pf_reset\pf_reset.v}
read_verilog -mode system_verilog {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\component\work\top\top.v}
set_top_level {top}
map_netlist
read_sdc {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\constraint\top_derived_constraints.sdc}
check_constraints {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\constraint\synthesis_sdc_errors.log}
write_fdc {C:\WFH_Tasks\RTG4_v12.6_Updates\PF_v12.6\TU0778_CM1\Libero_Project\designer\top\synthesis.fdc}
