//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Jan 11 20:24:10 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

//////////////////////////////////////////////////////////////////////
// Component Description (Tcl) 
//////////////////////////////////////////////////////////////////////
/*
# Exporting Component Description of CoretxM1_0 to TCL
# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component CoretxM1_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CORECORTEXM1:4.0.100} -component_name {CoretxM1_0} -params {\
"DEBUG_IF:0"  \
"DEBUG_INCL:true"  \
"ENABLE_ECC:false"  \
"INCL_RESET_CTRL:true"  \
"NUM_IRQ_TOP:32"  \
"USE_BFM:false"   }
# Exporting Component Description of CoretxM1_0 to TCL done
*/

// CoretxM1_0
module CoretxM1_0(
    // Inputs
    DBGRESETN,
    DBGRESTART,
    EDBGRQ,
    HCLK,
    HRDATA,
    HREADY,
    HRESP,
    IRQ0,
    IRQ1,
    IRQ10,
    IRQ11,
    IRQ12,
    IRQ13,
    IRQ14,
    IRQ15,
    IRQ16,
    IRQ17,
    IRQ18,
    IRQ19,
    IRQ2,
    IRQ20,
    IRQ21,
    IRQ22,
    IRQ23,
    IRQ24,
    IRQ25,
    IRQ26,
    IRQ27,
    IRQ28,
    IRQ29,
    IRQ3,
    IRQ30,
    IRQ31,
    IRQ4,
    IRQ5,
    IRQ6,
    IRQ7,
    IRQ8,
    IRQ9,
    NMI,
    NRESET,
    NTRST,
    SWCLKTCK,
    SWDITMS,
    SYSRESETN,
    TDI,
    WDOGRES,
    // Outputs
    DBGRESTARTED,
    HADDR,
    HALTED,
    HBURST,
    HMASTLOCK,
    HPROT,
    HRESETN,
    HSIZE,
    HTRANS,
    HWDATA,
    HWRITE,
    JTAGTOP,
    LOCKUP,
    SYSRESETREQ,
    TDO,
    WDOGRESN
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input         DBGRESETN;
input         DBGRESTART;
input         EDBGRQ;
input         HCLK;
input  [31:0] HRDATA;
input         HREADY;
input  [1:0]  HRESP;
input         IRQ0;
input         IRQ1;
input         IRQ10;
input         IRQ11;
input         IRQ12;
input         IRQ13;
input         IRQ14;
input         IRQ15;
input         IRQ16;
input         IRQ17;
input         IRQ18;
input         IRQ19;
input         IRQ2;
input         IRQ20;
input         IRQ21;
input         IRQ22;
input         IRQ23;
input         IRQ24;
input         IRQ25;
input         IRQ26;
input         IRQ27;
input         IRQ28;
input         IRQ29;
input         IRQ3;
input         IRQ30;
input         IRQ31;
input         IRQ4;
input         IRQ5;
input         IRQ6;
input         IRQ7;
input         IRQ8;
input         IRQ9;
input         NMI;
input         NRESET;
input         NTRST;
input         SWCLKTCK;
input         SWDITMS;
input         SYSRESETN;
input         TDI;
input         WDOGRES;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output        DBGRESTARTED;
output [31:0] HADDR;
output        HALTED;
output [2:0]  HBURST;
output        HMASTLOCK;
output [3:0]  HPROT;
output        HRESETN;
output [2:0]  HSIZE;
output [1:0]  HTRANS;
output [31:0] HWDATA;
output        HWRITE;
output        JTAGTOP;
output        LOCKUP;
output        SYSRESETREQ;
output        TDO;
output        WDOGRESN;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] AHB_MASTER_HADDR;
wire   [2:0]  AHB_MASTER_HBURST;
wire          AHB_MASTER_HLOCK;
wire   [3:0]  AHB_MASTER_HPROT;
wire   [31:0] HRDATA;
wire          HREADY;
wire   [1:0]  HRESP;
wire   [2:0]  AHB_MASTER_HSIZE;
wire   [1:0]  AHB_MASTER_HTRANS;
wire   [31:0] AHB_MASTER_HWDATA;
wire          AHB_MASTER_HWRITE;
wire          DBGRESETN;
wire          DBGRESTART;
wire          DBGRESTARTED_net_0;
wire          EDBGRQ;
wire          HALTED_net_0;
wire          HCLK;
wire          HRESETN_net_0;
wire          IRQ0;
wire          IRQ1;
wire          IRQ2;
wire          IRQ3;
wire          IRQ4;
wire          IRQ5;
wire          IRQ6;
wire          IRQ7;
wire          IRQ8;
wire          IRQ9;
wire          IRQ10;
wire          IRQ11;
wire          IRQ12;
wire          IRQ13;
wire          IRQ14;
wire          IRQ15;
wire          IRQ16;
wire          IRQ17;
wire          IRQ18;
wire          IRQ19;
wire          IRQ20;
wire          IRQ21;
wire          IRQ22;
wire          IRQ23;
wire          IRQ24;
wire          IRQ25;
wire          IRQ26;
wire          IRQ27;
wire          IRQ28;
wire          IRQ29;
wire          IRQ30;
wire          IRQ31;
wire          JTAGTOP_net_0;
wire          LOCKUP_net_0;
wire          NMI;
wire          NRESET;
wire          NTRST;
wire          SWCLKTCK;
wire          SWDITMS;
wire          SYSRESETN;
wire          SYSRESETREQ_net_0;
wire          TDI;
wire          TDO_net_0;
wire          WDOGRES;
wire          WDOGRESN_net_0;
wire          HRESETN_net_1;
wire          WDOGRESN_net_1;
wire          LOCKUP_net_1;
wire          HALTED_net_1;
wire          SYSRESETREQ_net_1;
wire          JTAGTOP_net_1;
wire          DBGRESTARTED_net_1;
wire   [31:0] AHB_MASTER_HADDR_net_0;
wire   [2:0]  AHB_MASTER_HBURST_net_0;
wire          AHB_MASTER_HLOCK_net_0;
wire   [3:0]  AHB_MASTER_HPROT_net_0;
wire   [2:0]  AHB_MASTER_HSIZE_net_0;
wire   [1:0]  AHB_MASTER_HTRANS_net_0;
wire   [31:0] AHB_MASTER_HWDATA_net_0;
wire          AHB_MASTER_HWRITE_net_0;
wire          TDO_net_1;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign HRESETN_net_1           = HRESETN_net_0;
assign HRESETN                 = HRESETN_net_1;
assign WDOGRESN_net_1          = WDOGRESN_net_0;
assign WDOGRESN                = WDOGRESN_net_1;
assign LOCKUP_net_1            = LOCKUP_net_0;
assign LOCKUP                  = LOCKUP_net_1;
assign HALTED_net_1            = HALTED_net_0;
assign HALTED                  = HALTED_net_1;
assign SYSRESETREQ_net_1       = SYSRESETREQ_net_0;
assign SYSRESETREQ             = SYSRESETREQ_net_1;
assign JTAGTOP_net_1           = JTAGTOP_net_0;
assign JTAGTOP                 = JTAGTOP_net_1;
assign DBGRESTARTED_net_1      = DBGRESTARTED_net_0;
assign DBGRESTARTED            = DBGRESTARTED_net_1;
assign AHB_MASTER_HADDR_net_0  = AHB_MASTER_HADDR;
assign HADDR[31:0]             = AHB_MASTER_HADDR_net_0;
assign AHB_MASTER_HBURST_net_0 = AHB_MASTER_HBURST;
assign HBURST[2:0]             = AHB_MASTER_HBURST_net_0;
assign AHB_MASTER_HLOCK_net_0  = AHB_MASTER_HLOCK;
assign HMASTLOCK               = AHB_MASTER_HLOCK_net_0;
assign AHB_MASTER_HPROT_net_0  = AHB_MASTER_HPROT;
assign HPROT[3:0]              = AHB_MASTER_HPROT_net_0;
assign AHB_MASTER_HSIZE_net_0  = AHB_MASTER_HSIZE;
assign HSIZE[2:0]              = AHB_MASTER_HSIZE_net_0;
assign AHB_MASTER_HTRANS_net_0 = AHB_MASTER_HTRANS;
assign HTRANS[1:0]             = AHB_MASTER_HTRANS_net_0;
assign AHB_MASTER_HWDATA_net_0 = AHB_MASTER_HWDATA;
assign HWDATA[31:0]            = AHB_MASTER_HWDATA_net_0;
assign AHB_MASTER_HWRITE_net_0 = AHB_MASTER_HWRITE;
assign HWRITE                  = AHB_MASTER_HWRITE_net_0;
assign TDO_net_1               = TDO_net_0;
assign TDO                     = TDO_net_1;
//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------CORECORTEXM1   -   Actel:DirectCore:CORECORTEXM1:4.0.100
CORECORTEXM1 #( 
        .DEBUG_IF        ( 0 ),
        .DEBUG_INCL      ( 1 ),
        .ENABLE_ECC      ( 0 ),
        .FAMILY          ( 26 ),
        .INCL_RESET_CTRL ( 1 ),
        .NUM_IRQ_TOP     ( 32 ),
        .USE_BFM         ( 0 ) )
CoretxM1_0_0(
        // Inputs
        .HCLK         ( HCLK ),
        .SYSRESETN    ( SYSRESETN ),
        .DBGRESETN    ( DBGRESETN ),
        .NRESET       ( NRESET ),
        .WDOGRES      ( WDOGRES ),
        .NMI          ( NMI ),
        .IRQ31        ( IRQ31 ),
        .IRQ30        ( IRQ30 ),
        .IRQ29        ( IRQ29 ),
        .IRQ28        ( IRQ28 ),
        .IRQ27        ( IRQ27 ),
        .IRQ26        ( IRQ26 ),
        .IRQ25        ( IRQ25 ),
        .IRQ24        ( IRQ24 ),
        .IRQ23        ( IRQ23 ),
        .IRQ22        ( IRQ22 ),
        .IRQ21        ( IRQ21 ),
        .IRQ20        ( IRQ20 ),
        .IRQ19        ( IRQ19 ),
        .IRQ18        ( IRQ18 ),
        .IRQ17        ( IRQ17 ),
        .IRQ16        ( IRQ16 ),
        .IRQ15        ( IRQ15 ),
        .IRQ14        ( IRQ14 ),
        .IRQ13        ( IRQ13 ),
        .IRQ12        ( IRQ12 ),
        .IRQ11        ( IRQ11 ),
        .IRQ10        ( IRQ10 ),
        .IRQ9         ( IRQ9 ),
        .IRQ8         ( IRQ8 ),
        .IRQ7         ( IRQ7 ),
        .IRQ6         ( IRQ6 ),
        .IRQ5         ( IRQ5 ),
        .IRQ4         ( IRQ4 ),
        .IRQ3         ( IRQ3 ),
        .IRQ2         ( IRQ2 ),
        .IRQ1         ( IRQ1 ),
        .IRQ0         ( IRQ0 ),
        .HRDATA       ( HRDATA ),
        .HREADY       ( HREADY ),
        .HRESP        ( HRESP ),
        .EDBGRQ       ( EDBGRQ ),
        .DBGRESTART   ( DBGRESTART ),
        .SWCLKTCK     ( SWCLKTCK ),
        .NTRST        ( NTRST ),
        .SWDITMS      ( SWDITMS ),
        .TDI          ( TDI ),
        // Outputs
        .HRESETN      ( HRESETN_net_0 ),
        .WDOGRESN     ( WDOGRESN_net_0 ),
        .LOCKUP       ( LOCKUP_net_0 ),
        .HALTED       ( HALTED_net_0 ),
        .SYSRESETREQ  ( SYSRESETREQ_net_0 ),
        .HADDR        ( AHB_MASTER_HADDR ),
        .HBURST       ( AHB_MASTER_HBURST ),
        .HPROT        ( AHB_MASTER_HPROT ),
        .HSIZE        ( AHB_MASTER_HSIZE ),
        .HTRANS       ( AHB_MASTER_HTRANS ),
        .HWDATA       ( AHB_MASTER_HWDATA ),
        .HWRITE       ( AHB_MASTER_HWRITE ),
        .HMASTLOCK    ( AHB_MASTER_HLOCK ),
        .JTAGTOP      ( JTAGTOP_net_0 ),
        .JTAGNSW      (  ),
        .DBGRESTARTED ( DBGRESTARTED_net_0 ),
        .SWDO         (  ),
        .SWDOEN       (  ),
        .NTDOEN       (  ),
        .TDO          ( TDO_net_0 ) 
        );


endmodule
