//////////////////////////////////////////////////////////////////////
// Created by SmartDesign Mon Jan 11 21:09:35 2021
// Version: v12.6 12.900.20.24
//////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps

// top
module top(
    // Inputs
    NTRST,
    REF_CLK_0,
    RESETN,
    RX,
    SWCLKTCK,
    SWDITMS,
    TDI,
    // Outputs
    GPIO_OUT,
    TDO,
    TX
);

//--------------------------------------------------------------------
// Input
//--------------------------------------------------------------------
input        NTRST;
input        REF_CLK_0;
input        RESETN;
input        RX;
input        SWCLKTCK;
input        SWDITMS;
input        TDI;
//--------------------------------------------------------------------
// Output
//--------------------------------------------------------------------
output [3:0] GPIO_OUT;
output       TDO;
output       TX;
//--------------------------------------------------------------------
// Nets
//--------------------------------------------------------------------
wire   [31:0] core_ahb_to_apb3_0_APBmaster_PADDR;
wire          core_ahb_to_apb3_0_APBmaster_PENABLE;
wire   [31:0] core_ahb_to_apb3_0_APBmaster_PRDATA;
wire          core_ahb_to_apb3_0_APBmaster_PREADY;
wire          core_ahb_to_apb3_0_APBmaster_PSELx;
wire          core_ahb_to_apb3_0_APBmaster_PSLVERR;
wire   [31:0] core_ahb_to_apb3_0_APBmaster_PWDATA;
wire          core_ahb_to_apb3_0_APBmaster_PWRITE;
wire   [31:0] coreahblite_0_0_AHBmslave0_HADDR;
wire   [2:0]  coreahblite_0_0_AHBmslave0_HBURST;
wire          coreahblite_0_0_AHBmslave0_HMASTLOCK;
wire   [3:0]  coreahblite_0_0_AHBmslave0_HPROT;
wire   [31:0] coreahblite_0_0_AHBmslave0_HRDATA;
wire          coreahblite_0_0_AHBmslave0_HREADY;
wire          coreahblite_0_0_AHBmslave0_HREADYOUT;
wire   [1:0]  coreahblite_0_0_AHBmslave0_HRESP;
wire          coreahblite_0_0_AHBmslave0_HSELx;
wire   [2:0]  coreahblite_0_0_AHBmslave0_HSIZE;
wire   [1:0]  coreahblite_0_0_AHBmslave0_HTRANS;
wire   [31:0] coreahblite_0_0_AHBmslave0_HWDATA;
wire          coreahblite_0_0_AHBmslave0_HWRITE;
wire   [31:0] coreahblite_0_0_AHBmslave4_HADDR;
wire   [2:0]  coreahblite_0_0_AHBmslave4_HBURST;
wire          coreahblite_0_0_AHBmslave4_HMASTLOCK;
wire   [3:0]  coreahblite_0_0_AHBmslave4_HPROT;
wire   [31:0] coreahblite_0_0_AHBmslave4_HRDATA;
wire          coreahblite_0_0_AHBmslave4_HREADY;
wire          coreahblite_0_0_AHBmslave4_HREADYOUT;
wire   [1:0]  coreahblite_0_0_AHBmslave4_HRESP;
wire          coreahblite_0_0_AHBmslave4_HSELx;
wire   [2:0]  coreahblite_0_0_AHBmslave4_HSIZE;
wire   [1:0]  coreahblite_0_0_AHBmslave4_HTRANS;
wire   [31:0] coreahblite_0_0_AHBmslave4_HWDATA;
wire          coreahblite_0_0_AHBmslave4_HWRITE;
wire          CoreAPB3_0_0_APBmslave0_PENABLE;
wire   [31:0] CoreAPB3_0_0_APBmslave0_PRDATA;
wire          CoreAPB3_0_0_APBmslave0_PREADY;
wire          CoreAPB3_0_0_APBmslave0_PSELx;
wire          CoreAPB3_0_0_APBmslave0_PSLVERR;
wire          CoreAPB3_0_0_APBmslave0_PWRITE;
wire          CoreAPB3_0_0_APBmslave1_PREADY;
wire          CoreAPB3_0_0_APBmslave1_PSELx;
wire          CoreAPB3_0_0_APBmslave1_PSLVERR;
wire   [31:0] CoretxM1_0_0_AHB_MASTER_HADDR;
wire   [2:0]  CoretxM1_0_0_AHB_MASTER_HBURST;
wire          CoretxM1_0_0_AHB_MASTER_HLOCK;
wire   [3:0]  CoretxM1_0_0_AHB_MASTER_HPROT;
wire   [31:0] CoretxM1_0_0_AHB_MASTER_HRDATA;
wire          CoretxM1_0_0_AHB_MASTER_HREADY;
wire   [1:0]  CoretxM1_0_0_AHB_MASTER_HRESP;
wire   [2:0]  CoretxM1_0_0_AHB_MASTER_HSIZE;
wire   [1:0]  CoretxM1_0_0_AHB_MASTER_HTRANS;
wire   [31:0] CoretxM1_0_0_AHB_MASTER_HWDATA;
wire          CoretxM1_0_0_AHB_MASTER_HWRITE;
wire          CoretxM1_0_0_HRESETN;
wire   [3:0]  GPIO_OUT_net_0;
wire          NTRST;
wire          PF_CCC_0_0_OUT0_FABCLK_0;
wire          PF_CCC_0_0_PLL_LOCK_0;
wire          PF_INIT_MONITOR_0_0_BANK_6_VDDI_STATUS;
wire          PF_INIT_MONITOR_0_0_DEVICE_INIT_DONE;
wire          PF_INIT_MONITOR_0_0_FABRIC_POR_N;
wire          pf_reset_0_FABRIC_RESET_N;
wire          pf_reset_0_PLL_POWERDOWN_B;
wire          REF_CLK_0;
wire          RESETN;
wire          RX;
wire          SWCLKTCK;
wire          SWDITMS;
wire          TDI;
wire          TDO_net_0;
wire          TX_net_0;
wire          TDO_net_1;
wire          TX_net_1;
wire   [3:0]  GPIO_OUT_net_1;
//--------------------------------------------------------------------
// TiedOff Nets
//--------------------------------------------------------------------
wire          GND_net;
wire   [3:0]  GPIO_IN_const_net_0;
//--------------------------------------------------------------------
// Bus Interface Nets Declarations - Unequal Pin Widths
//--------------------------------------------------------------------
wire   [4:0]  CoreAPB3_0_0_APBmslave0_PADDR_1_4to0;
wire   [4:0]  CoreAPB3_0_0_APBmslave0_PADDR_1;
wire   [7:0]  CoreAPB3_0_0_APBmslave0_PADDR_0_7to0;
wire   [7:0]  CoreAPB3_0_0_APBmslave0_PADDR_0;
wire   [31:0] CoreAPB3_0_0_APBmslave0_PADDR;
wire   [7:0]  CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0;
wire   [7:0]  CoreAPB3_0_0_APBmslave0_PWDATA_0;
wire   [31:0] CoreAPB3_0_0_APBmslave0_PWDATA;
wire   [7:0]  CoreAPB3_0_0_APBmslave1_PRDATA;
wire   [31:8] CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8;
wire   [7:0]  CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0;
wire   [31:0] CoreAPB3_0_0_APBmslave1_PRDATA_0;
//--------------------------------------------------------------------
// Constant assignments
//--------------------------------------------------------------------
assign GND_net             = 1'b0;
assign GPIO_IN_const_net_0 = 4'h0;
//--------------------------------------------------------------------
// Top level output port assignments
//--------------------------------------------------------------------
assign TDO_net_1      = TDO_net_0;
assign TDO            = TDO_net_1;
assign TX_net_1       = TX_net_0;
assign TX             = TX_net_1;
assign GPIO_OUT_net_1 = GPIO_OUT_net_0;
assign GPIO_OUT[3:0]  = GPIO_OUT_net_1;
//--------------------------------------------------------------------
// Bus Interface Nets Assignments - Unequal Pin Widths
//--------------------------------------------------------------------
assign CoreAPB3_0_0_APBmslave0_PADDR_1_4to0 = CoreAPB3_0_0_APBmslave0_PADDR[4:0];
assign CoreAPB3_0_0_APBmslave0_PADDR_1 = { CoreAPB3_0_0_APBmslave0_PADDR_1_4to0 };
assign CoreAPB3_0_0_APBmslave0_PADDR_0_7to0 = CoreAPB3_0_0_APBmslave0_PADDR[7:0];
assign CoreAPB3_0_0_APBmslave0_PADDR_0 = { CoreAPB3_0_0_APBmslave0_PADDR_0_7to0 };

assign CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0 = CoreAPB3_0_0_APBmslave0_PWDATA[7:0];
assign CoreAPB3_0_0_APBmslave0_PWDATA_0 = { CoreAPB3_0_0_APBmslave0_PWDATA_0_7to0 };

assign CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8 = 24'h0;
assign CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0 = CoreAPB3_0_0_APBmslave1_PRDATA[7:0];
assign CoreAPB3_0_0_APBmslave1_PRDATA_0 = { CoreAPB3_0_0_APBmslave1_PRDATA_0_31to8, CoreAPB3_0_0_APBmslave1_PRDATA_0_7to0 };

//--------------------------------------------------------------------
// Component instances
//--------------------------------------------------------------------
//--------core_ahb_to_apb3
core_ahb_to_apb3 core_ahb_to_apb3_0(
        // Inputs
        .HCLK      ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .HRESETN   ( CoretxM1_0_0_HRESETN ),
        .HWRITE    ( coreahblite_0_0_AHBmslave4_HWRITE ),
        .HSEL      ( coreahblite_0_0_AHBmslave4_HSELx ),
        .HREADY    ( coreahblite_0_0_AHBmslave4_HREADY ),
        .PREADY    ( core_ahb_to_apb3_0_APBmaster_PREADY ),
        .PSLVERR   ( core_ahb_to_apb3_0_APBmaster_PSLVERR ),
        .HADDR     ( coreahblite_0_0_AHBmslave4_HADDR ),
        .HTRANS    ( coreahblite_0_0_AHBmslave4_HTRANS ),
        .HWDATA    ( coreahblite_0_0_AHBmslave4_HWDATA ),
        .PRDATA    ( core_ahb_to_apb3_0_APBmaster_PRDATA ),
        // Outputs
        .HREADYOUT ( coreahblite_0_0_AHBmslave4_HREADYOUT ),
        .PSEL      ( core_ahb_to_apb3_0_APBmaster_PSELx ),
        .PENABLE   ( core_ahb_to_apb3_0_APBmaster_PENABLE ),
        .PWRITE    ( core_ahb_to_apb3_0_APBmaster_PWRITE ),
        .HRDATA    ( coreahblite_0_0_AHBmslave4_HRDATA ),
        .HRESP     ( coreahblite_0_0_AHBmslave4_HRESP ),
        .PADDR     ( core_ahb_to_apb3_0_APBmaster_PADDR ),
        .PWDATA    ( core_ahb_to_apb3_0_APBmaster_PWDATA ) 
        );

//--------coreahblite_0
coreahblite_0 coreahblite_0_0(
        // Inputs
        .HCLK         ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .HRESETN      ( CoretxM1_0_0_HRESETN ),
        .REMAP_M0     ( GND_net ),
        .HWRITE_M0    ( CoretxM1_0_0_AHB_MASTER_HWRITE ),
        .HMASTLOCK_M0 ( CoretxM1_0_0_AHB_MASTER_HLOCK ),
        .HREADYOUT_S0 ( coreahblite_0_0_AHBmslave0_HREADYOUT ),
        .HREADYOUT_S4 ( coreahblite_0_0_AHBmslave4_HREADYOUT ),
        .HADDR_M0     ( CoretxM1_0_0_AHB_MASTER_HADDR ),
        .HTRANS_M0    ( CoretxM1_0_0_AHB_MASTER_HTRANS ),
        .HSIZE_M0     ( CoretxM1_0_0_AHB_MASTER_HSIZE ),
        .HBURST_M0    ( CoretxM1_0_0_AHB_MASTER_HBURST ),
        .HPROT_M0     ( CoretxM1_0_0_AHB_MASTER_HPROT ),
        .HWDATA_M0    ( CoretxM1_0_0_AHB_MASTER_HWDATA ),
        .HRDATA_S0    ( coreahblite_0_0_AHBmslave0_HRDATA ),
        .HRESP_S0     ( coreahblite_0_0_AHBmslave0_HRESP ),
        .HRDATA_S4    ( coreahblite_0_0_AHBmslave4_HRDATA ),
        .HRESP_S4     ( coreahblite_0_0_AHBmslave4_HRESP ),
        // Outputs
        .HREADY_M0    ( CoretxM1_0_0_AHB_MASTER_HREADY ),
        .HWRITE_S0    ( coreahblite_0_0_AHBmslave0_HWRITE ),
        .HSEL_S0      ( coreahblite_0_0_AHBmslave0_HSELx ),
        .HREADY_S0    ( coreahblite_0_0_AHBmslave0_HREADY ),
        .HMASTLOCK_S0 ( coreahblite_0_0_AHBmslave0_HMASTLOCK ),
        .HWRITE_S4    ( coreahblite_0_0_AHBmslave4_HWRITE ),
        .HSEL_S4      ( coreahblite_0_0_AHBmslave4_HSELx ),
        .HREADY_S4    ( coreahblite_0_0_AHBmslave4_HREADY ),
        .HMASTLOCK_S4 ( coreahblite_0_0_AHBmslave4_HMASTLOCK ),
        .HRDATA_M0    ( CoretxM1_0_0_AHB_MASTER_HRDATA ),
        .HRESP_M0     ( CoretxM1_0_0_AHB_MASTER_HRESP ),
        .HADDR_S0     ( coreahblite_0_0_AHBmslave0_HADDR ),
        .HTRANS_S0    ( coreahblite_0_0_AHBmslave0_HTRANS ),
        .HSIZE_S0     ( coreahblite_0_0_AHBmslave0_HSIZE ),
        .HWDATA_S0    ( coreahblite_0_0_AHBmslave0_HWDATA ),
        .HBURST_S0    ( coreahblite_0_0_AHBmslave0_HBURST ),
        .HPROT_S0     ( coreahblite_0_0_AHBmslave0_HPROT ),
        .HADDR_S4     ( coreahblite_0_0_AHBmslave4_HADDR ),
        .HTRANS_S4    ( coreahblite_0_0_AHBmslave4_HTRANS ),
        .HSIZE_S4     ( coreahblite_0_0_AHBmslave4_HSIZE ),
        .HWDATA_S4    ( coreahblite_0_0_AHBmslave4_HWDATA ),
        .HBURST_S4    ( coreahblite_0_0_AHBmslave4_HBURST ),
        .HPROT_S4     ( coreahblite_0_0_AHBmslave4_HPROT ) 
        );

//--------CoreAPB3_0
CoreAPB3_0 CoreAPB3_0_0(
        // Inputs
        .PSEL      ( core_ahb_to_apb3_0_APBmaster_PSELx ),
        .PENABLE   ( core_ahb_to_apb3_0_APBmaster_PENABLE ),
        .PWRITE    ( core_ahb_to_apb3_0_APBmaster_PWRITE ),
        .PREADYS0  ( CoreAPB3_0_0_APBmslave0_PREADY ),
        .PSLVERRS0 ( CoreAPB3_0_0_APBmslave0_PSLVERR ),
        .PREADYS1  ( CoreAPB3_0_0_APBmslave1_PREADY ),
        .PSLVERRS1 ( CoreAPB3_0_0_APBmslave1_PSLVERR ),
        .PADDR     ( core_ahb_to_apb3_0_APBmaster_PADDR ),
        .PWDATA    ( core_ahb_to_apb3_0_APBmaster_PWDATA ),
        .PRDATAS0  ( CoreAPB3_0_0_APBmslave0_PRDATA ),
        .PRDATAS1  ( CoreAPB3_0_0_APBmslave1_PRDATA_0 ),
        // Outputs
        .PREADY    ( core_ahb_to_apb3_0_APBmaster_PREADY ),
        .PSLVERR   ( core_ahb_to_apb3_0_APBmaster_PSLVERR ),
        .PSELS0    ( CoreAPB3_0_0_APBmslave0_PSELx ),
        .PENABLES  ( CoreAPB3_0_0_APBmslave0_PENABLE ),
        .PWRITES   ( CoreAPB3_0_0_APBmslave0_PWRITE ),
        .PSELS1    ( CoreAPB3_0_0_APBmslave1_PSELx ),
        .PRDATA    ( core_ahb_to_apb3_0_APBmaster_PRDATA ),
        .PADDRS    ( CoreAPB3_0_0_APBmslave0_PADDR ),
        .PWDATAS   ( CoreAPB3_0_0_APBmslave0_PWDATA ) 
        );

//--------CoreGPIO_0
CoreGPIO_0 CoreGPIO_0_0(
        // Inputs
        .PRESETN  ( CoretxM1_0_0_HRESETN ),
        .PCLK     ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .PSEL     ( CoreAPB3_0_0_APBmslave0_PSELx ),
        .PENABLE  ( CoreAPB3_0_0_APBmslave0_PENABLE ),
        .PWRITE   ( CoreAPB3_0_0_APBmslave0_PWRITE ),
        .PADDR    ( CoreAPB3_0_0_APBmslave0_PADDR_0 ),
        .PWDATA   ( CoreAPB3_0_0_APBmslave0_PWDATA ),
        .GPIO_IN  ( GPIO_IN_const_net_0 ),
        // Outputs
        .PREADY   ( CoreAPB3_0_0_APBmslave0_PREADY ),
        .PSLVERR  ( CoreAPB3_0_0_APBmslave0_PSLVERR ),
        .PRDATA   ( CoreAPB3_0_0_APBmslave0_PRDATA ),
        .INT      (  ),
        .GPIO_OUT ( GPIO_OUT_net_0 ) 
        );

//--------CoretxM1_0
CoretxM1_0 CoretxM1_0_0(
        // Inputs
        .HCLK         ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .SYSRESETN    ( pf_reset_0_FABRIC_RESET_N ),
        .DBGRESETN    ( pf_reset_0_FABRIC_RESET_N ),
        .NRESET       ( pf_reset_0_FABRIC_RESET_N ),
        .WDOGRES      ( GND_net ),
        .NMI          ( GND_net ),
        .IRQ31        ( GND_net ),
        .IRQ30        ( GND_net ),
        .IRQ29        ( GND_net ),
        .IRQ28        ( GND_net ),
        .IRQ27        ( GND_net ),
        .IRQ26        ( GND_net ),
        .IRQ25        ( GND_net ),
        .IRQ24        ( GND_net ),
        .IRQ23        ( GND_net ),
        .IRQ22        ( GND_net ),
        .IRQ21        ( GND_net ),
        .IRQ20        ( GND_net ),
        .IRQ19        ( GND_net ),
        .IRQ18        ( GND_net ),
        .IRQ17        ( GND_net ),
        .IRQ16        ( GND_net ),
        .IRQ15        ( GND_net ),
        .IRQ14        ( GND_net ),
        .IRQ13        ( GND_net ),
        .IRQ12        ( GND_net ),
        .IRQ11        ( GND_net ),
        .IRQ10        ( GND_net ),
        .IRQ9         ( GND_net ),
        .IRQ8         ( GND_net ),
        .IRQ7         ( GND_net ),
        .IRQ6         ( GND_net ),
        .IRQ5         ( GND_net ),
        .IRQ4         ( GND_net ),
        .IRQ3         ( GND_net ),
        .IRQ2         ( GND_net ),
        .IRQ1         ( GND_net ),
        .IRQ0         ( GND_net ),
        .EDBGRQ       ( GND_net ),
        .DBGRESTART   ( GND_net ),
        .HREADY       ( CoretxM1_0_0_AHB_MASTER_HREADY ),
        .SWCLKTCK     ( SWCLKTCK ),
        .NTRST        ( NTRST ),
        .SWDITMS      ( SWDITMS ),
        .TDI          ( TDI ),
        .HRDATA       ( CoretxM1_0_0_AHB_MASTER_HRDATA ),
        .HRESP        ( CoretxM1_0_0_AHB_MASTER_HRESP ),
        // Outputs
        .HRESETN      ( CoretxM1_0_0_HRESETN ),
        .WDOGRESN     (  ),
        .LOCKUP       (  ),
        .HALTED       (  ),
        .SYSRESETREQ  (  ),
        .JTAGTOP      (  ),
        .DBGRESTARTED (  ),
        .HMASTLOCK    ( CoretxM1_0_0_AHB_MASTER_HLOCK ),
        .HWRITE       ( CoretxM1_0_0_AHB_MASTER_HWRITE ),
        .TDO          ( TDO_net_0 ),
        .HADDR        ( CoretxM1_0_0_AHB_MASTER_HADDR ),
        .HBURST       ( CoretxM1_0_0_AHB_MASTER_HBURST ),
        .HPROT        ( CoretxM1_0_0_AHB_MASTER_HPROT ),
        .HSIZE        ( CoretxM1_0_0_AHB_MASTER_HSIZE ),
        .HTRANS       ( CoretxM1_0_0_AHB_MASTER_HTRANS ),
        .HWDATA       ( CoretxM1_0_0_AHB_MASTER_HWDATA ) 
        );

//--------CoreUARTapb_0
CoreUARTapb_0 CoreUARTapb_0_0(
        // Inputs
        .PCLK        ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .PRESETN     ( CoretxM1_0_0_HRESETN ),
        .RX          ( RX ),
        .PSEL        ( CoreAPB3_0_0_APBmslave1_PSELx ),
        .PENABLE     ( CoreAPB3_0_0_APBmslave0_PENABLE ),
        .PWRITE      ( CoreAPB3_0_0_APBmslave0_PWRITE ),
        .PADDR       ( CoreAPB3_0_0_APBmslave0_PADDR_1 ),
        .PWDATA      ( CoreAPB3_0_0_APBmslave0_PWDATA_0 ),
        // Outputs
        .TXRDY       (  ),
        .RXRDY       (  ),
        .PARITY_ERR  (  ),
        .OVERFLOW    (  ),
        .TX          ( TX_net_0 ),
        .FRAMING_ERR (  ),
        .PREADY      ( CoreAPB3_0_0_APBmslave1_PREADY ),
        .PSLVERR     ( CoreAPB3_0_0_APBmslave1_PSLVERR ),
        .PRDATA      ( CoreAPB3_0_0_APBmslave1_PRDATA ) 
        );

//--------PF_CCC_0
PF_CCC_0 PF_CCC_0_0(
        // Inputs
        .REF_CLK_0         ( REF_CLK_0 ),
        .PLL_POWERDOWN_N_0 ( pf_reset_0_PLL_POWERDOWN_B ),
        // Outputs
        .OUT0_FABCLK_0     ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .PLL_LOCK_0        ( PF_CCC_0_0_PLL_LOCK_0 ) 
        );

//--------PF_INIT_MONITOR_0
PF_INIT_MONITOR_0 PF_INIT_MONITOR_0_0(
        // Outputs
        .FABRIC_POR_N               ( PF_INIT_MONITOR_0_0_FABRIC_POR_N ),
        .PCIE_INIT_DONE             (  ),
        .USRAM_INIT_DONE            (  ),
        .SRAM_INIT_DONE             (  ),
        .DEVICE_INIT_DONE           ( PF_INIT_MONITOR_0_0_DEVICE_INIT_DONE ),
        .XCVR_INIT_DONE             (  ),
        .USRAM_INIT_FROM_SNVM_DONE  (  ),
        .USRAM_INIT_FROM_UPROM_DONE (  ),
        .USRAM_INIT_FROM_SPI_DONE   (  ),
        .SRAM_INIT_FROM_SNVM_DONE   (  ),
        .SRAM_INIT_FROM_UPROM_DONE  (  ),
        .SRAM_INIT_FROM_SPI_DONE    (  ),
        .AUTOCALIB_DONE             (  ),
        .BANK_6_VDDI_STATUS         ( PF_INIT_MONITOR_0_0_BANK_6_VDDI_STATUS ) 
        );

//--------pf_reset
pf_reset pf_reset_0(
        // Inputs
        .CLK                ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .EXT_RST_N          ( RESETN ),
        .BANK_x_VDDI_STATUS ( PF_INIT_MONITOR_0_0_BANK_6_VDDI_STATUS ),
        .BANK_y_VDDI_STATUS ( PF_INIT_MONITOR_0_0_BANK_6_VDDI_STATUS ),
        .PLL_LOCK           ( PF_CCC_0_0_PLL_LOCK_0 ),
        .SS_BUSY            ( GND_net ),
        .INIT_DONE          ( PF_INIT_MONITOR_0_0_DEVICE_INIT_DONE ),
        .FF_US_RESTORE      ( GND_net ),
        .FPGA_POR_N         ( PF_INIT_MONITOR_0_0_FABRIC_POR_N ),
        // Outputs
        .PLL_POWERDOWN_B    ( pf_reset_0_PLL_POWERDOWN_B ),
        .FABRIC_RESET_N     ( pf_reset_0_FABRIC_RESET_N ) 
        );

//--------PF_SRAM
PF_SRAM PF_SRAM_0(
        // Inputs
        .HCLK      ( PF_CCC_0_0_OUT0_FABCLK_0 ),
        .HRESETN   ( CoretxM1_0_0_HRESETN ),
        .HWRITE    ( coreahblite_0_0_AHBmslave0_HWRITE ),
        .HSEL      ( coreahblite_0_0_AHBmslave0_HSELx ),
        .HREADYIN  ( coreahblite_0_0_AHBmslave0_HREADY ),
        .HADDR     ( coreahblite_0_0_AHBmslave0_HADDR ),
        .HTRANS    ( coreahblite_0_0_AHBmslave0_HTRANS ),
        .HSIZE     ( coreahblite_0_0_AHBmslave0_HSIZE ),
        .HBURST    ( coreahblite_0_0_AHBmslave0_HBURST ),
        .HWDATA    ( coreahblite_0_0_AHBmslave0_HWDATA ),
        // Outputs
        .HREADYOUT ( coreahblite_0_0_AHBmslave0_HREADYOUT ),
        .HRDATA    ( coreahblite_0_0_AHBmslave0_HRDATA ),
        .HRESP     ( coreahblite_0_0_AHBmslave0_HRESP ) 
        );


endmodule
