#==================================================================================
# // PF VIDEO Kit VKPFC2RXSDI12G demo Libero design
#
# // Check Libero version and path lenth to verify project can be created
#==================================================================================
if {[string compare [string range [get_libero_version] 0 end-4] "2023.1"]==0} {
	puts "Libero v2023.1 detected."
} else {
	error "Incorrect Libero version. Please use Libero v2023.1 to run these scripts."
}

if { [lindex $tcl_platform(os) 0]  == "Windows" } {
	if {[string length [pwd]] < 90} {
		puts "Project path length ok."
	} else {
		error "Path to project is too long, please reduce the path and try again."
	}
}

#==================================================================================
# // Process arguments
#==================================================================================
if { $::argc > 0 } {
    set i 1
    foreach arg $::argv {
        if {[string match "*:*" $arg]} {
            set temp [split $arg ":"]
            puts "Setting parameter [lindex $temp 0] to [lindex $temp 1]"
            set [lindex $temp 0] "[lindex $temp 1]"
        } else {
            set $arg 1
            puts "set $arg to 1"
        }
        incr i
    }
} else {
    puts "no command line argument passed"
}

#==================================================================================
# //Set required variables and add functions
#==================================================================================

set install_loc [defvar_get -name ACTEL_SW_DIR]
set local_dir [pwd]
set src_path ./script_support
set constraint_path ./script_support/constraint
set release_tag "2023.1"
set project_name "VKPFC2RXSDI12G"
file delete -force $project_name
set project_dir "$local_dir/$project_name"

#==================================================================================
# // Create Libero project
#==================================================================================
new_project \
		-location $project_name \
		-name $project_name \
		-project_description {} \
		-block_mode 0 \
		-standalone_peripheral_initialization 0 \
		-instantiate_in_smartdesign 1 \
		-ondemand_build_dh 1 \
		-use_relative_path 0 \
		-linked_files_root_dir_env {} \
		-hdl {VERILOG} \
		-family {PolarFire} \
		-die {MPF300TS} \
		-package {FCG1152} \
		-speed {-1} \
		-die_voltage {1.0} \
		-part_range {IND} \
		-adv_options {IO_DEFT_STD:LVCMOS 1.8V} \
		-adv_options {RESTRICTPROBEPINS:1} \
		-adv_options {RESTRICTSPIPINS:0} \
		-adv_options {SYSTEM_CONTROLLER_SUSPEND_MODE:0} \
		-adv_options {TEMPR:IND} \
		-adv_options {VCCI_1.2_VOLTR:IND} \
		-adv_options {VCCI_1.5_VOLTR:IND} \
		-adv_options {VCCI_1.8_VOLTR:IND} \
		-adv_options {VCCI_2.5_VOLTR:IND} \
		-adv_options {VCCI_3.3_VOLTR:IND} \
		-adv_options {VOLTR:IND}
		
#==================================================================================
#DirectCore
#SolutionCore
#==================================================================================
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREI2C:7.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CORERXIODBITALIGN:2.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREBCLKSCLKALIGN:2.0.111} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBLSRAM_PF:2.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREDDR_TIP:2.1.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREUART:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREUHD_SDIRX:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREUHD_SDITX:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Bayer_Interpolation:4.7.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:DDR_AXI4_ARBITER_PF:2.1.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:YCbCrtoRGB:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:RGBtoYCbCr:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:Display_Controller:4.8.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Gamma_Correction:4.3.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:HDMI_TX:5.1.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:SolutionCore:Image_Enhancement:4.4.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:mipicsi2rxdecoderPF:4.7.0} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:DirectCore:COREDDR_LITEAXI:2.0.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microchip:SolutionCore:MIPI_TRAINING_LITE:1.0.0} -location {www.microchip-ip.com/repositories/DirectCore}
#SgCore
download_core -vlnv {Actel:SgCore:PF_CCC:2.2.220} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_INIT_MONITOR:2.0.307} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_TX_PLL:2.0.302} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:PF_XCVR_REF_CLK:1.0.103} -location {www.microchip-ip.com/repositories/SgCore}
#SystemBuilder - SgCore
download_core -vlnv {Actel:SystemBuilder:PF_DDR4:2.5.111} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_IOD_GENERIC_RX:2.1.110} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_SRAM_AHBL_AXI:1.2.110} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:PF_XCVR_ERM:3.1.200} -location {www.microchip-ip.com/repositories/SgCore}

#==================================================================================
# // Sourcing the Tcl file in which all the HDL source files used in the design are imported or linked
# // Sourcing the Tcl files for creating individual ${src_path}/components under the top level
#==================================================================================
source ./script_support/design_source.tcl
build_design_hierarchy
set_root -module {VIDEO_KIT_TOP::work}

#==================================================================================
# // Derive timing constraints
#==================================================================================
derive_constraints_sdc
	
#==================================================================================
# // Import I/O constraints
#==================================================================================
import_files \
		-convert_EDN_to_HDL 0 \
		-io_pdc "${constraint_path}/io/user.pdc" \
	
set_as_target -type {io_pdc} \
		-file "${constraint_path}/io/user.pdc"
		
#==================================================================================
# // Import floor planning constraints
#==================================================================================
import_files \
		-convert_EDN_to_HDL 0 \
		-fp_pdc "${constraint_path}/fp/user.pdc" 

configure_tool -name {PLACEROUTE} \
-params {DELAY_ANALYSIS:MAX} \
-params {EFFORT_LEVEL:false} \
-params {GB_DEMOTION:true} \
-params {INCRPLACEANDROUTE:false} \
-params {IOREG_COMBINING:false} \
-params {MULTI_PASS_CRITERIA:VIOLATIONS} \
-params {MULTI_PASS_LAYOUT:false} \
-params {NUM_MULTI_PASSES:5} \
-params {PDPR:false} \
-params {RANDOM_SEED:0} \
-params {REPAIR_MIN_DELAY:true} \
-params {REPLICATION:true} \
-params {SLACK_CRITERIA:WORST_SLACK} \
-params {SPECIFIC_CLOCK:} \
-params {START_SEED_INDEX:1} \
-params {STOP_ON_FIRST_PASS:false} \
-params {TDPR:true}

set_as_target -type {fp_pdc} \
		-file "${constraint_path}/fp/user.pdc"
 
#==================================================================================
# // Import timing constraints
#==================================================================================
import_files \
		-convert_EDN_to_HDL 0 \
		-sdc "${constraint_path}/user.sdc" 
	
configure_tool -name {VERIFYTIMING} \
-params {CONSTRAINTS_COVERAGE:1} \
-params {FORMAT:XML} \
-params {MAX_EXPANDED_PATHS_TIMING:1} \
-params {MAX_EXPANDED_PATHS_VIOLATION:0} \
-params {MAX_PARALLEL_PATHS_TIMING:1} \
-params {MAX_PARALLEL_PATHS_VIOLATION:1} \
-params {MAX_PATHS_INTERACTIVE_REPORT:1000} \
-params {MAX_PATHS_TIMING:5} \
-params {MAX_PATHS_VIOLATION:20} \
-params {MAX_TIMING_FAST_HV_LT:1} \
-params {MAX_TIMING_MULTI_CORNER:1} \
-params {MAX_TIMING_SLOW_LV_HT:1} \
-params {MAX_TIMING_SLOW_LV_LT:1} \
-params {MAX_TIMING_VIOLATIONS_FAST_HV_LT:1} \
-params {MAX_TIMING_VIOLATIONS_MULTI_CORNER:1} \
-params {MAX_TIMING_VIOLATIONS_SLOW_LV_HT:1} \
-params {MAX_TIMING_VIOLATIONS_SLOW_LV_LT:1} \
-params {MIN_TIMING_FAST_HV_LT:1} \
-params {MIN_TIMING_MULTI_CORNER:1} \
-params {MIN_TIMING_SLOW_LV_HT:1} \
-params {MIN_TIMING_SLOW_LV_LT:1} \
-params {MIN_TIMING_VIOLATIONS_FAST_HV_LT:1} \
-params {MIN_TIMING_VIOLATIONS_MULTI_CORNER:1} \
-params {MIN_TIMING_VIOLATIONS_SLOW_LV_HT:1} \
-params {MIN_TIMING_VIOLATIONS_SLOW_LV_LT:1} \
-params {SLACK_THRESHOLD_VIOLATION:0.0} \
-params {SMART_INTERACTIVE:1}

set_as_target -type {sdc} \
		-file "${constraint_path}/user.sdc"

#==================================================================================
# // Associate imported constraints with the design flow
#==================================================================================
organize_tool_files -tool {SYNTHESIZE} \
		-file "${project_dir}/constraint/VIDEO_KIT_TOP_derived_constraints.sdc" \
		-file "${project_dir}/constraint/user.sdc" \
		-module {VIDEO_KIT_TOP::work} \
		-input_type {constraint}

organize_tool_files -tool {PLACEROUTE} \
		-file "${project_dir}/constraint/io/user.pdc" \
		-file "${project_dir}/constraint/VIDEO_KIT_TOP_derived_constraints.sdc" \
		-file "${project_dir}/constraint/user.sdc" \
		-file "${project_dir}/constraint/fp/user.pdc" \
		-module {VIDEO_KIT_TOP::work} \
		-input_type {constraint}
	
organize_tool_files -tool {VERIFYTIMING} \
		-file "${project_dir}/constraint/user.sdc" \
		-file "${project_dir}/constraint/VIDEO_KIT_TOP_derived_constraints.sdc" \
		-module {VIDEO_KIT_TOP::work} \
		-input_type {constraint}

set_as_target -type {io_pdc} \
		-file "${project_dir}/constraint/io/user.pdc"

save_project 

#==================================================================================
# // Executing Tools
#==================================================================================
clean_tool -name {SYNTHESIZE} 
run_tool -name {PLACEROUTE} 
run_tool -name {VERIFYTIMING}
run_tool -name {GENERATEPROGRAMMINGDATA}
configure_ram -cfg_file {script_support/configuration/memory.cfg}
update_and_run_tool -name {GENERATEPROGRAMMINGFILE}
save_project
export_prog_job \
			-job_file_name {SDI12G} \
			-export_dir {VKPFC2RXSDI12G/designer/VIDEO_KIT_TOP/export} \
			-bitstream_file_type {TRUSTED_FACILITY} \
			-bitstream_file_components {FABRIC SNVM} \
			-zeroization_likenew_action 0 \
			-zeroization_unrecoverable_action 0 \
			-program_design 1 \
			-program_spi_flash 0 \
			-include_plaintext_passkey 0 \
			-design_bitstream_format {PPD} \
			-prog_optional_procedures {} \
			-skip_recommended_procedures {} \
			-sanitize_snvm 0 
			
save_project
