# Creating SmartDesign DDR_Write
set sd_name {DDR_Write}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {data_valid_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ddr_clock_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {frame_valid_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {parallel_clk_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {reset_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {write_ackn_i} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {write_done_i} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {rdata_rdy_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {write_req_o} -port_direction {OUT}


# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {bayer_format} -port_direction {IN} -port_range {[1:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {data_i} -port_direction {IN} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {frame_ddr_addr_i} -port_direction {IN} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {beats_to_write_o} -port_direction {OUT} -port_range {[15:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {display_frame_addr_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {rdata_o} -port_direction {OUT} -port_range {[511:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {write_start_addr_o} -port_direction {OUT} -port_range {[31:0]}


# Add AND3_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND3} -instance_name {AND3_0}



# Add Bayer_Interpolation_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Bayer_Interpolation_C2} -instance_name {Bayer_Interpolation_C2_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:DATA_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:DATA_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:DATA_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:DATA_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:R_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:R_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:R_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:R_O} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:G_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:G_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:G_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:G_O} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:B_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:B_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:B_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Bayer_Interpolation_C2_0:B_O} -pin_slices {[7:0]}



# Add data_packer_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {data_packer} -hdl_file {hdl\data_packer.vhd} -instance_name {data_packer_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[47:40]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[55:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[63:56]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_0:data_i} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {data_packer_0:h_count_o}



# Add data_packer_SDI_TX_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {data_packer_SDI_TX} -hdl_file {hdl\data_packer_SDI_TX.vhd} -instance_name {data_packer_SDI_TX_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_SDI_TX_0:data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_SDI_TX_0:data_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_SDI_TX_0:data_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {data_packer_SDI_TX_0:data_o} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {data_packer_SDI_TX_0:start_ddr_w_o}



# Add DDR_write_controller_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {DDR_write_controller} -hdl_file {hdl\DDR_write_controller.vhd} -instance_name {DDR_write_controller_0}



# Add Register_Config_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {Register_Config} -instance_name {Register_Config_0}
# Exporting Parameters of instance Register_Config_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {Register_Config_0} -params {\
"G_REGISTER_WIDTH:1" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {Register_Config_0}
sd_update_instance -sd_name ${sd_name} -instance_name {Register_Config_0}



# Add RGB2YCbCr_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGB2YCbCr_C2_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_0:Cr_OUT_O}



# Add RGB2YCbCr_C2_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGB2YCbCr_C2_1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_1:DATA_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_1:Cb_OUT_O}



# Add RGB2YCbCr_C2_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGB2YCbCr_C2_2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_2:DATA_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_2:Cr_OUT_O}



# Add RGB2YCbCr_C2_3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {RGBtoYCbCr_C0} -instance_name {RGB2YCbCr_C2_3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_3:DATA_VALID_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {RGB2YCbCr_C2_3:Cb_OUT_O}



# Add video_fifo_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {video_fifo} -instance_name {video_fifo_0}
# Exporting Parameters of instance video_fifo_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {video_fifo_0} -params {\
"g_HALF_EMPTY_THRESHOLD:800" \
"g_INPUT_VIDEO_DATA_BIT_WIDTH:512" \
"g_VIDEO_FIFO_AWIDTH:10" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {video_fifo_0}
sd_update_instance -sd_name ${sd_name} -instance_name {video_fifo_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wfull_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wafull_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rdata_rdy_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:raempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rhempty_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:wdata_count_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {video_fifo_0:rdata_count_o}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:A" "Bayer_Interpolation_C2_0:RESETN_I" "DDR_write_controller_0:reset_i" "RGB2YCbCr_C2_0:RESET_N_I" "RGB2YCbCr_C2_1:RESET_N_I" "RGB2YCbCr_C2_2:RESET_N_I" "RGB2YCbCr_C2_3:RESET_N_I" "Register_Config_0:RESETN_I" "data_packer_0:reset_i" "data_packer_SDI_TX_0:reset_i" "reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:B" "data_packer_SDI_TX_0:fifo_reset_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:C" "data_packer_0:fifo_reset_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND3_0:Y" "video_fifo_0:rresetn_i" "video_fifo_0:wresetn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:DATA_VALID_I" "data_packer_SDI_TX_0:data_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:EOF_I" "data_packer_SDI_TX_0:eof_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:EOF_O" "data_packer_0:frame_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:RGB_VALID_O" "RGB2YCbCr_C2_0:DATA_VALID_I" "RGB2YCbCr_C2_1:DATA_VALID_I" "RGB2YCbCr_C2_2:DATA_VALID_I" "RGB2YCbCr_C2_3:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:SYS_CLK_I" "RGB2YCbCr_C2_0:CLOCK_I" "RGB2YCbCr_C2_1:CLOCK_I" "RGB2YCbCr_C2_2:CLOCK_I" "RGB2YCbCr_C2_3:CLOCK_I" "data_packer_0:sys_clk_i" "data_packer_SDI_TX_0:sys_clk_i" "parallel_clk_i" "video_fifo_0:wclock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:frame_valid_i" "data_packer_0:frame_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:read_fifo_o" "Register_Config_0:Data_I" "video_fifo_0:ren_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:start_i" "data_packer_0:start_ddr_w_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:sys_clk_i" "Register_Config_0:SYS_CLK_I" "ddr_clock_i" "video_fifo_0:rclock_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:write_ackn_i" "write_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:write_done_i" "write_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:write_req_o" "write_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_0:DATA_VALID_O" "data_packer_0:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Register_Config_0:Data_O" "rdata_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_0:data_valid_o" "video_fifo_0:wen_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_SDI_TX_0:data_valid_i" "data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_SDI_TX_0:frame_valid_i" "frame_valid_i" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:BAYER_FORMAT" "bayer_format" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:B_O[15:8]" "RGB2YCbCr_C2_1:BLUE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:B_O[23:16]" "RGB2YCbCr_C2_2:BLUE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:B_O[31:24]" "RGB2YCbCr_C2_3:BLUE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:B_O[7:0]" "RGB2YCbCr_C2_0:BLUE_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:DATA_I[15:8]" "data_packer_SDI_TX_0:data_o[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:DATA_I[23:16]" "data_packer_SDI_TX_0:data_o[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:DATA_I[31:24]" "data_packer_SDI_TX_0:data_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:DATA_I[7:0]" "data_packer_SDI_TX_0:data_o[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:G_O[15:8]" "RGB2YCbCr_C2_1:GREEN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:G_O[23:16]" "RGB2YCbCr_C2_2:GREEN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:G_O[31:24]" "RGB2YCbCr_C2_3:GREEN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:G_O[7:0]" "RGB2YCbCr_C2_0:GREEN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:R_O[15:8]" "RGB2YCbCr_C2_1:RED_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:R_O[23:16]" "RGB2YCbCr_C2_2:RED_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:R_O[31:24]" "RGB2YCbCr_C2_3:RED_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Bayer_Interpolation_C2_0:R_O[7:0]" "RGB2YCbCr_C2_0:RED_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:display_frame_addr_o" "display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:frame_ddr_addr_i" "frame_ddr_addr_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:horiz_resolution_i" "data_packer_SDI_TX_0:h_count_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:write_length_o" "beats_to_write_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_write_controller_0:write_start_addr_o" "write_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_0:Cb_OUT_O" "data_packer_0:data_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_0:Y_OUT_O" "data_packer_0:data_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_1:Cr_OUT_O" "data_packer_0:data_i[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_1:Y_OUT_O" "data_packer_0:data_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_2:Cb_OUT_O" "data_packer_0:data_i[47:40]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_2:Y_OUT_O" "data_packer_0:data_i[39:32]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_3:Cr_OUT_O" "data_packer_0:data_i[63:56]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RGB2YCbCr_C2_3:Y_OUT_O" "data_packer_0:data_i[55:48]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"data_i" "data_packer_SDI_TX_0:data_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"data_packer_0:data_o" "video_fifo_0:wdata_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"rdata_o" "video_fifo_0:rdata_o" }


# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign DDR_Write
generate_component -component_name ${sd_name}
