# Creating SmartDesign PROC_SUBSYSTEM
set sd_name {PROC_SUBSYSTEM}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {PCLK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PREADYS9} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSLVERRS9} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {reset} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {APB_Reset} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {GPIO_OUT} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PENABLES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PSELS9} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {PWRITES} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRNG_RST_N} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {PRDATAS9} -port_direction {IN} -port_range {[31:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PADDRS} -port_direction {OUT} -port_range {[31:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {PWDATAS} -port_direction {OUT} -port_range {[31:0]}


# Create top level Bus interface Ports
sd_create_bif_port -sd_name ${sd_name} -port_name {APBmslave9} -port_bif_vlnv {AMBA:AMBA2:APB:r0p0} -port_bif_role {mirroredSlave} -port_bif_mapping {\
"PADDR:PADDRS" \
"PSELx:PSELS9" \
"PENABLE:PENABLES" \
"PWRITE:PWRITES" \
"PRDATA:PRDATAS9" \
"PWDATA:PWDATAS" \
"PREADY:PREADYS9" \
"PSLVERR:PSLVERRS9" } 

# Add BIBUF_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_0:D} -value {GND}



# Add BIBUF_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_1:D} -value {GND}



# Add BIBUF_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_2:D} -value {GND}



# Add BIBUF_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_3:D} -value {GND}



# Add BIBUF_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_4}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_4:D} -value {GND}



# Add BIBUF_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {BIBUF} -instance_name {BIBUF_5}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {BIBUF_5:D} -value {GND}



# Add CoreAHBLite_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBLite_C0} -instance_name {CoreAHBLite_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBLite_C0_0:REMAP_M0} -value {GND}



# Add CoreAHBLite_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBLite_C1} -instance_name {CoreAHBLite_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBLite_C1_0:REMAP_M0} -value {GND}



# Add COREAHBTOAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_C0} -instance_name {COREAHBTOAPB3_C0_0}



# Add CoreAPB3_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreAPB3_C0_0:APBmslave6}



# Add CoreGPIO_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_C0} -instance_name {CoreGPIO_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[31:10]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_OUT[31:10]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[3:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[4:4]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[6:5]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[7:7]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[8:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_C0_0:GPIO_OUT} -pin_slices {[9:9]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:INT}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_C0_0:GPIO_IN} -value {GND}



# Add COREI2C_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C0} -instance_name {COREI2C_C0_0}



# Add COREI2C_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C1} -instance_name {COREI2C_C1_0}



# Add COREI2C_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREI2C_C2} -instance_name {COREI2C_C2_0}



# Add COREJTAGDEBUG_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREJTAGDEBUG_C0} -instance_name {COREJTAGDEBUG_C0_0}



# Add INV_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_0}



# Add INV_1 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_1}



# Add INV_2 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_2}



# Add INV_3 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_3}



# Add INV_4 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_4}



# Add INV_5 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {INV} -instance_name {INV_5}



# Add MIV_RV32IMA_L1_AHB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMA_L1_AHB_C0} -instance_name {MIV_RV32IMA_L1_AHB_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_C0_0:IRQ} -pin_slices {[26:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:IRQ[26:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_C0_0:IRQ} -pin_slices {[27:27]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_C0_0:IRQ} -pin_slices {[28:28]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_C0_0:IRQ} -pin_slices {[29:29]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_C0_0:IRQ} -pin_slices {[30:30]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:IRQ[30:30]} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:AHB_MST_MEM_HSEL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:AHB_MST_MMIO_HSEL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:EXT_RESETN}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_C0_0:DRV_TDO}



# Add PF_SRAM_AHBL_AXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_AHBL_AXI_C0} -instance_name {PF_SRAM_AHBL_AXI_C0_0}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_CLK" "COREAHBTOAPB3_C0_0:HCLK" "COREI2C_C0_0:PCLK" "COREI2C_C1_0:PCLK" "COREI2C_C2_0:PCLK" "CoreAHBLite_C0_0:HCLK" "CoreAHBLite_C1_0:HCLK" "CoreGPIO_C0_0:PCLK" "MIV_RV32IMA_L1_AHB_C0_0:CLK" "PCLK" "PF_SRAM_AHBL_AXI_C0_0:HCLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"APB_Reset" "COREAHBTOAPB3_C0_0:HRESETN" "COREI2C_C0_0:PRESETN" "COREI2C_C1_0:PRESETN" "COREI2C_C2_0:PRESETN" "CoreAHBLite_C0_0:HRESETN" "CoreAHBLite_C1_0:HRESETN" "CoreGPIO_C0_0:PRESETN" "HDMI_RST" "MIV_RV32IMA_L1_AHB_C0_0:RESETN" "PF_SRAM_AHBL_AXI_C0_0:HRESETN" "reset" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:E" "INV_0:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:PAD" "CAM1_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_0:Y" "COREI2C_C0_0:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:E" "INV_1:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:PAD" "CAM1_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_1:Y" "COREI2C_C0_0:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:E" "INV_2:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:PAD" "HDMI_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_2:Y" "COREI2C_C1_0:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:E" "INV_3:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:PAD" "HDMI_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_3:Y" "COREI2C_C1_0:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:E" "INV_4:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:PAD" "CAM2_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_4:Y" "COREI2C_C2_0:SCLI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:E" "INV_5:Y" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:PAD" "CAM2_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BIBUF_5:Y" "COREI2C_C2_0:SDAI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "CoreGPIO_C0_0:GPIO_OUT[8:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:INT" "MIV_RV32IMA_L1_AHB_C0_0:IRQ[28:28]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:SCLO" "INV_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:SDAO" "INV_1:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C1_0:INT" "MIV_RV32IMA_L1_AHB_C0_0:IRQ[27:27]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C1_0:SCLO" "INV_2:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C1_0:SDAO" "INV_3:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C2_0:INT" "MIV_RV32IMA_L1_AHB_C0_0:IRQ[29:29]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C2_0:SCLO" "INV_4:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C2_0:SDAO" "INV_5:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TCK_0" "MIV_RV32IMA_L1_AHB_C0_0:TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDI_0" "MIV_RV32IMA_L1_AHB_C0_0:TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TDO_0" "MIV_RV32IMA_L1_AHB_C0_0:TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TMS_0" "MIV_RV32IMA_L1_AHB_C0_0:TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TGT_TRST_0" "MIV_RV32IMA_L1_AHB_C0_0:TRST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREJTAGDEBUG_C0_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_OUT[4:4]" "TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_OUT[9:9]" "GPIO_OUT" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_C0_0:GPIO_OUT[3:0]" "GPIO_OUT_0" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"APBmslave9" "CoreAPB3_C0_0:APBmslave9" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:AHBslave" "CoreAHBLite_C1_0:AHBmslave7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_C0_0:APBmaster" "CoreAPB3_C0_0:APB3mmaster" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C0_0:APBslave" "CoreAPB3_C0_0:APBmslave7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C1_0:APBslave" "CoreAPB3_C0_0:APBmslave8" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREI2C_C2_0:APBslave" "CoreAPB3_C0_0:APBmslave4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite_C0_0:AHBmmaster0" "MIV_RV32IMA_L1_AHB_C0_0:AHB_MST_MEM" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite_C0_0:AHBmslave16" "PF_SRAM_AHBL_AXI_C0_0:AHBSlaveInterface" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBLite_C1_0:AHBmmaster0" "MIV_RV32IMA_L1_AHB_C0_0:AHB_MST_MMIO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_C0_0:APBmslave5" "CoreGPIO_C0_0:APB_bif" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign PROC_SUBSYSTEM
generate_component -component_name ${sd_name}
