# Creating SmartDesign VIDEO_KIT_TOP
set sd_name {VIDEO_KIT_TOP}
create_smartdesign -sd_name ${sd_name}

# Disable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 0

# Create top level Scalar Ports
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RX_CLK_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CLK_IN} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P_0} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_RXD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_N} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {REF_CLK_PAD_P} -port_direction {IN} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN}

sd_create_scalar_port -sd_name ${sd_name} -port_name {ACT_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {BG} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_RST} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAMERA_CLK} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM_CLK_EN} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CK0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CKE} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P_0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE0_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE1_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE2_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {LANE3_TXD_P} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {ODT} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RAS_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {RESET_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD0} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD1} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD2} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD3} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD4} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD5} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD6} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {SHIELD7} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {WE_N} -port_direction {OUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {data_enable_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {hdmi_clk} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {horz_sync_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {line_valid_o} -port_direction {OUT}
sd_create_scalar_port -sd_name ${sd_name} -port_name {vert_sync_o} -port_direction {OUT}

sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM1_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {CAM2_SDA} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SCL} -port_direction {INOUT} -port_is_pad {1}
sd_create_scalar_port -sd_name ${sd_name} -port_name {HDMI_SDA} -port_direction {INOUT} -port_is_pad {1}

# Create top level Bus Ports
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD_N} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {CAM1_RXD} -port_direction {IN} -port_range {[3:0]} -port_is_pad {1}

sd_create_bus_port -sd_name ${sd_name} -port_name {A} -port_direction {OUT} -port_range {[13:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {BA} -port_direction {OUT} -port_range {[1:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {B_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {DM_N} -port_direction {OUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {GPIO_OUT_0} -port_direction {OUT} -port_range {[3:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {G_out_o} -port_direction {OUT} -port_range {[7:0]}
sd_create_bus_port -sd_name ${sd_name} -port_name {R_out_o} -port_direction {OUT} -port_range {[7:0]}

sd_create_bus_port -sd_name ${sd_name} -port_name {DQS_N} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQS} -port_direction {INOUT} -port_range {[7:0]} -port_is_pad {1}
sd_create_bus_port -sd_name ${sd_name} -port_name {DQ} -port_direction {INOUT} -port_range {[63:0]} -port_is_pad {1}

# Add AND2_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0}



# Add AND4_0 instance
sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND4} -instance_name {AND4_0}



# Add apb3_if_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {apb3_if} -instance_name {apb3_if_0}
# Exporting Parameters of instance apb3_if_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {apb3_if_0} -params {\
"g_APB3_IF_DATA_WIDTH:32" \
"g_CONST_WIDTH:12" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_update_instance -sd_name ${sd_name} -instance_name {apb3_if_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:mode_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:alpha_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:step_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {apb3_if_0:frame_tcount_o}



# Add COREDDR_LITEAXI_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREDDR_LITEAXI_C0} -instance_name {COREDDR_LITEAXI_C0_0}



# Add CORERESET_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C0} -instance_name {CORERESET_PF_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:INIT_DONE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:FPGA_POR_N} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C0_0:PLL_POWERDOWN_B}



# Add CORERESET_PF_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:INIT_DONE} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:FPGA_POR_N} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_0:PLL_POWERDOWN_B}



# Add CORERESET_PF_C1_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:FPGA_POR_N} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_1:PLL_POWERDOWN_B}



# Add CORERESET_PF_C1_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {CORERESET_PF_C1} -instance_name {CORERESET_PF_C1_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:EXT_RST_N} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:BANK_x_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:BANK_y_VDDI_STATUS} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:SS_BUSY} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:FF_US_RESTORE} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:FPGA_POR_N} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CORERESET_PF_C1_2:PLL_POWERDOWN_B}



# Add COREUHD_SDIRX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREUHD_SDIRX_C0} -instance_name {COREUHD_SDIRX_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS1} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS1[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS1} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS2} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS2[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS2} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS3} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS3[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS3} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS4} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS4[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS4} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS5} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS5[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS5} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS6} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS6[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS6} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS7} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS7[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS7} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS8} -pin_slices {[1:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DATA_DS8[1:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {COREUHD_SDIRX_C0_0:RX_DATA_DS8} -pin_slices {[9:2]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_ALIGNED}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DS_MUX}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_TRS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_SAV}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_EAV}
sd_invert_pins -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VANC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_HANC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DS_C}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_DS_Y}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_BAD_TRS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_C_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_LN_Y_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_C_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_Y_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_C_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS1}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS2}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS3}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS4}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS5}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS6}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS7}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_VPID_LN_Y_DS8}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_CS_C_ERROR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_CS_Y_ERROR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_CRC_C_ERROR}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDIRX_C0_0:RX_CRC_Y_ERROR}



# Add COREUHD_SDITX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {COREUHD_SDITX_C0} -instance_name {COREUHD_SDITX_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_INSERT_LN} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_INSERT_CRC} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_INSERT_VPID} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_DS_MUX}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_TRS}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_BAD_TRS}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS1} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS2} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS3} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS4} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS5} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS6} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS7} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_LN_DS8} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS1} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS2} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS3} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS4} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS5} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS6} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS7} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_DS8} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS1} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS2} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS3} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS4} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS5} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS6} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS7} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {COREUHD_SDITX_C0_0:TX_VPID_LN_DS8} -value {GND}



# Add DDR_AXI4_ARBITER_PF_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_AXI4_ARBITER_PF_C0} -instance_name {DDR_AXI4_ARBITER_PF_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_data_valid_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_req_i} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_ack_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_done_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_burst_size_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_data_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_AXI4_ARBITER_PF_C0_0:w3_wstart_addr_i} -value {GND}



# Add DDR_Read_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read} -instance_name {DDR_Read_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:beats_to_read_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_0:beats_to_read_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:beats_to_read_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:bayer_data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:bayer_data_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:bayer_data_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_0:bayer_data_o} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_0:ddr_read_offset} -value {0000000000000000}



# Add DDR_Read_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read} -instance_name {DDR_Read_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:beats_to_read_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_1:beats_to_read_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:beats_to_read_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:bayer_data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:bayer_data_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:bayer_data_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_1:bayer_data_o} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_1:bayer_dvalid_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_1:ddr_read_offset} -value {0010000000000000}



# Add DDR_Read_FHD_RX_0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_FHD_RX_0} -instance_name {DDR_Read_FHD_RX_0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_FHD_RX_0_0:beats_to_read_0} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_FHD_RX_0_0:beats_to_read_0[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_FHD_RX_0_0:beats_to_read_0} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_FHD_RX_0_0:data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_FHD_RX_0_0:data_o} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_FHD_RX_0_0:horz_resl_i} -value {0000011110000000}



# Add DDR_Read_HDMI_RX_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Read_HDMI_RX} -instance_name {DDR_Read_HDMI_RX_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:beats_to_read_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:beats_to_read_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:beats_to_read_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[47:40]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[55:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[63:56]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Read_HDMI_RX_0:data_o} -pin_slices {[7:0]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:blue_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:red_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:green_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:v_pan_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:h_pan_i} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:horz_resl_i} -value {0000111100000000}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Read_HDMI_RX_0:alpha_o}



# Add DDR_Write_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write} -instance_name {DDR_Write_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_0:beats_to_write_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Write_0:beats_to_write_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_0:beats_to_write_o} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_0:frame_ddr_addr_i} -value {00000000}



# Add DDR_Write_HDMI_RX_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_HDMI_RX} -instance_name {DDR_Write_HDMI_RX_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:beats_to_write_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_0:beats_to_write_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:beats_to_write_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:data_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:data_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:data_i} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_0:data_i} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_0:frame_ddr_addr_i} -value {00010000}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_0:ddr_write_offset} -value {0000000000000000}



# Add DDR_Write_HDMI_RX_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {DDR_Write_HDMI_RX} -instance_name {DDR_Write_HDMI_RX_1}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:beats_to_write_o} -pin_slices {[15:8]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_1:beats_to_write_o[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:beats_to_write_o} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:data_i} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:data_i} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:data_i} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {DDR_Write_HDMI_RX_1:data_i} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_1:frame_ddr_addr_i} -value {00010000}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_1:display_frame_addr_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {DDR_Write_HDMI_RX_1:ddr_write_offset} -value {0010000000000000}



# Add Display_Controller_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Display_Controller_C2} -instance_name {Display_Controller_C2_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[47:40]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[55:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[63:56]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[71:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[79:72]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[87:80]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_I} -pin_slices {[95:88]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[39:32]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[47:40]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[55:48]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[63:56]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[71:64]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[79:72]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[87:80]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C2_0:DATA_O} -pin_slices {[95:88]}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C2_0:V_ACTIVE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C2_0:H_RES_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C2_0:V_RES_O}



# Add Display_Controller_C3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Display_Controller_C3} -instance_name {Display_Controller_C3_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {Display_Controller_C3_0:DATA_O} -pin_slices {[7:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Display_Controller_C3_0:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C3_0:V_ACTIVE_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C3_0:H_RES_O}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Display_Controller_C3_0:V_RES_O}



# Add Gamma_Correction_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C0} -instance_name {Gamma_Correction_C0_0}



# Add Gamma_Correction_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C1} -instance_name {Gamma_Correction_C1_0}



# Add Gamma_Correction_C2_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C2} -instance_name {Gamma_Correction_C2_0}



# Add Gamma_Correction_C3_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C3} -instance_name {Gamma_Correction_C3_0}



# Add Gamma_Correction_C4_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Gamma_Correction_C4} -instance_name {Gamma_Correction_C4_0}



# Add HDMI_TX_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {HDMI_TX_C1} -instance_name {HDMI_TX_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_R_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_R_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_R_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_R_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_G_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_G_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_G_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_G_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_B_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_B_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_B_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {HDMI_TX_C0_0:DATA_B_I} -pin_slices {[7:0]}



# Add Image_Enhancement_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_0}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_0:ENABLE_I} -value {VCC}



# Add Image_Enhancement_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_1}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_1:ENABLE_I} -value {VCC}



# Add Image_Enhancement_C0_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_2}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_2:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_2:DATA_VALID_O}



# Add Image_Enhancement_C0_3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_3}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_3:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_3:DATA_VALID_O}



# Add Image_Enhancement_C0_4 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {Image_Enhancement_C0} -instance_name {Image_Enhancement_C0_4}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_4:ENABLE_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {Image_Enhancement_C0_4:DATA_VALID_O}



# Add IMX334_IF_TOP_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {IMX334_IF_TOP} -instance_name {IMX334_IF_TOP_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {IMX334_IF_TOP_0:frame_start_o}



# Add PF_CCC_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C0} -instance_name {PF_CCC_C0_0}



# Add PF_CCC_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_C1} -instance_name {PF_CCC_C1_0}



# Add PF_DDR4_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_DDR4_C0} -instance_name {PF_DDR4_C0_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_DDR4_C0_0:l_addr_p0} -pin_slices {[35:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {PF_DDR4_C0_0:l_addr_p0} -pin_slices {[38:36]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_DDR4_C0_0:l_addr_p0[38:36]} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_DDR4_C0_0:l_auto_pch_p0} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DDR4_C0_0:l_r_valid_last_p0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_DDR4_C0_0:l_d_req_last_p0}



# Add PF_INIT_MONITOR_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_INIT_MONITOR_C0} -instance_name {PF_INIT_MONITOR_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:FABRIC_POR_N}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:PCIE_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:XCVR_INIT_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:USRAM_INIT_FROM_SPI_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SNVM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_UPROM_DONE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_INIT_MONITOR_C0_0:SRAM_INIT_FROM_SPI_DONE}



# Add PF_TX_PLL_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C0} -instance_name {PF_TX_PLL_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_TX_PLL_C0_0:PLL_LOCK}



# Add PF_TX_PLL_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_TX_PLL_C1} -instance_name {PF_TX_PLL_C1_0}



# Add PF_XCVR_ERM_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C0} -instance_name {PF_XCVR_ERM_C0_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_CLK_R}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_VAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_CLK_R}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_VAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_CLK_R}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_VAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_BYPASS_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_CLK_R}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_READY}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_VAL}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_TX_DATA} -value {0000011111000001111100000111110000011111}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE0_RX_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE1_RX_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE2_RX_DATA}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C0_0:LANE3_RX_DATA}



# Add PF_XCVR_ERM_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_ERM_C1} -instance_name {PF_XCVR_ERM_C1_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_IDLE}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_BYPASS_DATA}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_LOS} -value {GND}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_CALIB_REQ} -value {GND}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_CALIBRATING}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PF_XCVR_ERM_C1_0:LANE0_RX_VAL}



# Add PF_XCVR_REF_CLK_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PF_XCVR_REF_CLK_C0} -instance_name {PF_XCVR_REF_CLK_C0_0}



# Add PROC_SUBSYSTEM_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {PROC_SUBSYSTEM} -instance_name {PROC_SUBSYSTEM_0}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {PROC_SUBSYSTEM_0:HDMI_RST}



# Add SDI_interface_12G422_0 instance
sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {SDI_interface_12G422} -hdl_file {hdl\SDI_interface_12G422.vhd} -instance_name {SDI_interface_12G422_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y11_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Y11_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y11_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb11_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cb11_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb11_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr11_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cr11_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr11_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y12_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Y12_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y12_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb12_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cb12_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb12_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr12_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cr12_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr12_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y21_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Y21_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y21_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb21_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cb21_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb21_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr21_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cr21_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr21_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y22_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Y22_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Y22_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb22_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cb22_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cb22_I} -pin_slices {[9:2]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr22_I} -pin_slices {[1:0]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:Cr22_I[1:0]} -value {GND}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {SDI_interface_12G422_0:Cr22_I} -pin_slices {[9:2]}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:ENABLE_I} -value {VCC}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:ENABLE_EXT_SYNC_I} -value {VCC}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {SDI_interface_12G422_0:DATA_ENABLE_O}



# Add UART_interface_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {UART_interface} -instance_name {UART_interface_0}
sd_invert_pins -sd_name ${sd_name} -pin_names {UART_interface_0:pip_select_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_edge_sel_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:pip_mode_sel_o}
sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {UART_interface_0:status_i} -value {1010}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:alpha_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:v_shift_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:h_shift_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:step_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:h_pan_c2_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:v_pan_c2_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_format2_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:bayer_format0_o}
sd_mark_pins_unused -sd_name ${sd_name} -pin_names {UART_interface_0:alpha_hdmi_o}



# Add YCbCr2RGB_C0_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCr2RGB_C0_0}



# Add YCbCr2RGB_C0_1 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCr2RGB_C0_1}



# Add YCbCr2RGB_C0_2 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCr2RGB_C0_2}



# Add YCbCr2RGB_C0_3 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCr2RGB_C0_3}



# Add YCbCr2RGB_C1_0 instance
sd_instantiate_component -sd_name ${sd_name} -component_name {YCbCrtoRGB_C0} -instance_name {YCbCr2RGB_C1_0}



# Add YCbCr_422to444_0 instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {YCbCr_422two444} -instance_name {YCbCr_422to444_0}
# Exporting Parameters of instance YCbCr_422to444_0
sd_configure_core_instance -sd_name ${sd_name} -instance_name {YCbCr_422to444_0} -params {\
"G_YCbCr_422_DATA_BIT_WIDTH:8" \
"G_YCbCr_422_NUM_OF_PIXELS:4" \
"G_YCbCr_444_DATA_BIT_WIDTH:8" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {YCbCr_422to444_0}
sd_update_instance -sd_name ${sd_name} -instance_name {YCbCr_422to444_0}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:C_I} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:C_I} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:C_I} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:C_I} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Y_O} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cb_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cb_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cb_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cb_O} -pin_slices {[7:0]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cr_O} -pin_slices {[15:8]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cr_O} -pin_slices {[23:16]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cr_O} -pin_slices {[31:24]}
sd_create_pin_slices -sd_name ${sd_name} -pin_name {YCbCr_422to444_0:Cr_O} -pin_slices {[7:0]}



# Add YCbCr_422to444_1pixel instance
sd_instantiate_hdl_core -sd_name ${sd_name} -hdl_core_name {YCbCr_422two444} -instance_name {YCbCr_422to444_1pixel}
# Exporting Parameters of instance YCbCr_422to444_1pixel
sd_configure_core_instance -sd_name ${sd_name} -instance_name {YCbCr_422to444_1pixel} -params {\
"G_YCbCr_422_DATA_BIT_WIDTH:8" \
"G_YCbCr_422_NUM_OF_PIXELS:1" \
"G_YCbCr_444_DATA_BIT_WIDTH:8" }\
-validate_rules 0
sd_save_core_instance_config -sd_name ${sd_name} -instance_name {YCbCr_422to444_1pixel}
sd_update_instance -sd_name ${sd_name} -instance_name {YCbCr_422to444_1pixel}



# Add scalar net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"ACT_N" "PF_DDR4_C0_0:ACT_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "CORERESET_PF_C1_1:INIT_DONE" "CORERESET_PF_C1_2:INIT_DONE" "COREUHD_SDIRX_C0_0:RX_RESETN" "PF_INIT_MONITOR_C0_0:DEVICE_INIT_DONE" "PF_XCVR_ERM_C1_0:CTRL_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C1_0:LANE0_PMA_ARST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "AND4_0:A" "PF_CCC_C0_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "CORERESET_PF_C1_2:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:B" "PF_DDR4_C0_0:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:C" "DDR_AXI4_ARBITER_PF_C0_0:ddr_ctrl_ready_i" "PF_DDR4_C0_0:CTRLR_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:D" "PF_CCC_C1_0:PLL_LOCK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"AND4_0:Y" "CORERESET_PF_C0_0:PLL_LOCK" "CORERESET_PF_C1_0:PLL_LOCK" "CORERESET_PF_C1_1:PLL_LOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BG" "PF_DDR4_C0_0:BG" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RST" "PROC_SUBSYSTEM_0:CAM1_RST" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_N" "IMX334_IF_TOP_0:CAM1_RX_CLK_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RX_CLK_P" "IMX334_IF_TOP_0:CAM1_RX_CLK_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_SCL" "PROC_SUBSYSTEM_0:CAM1_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_SDA" "PROC_SUBSYSTEM_0:CAM1_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SCL" "PROC_SUBSYSTEM_0:CAM2_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM2_SDA" "PROC_SUBSYSTEM_0:CAM2_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAMERA_CLK" "IMX334_IF_TOP_0:CAMERA_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM_CLK_EN" "PROC_SUBSYSTEM_0:GPIO_OUT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAS_N" "PF_DDR4_C0_0:CAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0" "PF_DDR4_C0_0:CK0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CK0_N" "PF_DDR4_C0_0:CK0_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CKE" "PF_DDR4_C0_0:CKE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CLK_IN" "PF_CCC_C0_0:REF_CLK_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:ACLK" "CORERESET_PF_C1_0:CLK" "DDR_AXI4_ARBITER_PF_C0_0:sys_clk_i" "DDR_Read_0:sys_clk_i" "DDR_Read_1:sys_clk_i" "DDR_Read_FHD_RX_0_0:sys_clk_i" "DDR_Read_HDMI_RX_0:sys_clk_i" "DDR_Write_0:ddr_clock_i" "DDR_Write_HDMI_RX_0:ddr_clk_i" "DDR_Write_HDMI_RX_1:ddr_clk_i" "PF_CCC_C1_0:REF_CLK_0" "PF_DDR4_C0_0:SYS_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:ARESET_N" "CORERESET_PF_C1_0:FABRIC_RESET_N" "DDR_AXI4_ARBITER_PF_C0_0:reset_i" "DDR_Read_0:reset_i" "DDR_Read_1:reset_i" "DDR_Read_HDMI_RX_0:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_BUSY" "PF_DDR4_C0_0:l_busy_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_D_REQ" "PF_DDR4_C0_0:l_d_req_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_R_REQ" "PF_DDR4_C0_0:l_r_req_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_R_VALID" "PF_DDR4_C0_0:l_r_valid_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_W_REQ" "PF_DDR4_C0_0:l_w_req_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:CLK" "DDR_Read_HDMI_RX_0:disp_clk_i" "Display_Controller_C2_0:SYS_CLK_I" "Gamma_Correction_C1_0:SYS_CLK_I" "Gamma_Correction_C2_0:SYS_CLK_I" "Gamma_Correction_C3_0:SYS_CLK_I" "Gamma_Correction_C4_0:SYS_CLK_I" "HDMI_TX_C0_0:SYS_CLK_I" "Image_Enhancement_C0_1:SYS_CLK_I" "Image_Enhancement_C0_2:SYS_CLK_I" "Image_Enhancement_C0_3:SYS_CLK_I" "Image_Enhancement_C0_4:SYS_CLK_I" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_R" "YCbCr2RGB_C0_0:CLOCK_I" "YCbCr2RGB_C0_1:CLOCK_I" "YCbCr2RGB_C0_2:CLOCK_I" "YCbCr2RGB_C1_0:CLOCK_I" "YCbCr_422to444_0:CLOCK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C0_0:FABRIC_RESET_N" "DDR_Write_HDMI_RX_0:reset_i" "DDR_Write_HDMI_RX_1:reset_i" "Display_Controller_C2_0:RESETN_I" "Gamma_Correction_C1_0:RESETN_I" "Gamma_Correction_C2_0:RESETN_I" "Gamma_Correction_C3_0:RESETN_I" "Gamma_Correction_C4_0:RESETN_I" "HDMI_TX_C0_0:RESET_N_I" "Image_Enhancement_C0_1:RESETN_I" "Image_Enhancement_C0_2:RESETN_I" "Image_Enhancement_C0_3:RESETN_I" "Image_Enhancement_C0_4:RESETN_I" "PF_XCVR_ERM_C0_0:LANE0_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE0_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE1_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE2_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE2_PMA_ARST_N" "PF_XCVR_ERM_C0_0:LANE3_PCS_ARST_N" "PF_XCVR_ERM_C0_0:LANE3_PMA_ARST_N" "YCbCr2RGB_C0_0:RESET_N_I" "YCbCr2RGB_C0_1:RESET_N_I" "YCbCr2RGB_C0_2:RESET_N_I" "YCbCr2RGB_C1_0:RESET_N_I" "YCbCr_422to444_0:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_1:CLK" "DDR_Read_FHD_RX_0_0:disp_clk_i" "Display_Controller_C3_0:SYS_CLK_I" "Gamma_Correction_C0_0:SYS_CLK_I" "Image_Enhancement_C0_0:SYS_CLK_I" "PF_CCC_C1_0:OUT0_FABCLK_0" "PF_TX_PLL_C0_0:FAB_REF_CLK" "PF_XCVR_ERM_C0_0:LANE0_CDR_REF_CLK_FAB" "PF_XCVR_ERM_C0_0:LANE1_CDR_REF_CLK_FAB" "PF_XCVR_ERM_C0_0:LANE2_CDR_REF_CLK_FAB" "PF_XCVR_ERM_C0_0:LANE3_CDR_REF_CLK_FAB" "YCbCr2RGB_C0_3:CLOCK_I" "YCbCr_422to444_1pixel:CLOCK_I" "hdmi_clk" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_1:FABRIC_RESET_N" "DDR_Read_FHD_RX_0_0:resetn_i" "Display_Controller_C3_0:RESETN_I" "Gamma_Correction_C0_0:RESETN_I" "Image_Enhancement_C0_0:RESETN_I" "YCbCr2RGB_C0_3:RESET_N_I" "YCbCr_422to444_1pixel:RESET_N_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_2:CLK" "PF_CCC_C0_0:OUT1_FABCLK_0" "PF_DDR4_C0_0:PLL_REF_CLK" "PROC_SUBSYSTEM_0:PCLK" "UART_interface_0:sys_clk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CORERESET_PF_C1_2:FABRIC_RESET_N" "PF_DDR4_C0_0:SYS_RESET_N" "PROC_SUBSYSTEM_0:reset" "UART_interface_0:reset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_AV" "DDR_Write_HDMI_RX_0:data_valid_i" "DDR_Write_HDMI_RX_1:data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_CLK" "DDR_Write_HDMI_RX_0:parallel_clk_i" "DDR_Write_HDMI_RX_1:parallel_clk_i" "PF_XCVR_ERM_C1_0:LANE0_RX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_READY" "DDR_Write_HDMI_RX_0:rx_ready_i" "DDR_Write_HDMI_RX_1:rx_ready_i" "PF_XCVR_ERM_C1_0:LANE0_RX_READY" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_VANC" "DDR_Write_HDMI_RX_0:frame_valid_i" "DDR_Write_HDMI_RX_1:frame_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_CLK" "DDR_Read_0:disp_clk_i" "DDR_Read_1:disp_clk_i" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_G" "SDI_interface_12G422_0:SYS_CLK_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_CLK_STABLE" "PF_XCVR_ERM_C1_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_RESETN" "PF_TX_PLL_C1_0:PLL_LOCK" "SDI_interface_12G422_0:RESETN_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CS_N" "PF_DDR4_C0_0:CS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_ack_o" "DDR_Read_HDMI_RX_0:read_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_data_valid_o" "DDR_Read_HDMI_RX_0:ddr_data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_done_o" "DDR_Read_HDMI_RX_0:read_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_req_i" "DDR_Read_HDMI_RX_0:read_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_ack_o" "DDR_Read_0:read_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_data_valid_o" "DDR_Read_0:ddr_data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_done_o" "DDR_Read_0:read_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_req_i" "DDR_Read_0:read_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_ack_o" "DDR_Read_1:read_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_data_valid_o" "DDR_Read_1:ddr_data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_done_o" "DDR_Read_1:read_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_req_i" "DDR_Read_1:read_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_ack_o" "DDR_Read_FHD_RX_0_0:read_ack_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_data_valid_o" "DDR_Read_FHD_RX_0_0:ddr_data_valid_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_done_o" "DDR_Read_FHD_RX_0_0:read_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_req_i" "DDR_Read_FHD_RX_0_0:read_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_ack_o" "DDR_Write_HDMI_RX_0:write_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_valid_i" "DDR_Write_HDMI_RX_0:rdata_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_done_o" "DDR_Write_HDMI_RX_0:write_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_req_i" "DDR_Write_HDMI_RX_0:write_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_ack_o" "DDR_Write_0:write_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_data_valid_i" "DDR_Write_0:rdata_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_done_o" "DDR_Write_0:write_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_req_i" "DDR_Write_0:write_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_ack_o" "DDR_Write_HDMI_RX_1:write_ackn_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_data_valid_i" "DDR_Write_HDMI_RX_1:rdata_rdy_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_done_o" "DDR_Write_HDMI_RX_1:write_done_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_req_i" "DDR_Write_HDMI_RX_1:write_req_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:bayer_dvalid_o" "SDI_interface_12G422_0:EXT_SYNC_SIGNAL_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:frame_end_i" "DDR_Read_1:frame_end_i" "SDI_interface_12G422_0:FRAME_END_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:read_en_i" "DDR_Read_1:read_en_i" "SDI_interface_12G422_0:DATA_TRIGGER_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:data_valid_o" "YCbCr_422to444_1pixel:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:frame_end_i" "Display_Controller_C3_0:FRAME_END_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:read_en_i" "Display_Controller_C3_0:DATA_TRIGGER_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:bayer_dvalid_o" "YCbCr_422to444_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:frame_end_i" "Display_Controller_C2_0:FRAME_END_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:read_en_i" "Display_Controller_C2_0:DATA_TRIGGER_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:data_valid_i" "IMX334_IF_TOP_0:line_valid_o" "line_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:frame_valid_i" "IMX334_IF_TOP_0:frame_valid_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:parallel_clk_i" "IMX334_IF_TOP_0:PARALLEL_CLOCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:reset_i" "IMX334_IF_TOP_0:CAMCLK_RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_VALID_O" "HDMI_TX_C0_0:VIDEO_DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:ENABLE_I" "PF_XCVR_ERM_C0_0:LANE0_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:EXT_SYNC_SIGNAL_I" "Image_Enhancement_C0_1:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:H_SYNC_O" "HDMI_TX_C0_0:H_SYNC_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:V_SYNC_O" "HDMI_TX_C0_0:V_SYNC_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_VALID_O" "data_enable_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:EXT_SYNC_SIGNAL_I" "Image_Enhancement_C0_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:H_SYNC_O" "horz_sync_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:V_SYNC_O" "vert_sync_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:DATA_VALID_I" "YCbCr2RGB_C0_3:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:DATA_VALID_O" "Image_Enhancement_C0_0:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:DATA_VALID_I" "YCbCr2RGB_C0_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:DATA_VALID_O" "Image_Enhancement_C0_1:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:DATA_VALID_I" "YCbCr2RGB_C1_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:DATA_VALID_O" "Image_Enhancement_C0_2:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:DATA_VALID_I" "YCbCr2RGB_C0_1:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:DATA_VALID_O" "Image_Enhancement_C0_3:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:DATA_VALID_I" "YCbCr2RGB_C0_2:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:DATA_VALID_O" "Image_Enhancement_C0_4:DATA_VALID_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_SCL" "PROC_SUBSYSTEM_0:HDMI_SCL" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_SDA" "PROC_SUBSYSTEM_0:HDMI_SDA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:B_CLK_I" "PF_XCVR_ERM_C0_0:LANE3_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:B_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE3_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:G_CLK_I" "PF_XCVR_ERM_C0_0:LANE2_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:G_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE2_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:R_CLK_I" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_R" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:R_CLK_LOCK" "PF_XCVR_ERM_C0_0:LANE1_TX_CLK_STABLE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:ARST_N" "IMX334_IF_TOP_0:INIT_DONE" "PF_INIT_MONITOR_C0_0:AUTOCALIB_DONE" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"IMX334_IF_TOP_0:TRNG_RST_N" "PROC_SUBSYSTEM_0:TRNG_RST_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N" "PF_XCVR_ERM_C0_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_N_0" "PF_XCVR_ERM_C1_0:LANE0_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P" "PF_XCVR_ERM_C0_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_RXD_P_0" "PF_XCVR_ERM_C1_0:LANE0_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N" "PF_XCVR_ERM_C0_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_N_0" "PF_XCVR_ERM_C1_0:LANE0_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P" "PF_XCVR_ERM_C0_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE0_TXD_P_0" "PF_XCVR_ERM_C1_0:LANE0_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_N" "PF_XCVR_ERM_C0_0:LANE1_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_RXD_P" "PF_XCVR_ERM_C0_0:LANE1_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_N" "PF_XCVR_ERM_C0_0:LANE1_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE1_TXD_P" "PF_XCVR_ERM_C0_0:LANE1_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_N" "PF_XCVR_ERM_C0_0:LANE2_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_RXD_P" "PF_XCVR_ERM_C0_0:LANE2_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_N" "PF_XCVR_ERM_C0_0:LANE2_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE2_TXD_P" "PF_XCVR_ERM_C0_0:LANE2_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_N" "PF_XCVR_ERM_C0_0:LANE3_RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_RXD_P" "PF_XCVR_ERM_C0_0:LANE3_RXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_N" "PF_XCVR_ERM_C0_0:LANE3_TXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"LANE3_TXD_P" "PF_XCVR_ERM_C0_0:LANE3_TXD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"ODT" "PF_DDR4_C0_0:ODT" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_C0_0:OUT0_FABCLK_0" "PF_XCVR_ERM_C1_0:CTRL_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RAS_N" "RAS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:RESET_N" "RESET_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD0" "SHIELD0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD1" "SHIELD1" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD2" "SHIELD2" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD3" "SHIELD3" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD4" "SHIELD4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD5" "SHIELD5" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD6" "SHIELD6" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:SHIELD7" "SHIELD7" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_DDR4_C0_0:WE_N" "WE_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:REF_CLK" "PF_XCVR_ERM_C1_0:LANE0_CDR_REF_CLK_0" "PF_XCVR_REF_CLK_C0_0:REF_CLK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_N" "REF_CLK_PAD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_XCVR_REF_CLK_C0_0:REF_CLK_PAD_P" "REF_CLK_PAD_P" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:APB_CLK" "apb3_if_0:pclk_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:APB_Reset" "apb3_if_0:preset_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:TCK" "TCK" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:TDI" "TDI" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:TDO" "TDO" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:TMS" "TMS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:TRSTB" "TRSTB" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"RX" "UART_interface_0:RX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"TX" "UART_interface_0:TX" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:pip_select_o" "YCbCr_422to444_0:SWAP_Cb_Cr_I" "YCbCr_422to444_1pixel:SWAP_Cb_Cr_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_0:DATA_VALID_I" "YCbCr2RGB_C0_1:DATA_VALID_I" "YCbCr2RGB_C0_2:DATA_VALID_I" "YCbCr2RGB_C1_0:DATA_VALID_I" "YCbCr_422to444_0:DATA_VALID_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_3:DATA_VALID_I" "YCbCr_422to444_1pixel:DATA_VALID_O" }

# Add bus net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"A" "PF_DDR4_C0_0:A" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"BA" "PF_DDR4_C0_0:BA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"B_out_o" "Display_Controller_C3_0:DATA_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD" "IMX334_IF_TOP_0:CAM1_RXD" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"CAM1_RXD_N" "IMX334_IF_TOP_0:RXD_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_ADDR" "PF_DDR4_C0_0:l_addr_p0[35:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_B_SIZE" "PF_DDR4_C0_0:l_b_size_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_DATAIN" "PF_DDR4_C0_0:l_datain_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_DATAOUT" "PF_DDR4_C0_0:l_dataout" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:L_DM_IN" "PF_DDR4_C0_0:l_dm_in_p0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS1[9:2]" "DDR_Write_HDMI_RX_0:data_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS2[9:2]" "DDR_Write_HDMI_RX_0:data_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS3[9:2]" "DDR_Write_HDMI_RX_0:data_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS4[9:2]" "DDR_Write_HDMI_RX_0:data_i[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS5[9:2]" "DDR_Write_HDMI_RX_1:data_i[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS6[9:2]" "DDR_Write_HDMI_RX_1:data_i[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS7[9:2]" "DDR_Write_HDMI_RX_1:data_i[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_DATA_DS8[9:2]" "DDR_Write_HDMI_RX_1:data_i[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDIRX_C0_0:RX_SDI_DATA" "PF_XCVR_ERM_C1_0:LANE0_RX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS1" "SDI_interface_12G422_0:DS1_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS2" "SDI_interface_12G422_0:DS2_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS3" "SDI_interface_12G422_0:DS3_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS4" "SDI_interface_12G422_0:DS4_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS5" "SDI_interface_12G422_0:DS5_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS6" "SDI_interface_12G422_0:DS6_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS7" "SDI_interface_12G422_0:DS7_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_DATA_DS8" "SDI_interface_12G422_0:DS8_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREUHD_SDITX_C0_0:TX_SDI_DATA" "PF_XCVR_ERM_C1_0:LANE0_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_burst_size_i" "DDR_Read_HDMI_RX_0:beats_to_read_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r0_rstart_addr_i" "DDR_Read_HDMI_RX_0:read_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_burst_size_i" "DDR_Read_0:beats_to_read_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r1_rstart_addr_i" "DDR_Read_0:read_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_burst_size_i" "DDR_Read_1:beats_to_read_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r2_rstart_addr_i" "DDR_Read_1:read_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_burst_size_i" "DDR_Read_FHD_RX_0_0:beats_to_read_0[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:r3_rstart_addr_i" "DDR_Read_FHD_RX_0_0:read_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:rdata_o" "DDR_Read_0:wdata_i" "DDR_Read_1:wdata_i" "DDR_Read_FHD_RX_0_0:wdata_i" "DDR_Read_HDMI_RX_0:wdata_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_burst_size_i" "DDR_Write_HDMI_RX_0:beats_to_write_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_data_i" "DDR_Write_HDMI_RX_0:rdata_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w0_wstart_addr_i" "DDR_Write_HDMI_RX_0:write_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_burst_size_i" "DDR_Write_0:beats_to_write_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_data_i" "DDR_Write_0:rdata_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w1_wstart_addr_i" "DDR_Write_0:write_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_burst_size_i" "DDR_Write_HDMI_RX_1:beats_to_write_o[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_data_i" "DDR_Write_HDMI_RX_1:rdata_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_AXI4_ARBITER_PF_C0_0:w2_wstart_addr_i" "DDR_Write_HDMI_RX_1:write_start_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:bayer_data_o[15:8]" "SDI_interface_12G422_0:Cb11_I[9:2]" "SDI_interface_12G422_0:Cr11_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:bayer_data_o[23:16]" "SDI_interface_12G422_0:Y12_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:bayer_data_o[31:24]" "SDI_interface_12G422_0:Cb12_I[9:2]" "SDI_interface_12G422_0:Cr12_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:bayer_data_o[7:0]" "SDI_interface_12G422_0:Y11_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:frame_start_addr_i" "DDR_Read_1:frame_start_addr_i" "DDR_Write_0:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_0:horz_resl_i" "DDR_Read_1:horz_resl_i" "SDI_interface_12G422_0:H_RES_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_1:bayer_data_o[15:8]" "SDI_interface_12G422_0:Cb21_I[9:2]" "SDI_interface_12G422_0:Cr21_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_1:bayer_data_o[23:16]" "SDI_interface_12G422_0:Y22_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_1:bayer_data_o[31:24]" "SDI_interface_12G422_0:Cb22_I[9:2]" "SDI_interface_12G422_0:Cr22_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_1:bayer_data_o[7:0]" "SDI_interface_12G422_0:Y21_I[9:2]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:data_o[15:8]" "YCbCr_422to444_1pixel:C_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:data_o[7:0]" "YCbCr_422to444_1pixel:Y_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:frame_start_addr_i" "DDR_Read_HDMI_RX_0:frame_start_addr_i" "DDR_Write_HDMI_RX_0:display_frame_addr_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:h_pan_i" "UART_interface_0:h_pan_c1_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_FHD_RX_0_0:v_pan_i" "UART_interface_0:v_pan_c1_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[15:8]" "YCbCr_422to444_0:C_I[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[23:16]" "YCbCr_422to444_0:Y_I[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[31:24]" "YCbCr_422to444_0:C_I[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[39:32]" "YCbCr_422to444_0:Y_I[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[47:40]" "YCbCr_422to444_0:C_I[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[55:48]" "YCbCr_422to444_0:Y_I[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[63:56]" "YCbCr_422to444_0:C_I[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Read_HDMI_RX_0:data_o[7:0]" "YCbCr_422to444_0:Y_I[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:bayer_format" "UART_interface_0:bayer_format1_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DDR_Write_0:data_i" "IMX334_IF_TOP_0:c1_data_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DM_N" "PF_DDR4_C0_0:DM_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQ" "PF_DDR4_C0_0:DQ" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS" "PF_DDR4_C0_0:DQS" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"DQS_N" "PF_DDR4_C0_0:DQS_N" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[15:8]" "Image_Enhancement_C0_2:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[23:16]" "Image_Enhancement_C0_3:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[31:24]" "Image_Enhancement_C0_4:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[39:32]" "Image_Enhancement_C0_1:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[47:40]" "Image_Enhancement_C0_2:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[55:48]" "Image_Enhancement_C0_3:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[63:56]" "Image_Enhancement_C0_4:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[71:64]" "Image_Enhancement_C0_1:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[79:72]" "Image_Enhancement_C0_2:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[7:0]" "Image_Enhancement_C0_1:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[87:80]" "Image_Enhancement_C0_3:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_I[95:88]" "Image_Enhancement_C0_4:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[15:8]" "HDMI_TX_C0_0:DATA_B_I[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[23:16]" "HDMI_TX_C0_0:DATA_B_I[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[31:24]" "HDMI_TX_C0_0:DATA_B_I[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[39:32]" "HDMI_TX_C0_0:DATA_G_I[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[47:40]" "HDMI_TX_C0_0:DATA_G_I[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[55:48]" "HDMI_TX_C0_0:DATA_G_I[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[63:56]" "HDMI_TX_C0_0:DATA_G_I[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[71:64]" "HDMI_TX_C0_0:DATA_R_I[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[79:72]" "HDMI_TX_C0_0:DATA_R_I[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[7:0]" "HDMI_TX_C0_0:DATA_B_I[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[87:80]" "HDMI_TX_C0_0:DATA_R_I[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C2_0:DATA_O[95:88]" "HDMI_TX_C0_0:DATA_R_I[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_I[15:8]" "Image_Enhancement_C0_0:G_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_I[23:16]" "Image_Enhancement_C0_0:R_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_I[7:0]" "Image_Enhancement_C0_0:B_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_O[15:8]" "G_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Display_Controller_C3_0:DATA_O[23:16]" "R_out_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"GPIO_OUT_0" "PROC_SUBSYSTEM_0:GPIO_OUT_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:BLUE_I" "YCbCr2RGB_C0_3:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:BLUE_O" "Image_Enhancement_C0_0:B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:GREEN_I" "YCbCr2RGB_C0_3:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:GREEN_O" "Image_Enhancement_C0_0:G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:RED_I" "YCbCr2RGB_C0_3:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C0_0:RED_O" "Image_Enhancement_C0_0:R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:BLUE_I" "YCbCr2RGB_C0_0:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:BLUE_O" "Image_Enhancement_C0_1:B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:GREEN_I" "YCbCr2RGB_C0_0:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:GREEN_O" "Image_Enhancement_C0_1:G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:RED_I" "YCbCr2RGB_C0_0:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C1_0:RED_O" "Image_Enhancement_C0_1:R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:BLUE_I" "YCbCr2RGB_C1_0:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:BLUE_O" "Image_Enhancement_C0_2:B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:GREEN_I" "YCbCr2RGB_C1_0:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:GREEN_O" "Image_Enhancement_C0_2:G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:RED_I" "YCbCr2RGB_C1_0:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C2_0:RED_O" "Image_Enhancement_C0_2:R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:BLUE_I" "YCbCr2RGB_C0_1:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:BLUE_O" "Image_Enhancement_C0_3:B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:GREEN_I" "YCbCr2RGB_C0_1:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:GREEN_O" "Image_Enhancement_C0_3:G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:RED_I" "YCbCr2RGB_C0_1:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C3_0:RED_O" "Image_Enhancement_C0_3:R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:BLUE_I" "YCbCr2RGB_C0_2:BLUE_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:BLUE_O" "Image_Enhancement_C0_4:B_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:GREEN_I" "YCbCr2RGB_C0_2:GREEN_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:GREEN_O" "Image_Enhancement_C0_4:G_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:RED_I" "YCbCr2RGB_C0_2:RED_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Gamma_Correction_C4_0:RED_O" "Image_Enhancement_C0_4:R_I" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_B_O" "PF_XCVR_ERM_C0_0:LANE3_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_G_O" "PF_XCVR_ERM_C0_0:LANE2_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"HDMI_TX_C0_0:TMDS_R_O" "PF_XCVR_ERM_C0_0:LANE1_TX_DATA" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:B_CONST_I" "Image_Enhancement_C0_1:B_CONST_I" "Image_Enhancement_C0_2:B_CONST_I" "Image_Enhancement_C0_3:B_CONST_I" "Image_Enhancement_C0_4:B_CONST_I" "apb3_if_0:bconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:COMMON_CONST_I" "Image_Enhancement_C0_1:COMMON_CONST_I" "Image_Enhancement_C0_2:COMMON_CONST_I" "Image_Enhancement_C0_3:COMMON_CONST_I" "Image_Enhancement_C0_4:COMMON_CONST_I" "apb3_if_0:second_const_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:G_CONST_I" "Image_Enhancement_C0_1:G_CONST_I" "Image_Enhancement_C0_2:G_CONST_I" "Image_Enhancement_C0_3:G_CONST_I" "Image_Enhancement_C0_4:G_CONST_I" "apb3_if_0:gconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"Image_Enhancement_C0_0:R_CONST_I" "Image_Enhancement_C0_1:R_CONST_I" "Image_Enhancement_C0_2:R_CONST_I" "Image_Enhancement_C0_3:R_CONST_I" "Image_Enhancement_C0_4:R_CONST_I" "apb3_if_0:rconst_o" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:bgain_o" "apb3_if_0:b_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:brightness_o" "apb3_if_0:brightness_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:contrast_o" "apb3_if_0:contrast_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:ggain_o" "apb3_if_0:g_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"UART_interface_0:rgain_o" "apb3_if_0:r_gain_i" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_0:Cb_IN" "YCbCr_422to444_0:Cb_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_0:Cr_IN" "YCbCr_422to444_0:Cr_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_0:Y_IN" "YCbCr_422to444_0:Y_O[7:0]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_1:Cb_IN" "YCbCr_422to444_0:Cb_O[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_1:Cr_IN" "YCbCr_422to444_0:Cr_O[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_1:Y_IN" "YCbCr_422to444_0:Y_O[23:16]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_2:Cb_IN" "YCbCr_422to444_0:Cb_O[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_2:Cr_IN" "YCbCr_422to444_0:Cr_O[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_2:Y_IN" "YCbCr_422to444_0:Y_O[31:24]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_3:Cb_IN" "YCbCr_422to444_1pixel:Cb_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_3:Cr_IN" "YCbCr_422to444_1pixel:Cr_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C0_3:Y_IN" "YCbCr_422to444_1pixel:Y_O" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C1_0:Cb_IN" "YCbCr_422to444_0:Cb_O[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C1_0:Cr_IN" "YCbCr_422to444_0:Cr_O[15:8]" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"YCbCr2RGB_C1_0:Y_IN" "YCbCr_422to444_0:Y_O[15:8]" }

# Add bus interface net connections
sd_connect_pins -sd_name ${sd_name} -pin_names {"COREDDR_LITEAXI_C0_0:AXI4_SLAVE" "DDR_AXI4_ARBITER_PF_C0_0:MIRRORED_SLAVE_AXI4" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C0_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C0_0:CLKS_FROM_TXPLL_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_TX_PLL_C1_0:CLKS_TO_XCVR" "PF_XCVR_ERM_C1_0:CLKS_FROM_TXPLL_0" }
sd_connect_pins -sd_name ${sd_name} -pin_names {"PROC_SUBSYSTEM_0:APBmslave9" "apb3_if_0:APB_IF" }

# Re-enable auto promotion of pins of type 'pad'
auto_promote_pad_pins -promote_all 1
# Save the smartDesign
save_smartdesign -sd_name ${sd_name}
# Generate SmartDesign VIDEO_KIT_TOP
generate_component -component_name ${sd_name}
