--=================================================================================================
-- File Name                           : SDI_interface_12G422.vhd


-- Targeted device                     : Microchip-SoC
-- Author                              : India Solutions Team
--
-- COPYRIGHT 2022 BY MICROCHIP
-- THE INFORMATION CONTAINED IN THIS DOCUMENT IS SUBJECT TO LICENSING RESTRICTIONS FROM MICROCHIP
-- CORP. IF YOU ARE NOT IN POSSESSION OF WRITTEN AUTHORIZATION FROM MICROCHIP FOR USE OF THIS
-- FILE, THEN THE FILE SHOULD BE IMMEDIATELY DESTROYED AND NO BACK-UP OF THE FILE SHOULD BE MADE.
--
--=================================================================================================

--=================================================================================================
-- Libraries
--=================================================================================================
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_SIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

--=================================================================================================
-- Display_Controller_hdmi entity declaration
--=================================================================================================
ENTITY SDI_interface_12G422 IS

PORT(
-- Port list
    -- System reset
    RESETN_I                            : IN STD_LOGIC;
    
    -- System clock
    SYS_CLK_I                                 : IN STD_LOGIC;
    
    -- enable
    ENABLE_I                            : IN STD_LOGIC;

    -- enable external syncing
    ENABLE_EXT_SYNC_I                   : IN STD_LOGIC;

    -- external sync reference signal
    EXT_SYNC_SIGNAL_I                   : IN STD_LOGIC;

    -- Luminance data input         
    Y11_I                                              : IN STD_LOGIC_VECTOR(9 DOWNTO 0);               

    -- Chroma data input 
    Cb11_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 

    Cr11_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Luminance data input         
    Y12_I                                              : IN STD_LOGIC_VECTOR(9 DOWNTO 0);               

    -- Chroma data input 
    Cb12_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0); 

    Cr12_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Luminance data input         
    Y21_I                                              : IN STD_LOGIC_VECTOR(9 DOWNTO 0);               

    -- Chroma data input 
    Cb21_I                                            : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    Cr21_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Luminance data input         
    Y22_I                                              : IN STD_LOGIC_VECTOR(9 DOWNTO 0);               

    -- Chroma data input 
    Cb22_I                                            : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    Cr22_I                                           : IN STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Data stream1
    DS1_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Data stream2
    DS2_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);  

    -- Data stream3
    DS3_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Data stream4
    DS4_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);        

    -- Data stream5
    DS5_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Data stream6
    DS6_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);  

    -- Data stream7
    DS7_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);

    -- Data stream8
    DS8_O                                                        : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); 

    -- Data trigger
    DATA_TRIGGER_O                                  : OUT STD_LOGIC;

    -- Frame end
    FRAME_END_O                                  : OUT STD_LOGIC;

    -- Data Enable
    DATA_ENABLE_O                                   : OUT STD_LOGIC;

    --Horizontal Resolution
    H_RES_O                             : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)

);
END SDI_interface_12G422;

--=================================================================================================
-- SDI_interface_12G422_YCbCr architecture body
--=================================================================================================

ARCHITECTURE SDI_interface_12G422 OF SDI_interface_12G422 IS

--=================================================================================================
-- Component declarations
--=================================================================================================
--NA--
--=================================================================================================
-- Synthesis Attributes
--=================================================================================================
--NA--
--=================================================================================================
-- Signal declarations
--=================================================================================================

       constant SDI_3FF               : std_logic_vector(9 downto 0) := "1111111111";
       constant SDI_000               : std_logic_vector(9 downto 0) := "0000000000";
       constant LN0_DSx               : std_logic_vector(9 downto 0) := "01"&x"00";
       constant LN1_DSx               : std_logic_vector(9 downto 0) := "01"&x"00";
       constant CRC_DSx               : std_logic_vector(9 downto 0) := "01"&x"00";
       constant ANC_C_DS_DATA       : std_logic_vector(9 downto 0) := "10"&x"00";
       constant ANC_Y_DS_DATA       : std_logic_vector(9 downto 0) := "00"&x"40";

       type sdi_state is        (pg_idle1_st,
       sav1_t1_st,  sav1_t2_st, 
       sav2_t1_st,  sav2_t2_st, 
       sav3_t1_st,  sav3_t2_st, 
       sav4_t1_st,  sav4_t2_st, 
       eav1_t1_st,  eav1_t2_st, 
       eav2_t1_st,  eav2_t2_st, 
       eav3_t1_st,  eav3_t2_st, 
       eav4_t1_st,  eav4_t2_st, 
       ln0_t1_st,   ln0_t2_st, 
       ln1_t1_st,   ln1_t2_st, 
       cr0_t1_st,   cr0_t2_st, 
       cr1_t1_st,   cr1_t2_st, 
       hanc_t1_st,  hanc_t2_st, 
       vanc_t1_st,  vanc_t2_st, 
       av_t1_st,    av_t2_st);

       signal fsm_state                             : sdi_state;
       SIGNAL s_h_activex                      : STD_LOGIC;       
       SIGNAL s_h_active                      : STD_LOGIC;       
       SIGNAL s_h_active_early               : STD_LOGIC;       
       SIGNAL s_v_activex                      : STD_LOGIC;       
       SIGNAL s_v_active                      : STD_LOGIC;       
       SIGNAL s_h_active_dly               : STD_LOGIC;       
       SIGNAL s_h_activex_dly               : STD_LOGIC;       
       SIGNAL s_h_active_fe               : STD_LOGIC;       
       SIGNAL s_h_activex_fe               : STD_LOGIC;       
       SIGNAL s_h_bit                                : STD_LOGIC;
       SIGNAL s_v_bit                                : STD_LOGIC;
       SIGNAL s_f_bit                                : STD_LOGIC;
       SIGNAL data_trigger_dly              : STD_LOGIC;
       SIGNAL data_trigger_dly1              : STD_LOGIC;
       SIGNAL data_trigger_re              : STD_LOGIC;
       SIGNAL second_line_detect             : STD_LOGIC;
       SIGNAL delay_adjust_en              : STD_LOGIC;
       SIGNAL delay_adjust_done              : STD_LOGIC;

       SIGNAL s_h_counterx             : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_h_counter              : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_v_counterx             : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_v_counter              : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_h_resolution           : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_v_resolution           : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_h_blank                : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_v_blank                : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_h_total                     : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL s_v_total                     : STD_LOGIC_VECTOR(15 DOWNTO 0);
       SIGNAL XYZ_DSx                                   : STD_LOGIC_VECTOR (9 DOWNTO 0);
       SIGNAL s_h_delay_counter        : STD_LOGIC_VECTOR (9 DOWNTO 0);
       SIGNAL s_h_data_delay_counter   : STD_LOGIC_VECTOR (9 DOWNTO 0);


BEGIN

--=================================================================================================
-- Top level output port assignments
--=================================================================================================

       DATA_TRIGGER_O       <= s_h_active_early AND s_v_active;
       DATA_ENABLE_O       <= s_h_activex AND s_v_activex;
       H_RES_O         <= s_h_resolution(14 DOWNTO 0) & '0';
       FRAME_END_O              <= '1' WHEN s_v_counter = x"0001" ELSE '0';

--=================================================================================================
-- Generate blocks
--=================================================================================================
--------------------------------------------------------------------------
-- Name       : Resolution definition
-- Description: Definition of various resolutions
--------------------------------------------------------------------------

       s_h_resolution       <= x"0780"; -- x"0F00" Divide by 2
       s_v_resolution       <= x"0438";
       s_h_blank          <= x"0118"; -- x"0230" Divide  by 2
       s_v_blank            <= x"002D";

--=================================================================================================
-- Asynchronous blocks
--=================================================================================================
-- Events for Generating sync pulses

       s_h_total              <= s_h_resolution + s_h_blank - 1;
       s_v_total              <= s_v_resolution + s_v_blank - 1;

       s_f_bit                     <= '0';       -- Progressive scanning
       s_v_bit                     <= NOT(s_v_activex);
       XYZ_DSx               <= '1' & s_f_bit & s_v_bit & s_h_bit &      --  '1' 'F' 'V' 'H' 
                   (s_v_bit xor s_h_bit) &                 -- 'P3'
                   (s_f_bit xor s_h_bit) &                 -- 'P2'
                   (s_f_bit xor s_v_bit) &                 -- 'P1'
                   (s_f_bit xor s_v_bit xor s_h_bit) & "00"; -- 'P0' '0' '0'

--=================================================================================================
-- Synchronous blocks
--=================================================================================================
--------------------------------------------------------------------------
-- Name       : SECOND_LINE_DETECT_CHK
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       SECOND_LINE_DETECT_CHK :
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     second_line_detect <= '0' ;
                     data_trigger_dly <= '0' ;
                     data_trigger_dly1 <= '0' ;
                     data_trigger_re <= '0' ;
              ELSIF rising_edge(SYS_CLK_I) THEN
                     data_trigger_dly <= s_h_active_early AND s_v_active;
                     data_trigger_dly1 <= data_trigger_dly ;
                     data_trigger_re   <= data_trigger_dly AND NOT(data_trigger_dly1) ;
                     IF(EXT_SYNC_SIGNAL_I = '1')THEN
                            second_line_detect <= '1' ;
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : DELAY_ADJUST
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       DELAY_ADJUST :
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     delay_adjust_en <= '0' ;
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(second_line_detect = '1' AND data_trigger_re = '1' AND delay_adjust_done = '0' )THEN
                            delay_adjust_en <= '1' ;
                     ELSIF (delay_adjust_done = '1') THEN
                            delay_adjust_en <= '0' ;
                     END IF;
              END IF;
       END PROCESS;


--------------------------------------------------------------------------
-- Name       : DELAY_ADJUST_SDI
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       DELAY_ADJUST_SDI :
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     delay_adjust_done <= '0' ;
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(EXT_SYNC_SIGNAL_I = '1' AND delay_adjust_en = '1')THEN
                            delay_adjust_done <= '1' ;
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : DATA_DELAY_COUNTER
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       DATA_DELAY_COUNTER:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_data_delay_counter <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(ENABLE_EXT_SYNC_I = '1')THEN
                            IF(delay_adjust_en = '1') THEN
                                   s_h_data_delay_counter <= s_h_data_delay_counter + '1';
                            END IF;
                     ELSE
                            s_h_data_delay_counter <= (OTHERS=>'0');
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : DELAY_COUNTER
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       DELAY_COUNTER:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_delay_counter <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(delay_adjust_done = '1')THEN
                            s_h_delay_counter <= s_h_data_delay_counter + x"2";
                     ELSE
                            s_h_delay_counter <= (OTHERS=>'0');
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : H_COUNTER
-- Description: Counter for horizontal line generation
--------------------------------------------------------------------------
       H_COUNTER:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_counter <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(ENABLE_I = '1')THEN
                            IF(s_h_counter < s_h_total) THEN
                                   s_h_counter <= s_h_counter + '1';
                            ELSE
                                   s_h_counter <= (OTHERS=>'0');
                            END IF;
                     ELSE
                            s_h_counter <= (OTHERS=>'0');
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : H_TIMIMG_GEN
-- Description: Timing signals based on horizontal counter
--------------------------------------------------------------------------
       H_TIMIMG_GEN:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_active  <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(s_h_counter < s_h_blank) THEN
                            s_h_active        <= '0';
                     ELSE
                            s_h_active        <= '1';
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : H_TIMIMG_GEN_EARLY
-- Description: Timing signals based on horizontal counter
--------------------------------------------------------------------------
       H_TIMIMG_GEN_EARLY:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_active_early  <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(s_h_counter < (s_h_blank - s_h_delay_counter) OR s_h_counter > (s_h_total - s_h_delay_counter - '1')) THEN
                            s_h_active_early        <= '0';
                     ELSE
                            s_h_active_early        <= '1';
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : V_COUNTER
-- Description: Counter for vertical line generation
--------------------------------------------------------------------------
       V_COUNTER:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_active_dly       <= '0';
                     s_h_active_fe              <= '0';
                     s_v_counter              <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     s_h_active_dly       <= s_h_active;
                     s_h_active_fe              <= NOT(s_h_active) AND (s_h_active_dly);
                     IF(ENABLE_I = '1')THEN
                            IF(s_h_active_fe = '1') THEN
                                   IF(s_v_counter < s_v_total) THEN
                                          s_v_counter <= s_v_counter + '1';
                                   ELSE
                                          s_v_counter <= (OTHERS=>'0');
                                   END IF;
                            END IF;
                     ELSE
                            s_v_counter <= (OTHERS=>'0');
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : V_TIMIMG_GEN
-- Description: Timing signals based on vertical counter
--------------------------------------------------------------------------
       V_TIMIMG_GEN:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_v_active  <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN       
                     IF(s_v_counter < s_v_blank) THEN
                            s_v_active        <= '0';
                     ELSE
                            s_v_active        <= '1';
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : H_COUNTER_EXT_SYNC
-- Description: Counter to detect external horizontal line generation
--------------------------------------------------------------------------
       H_COUNTER_EXT_SYNC:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_counterx <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(ENABLE_I = '1')THEN
                            IF(s_h_counterx < s_h_total) THEN
                                   s_h_counterx <= s_h_counterx + '1';
                            ELSE
                                   s_h_counterx <= (OTHERS=>'0');
                            END IF;
                     ELSE
                            s_h_counterx <= (OTHERS=>'0');
                     END IF;
              END IF;
       END PROCESS;

--------------------------------------------------------------------------
-- Name       : H_TIMIMG_GEN_EXT_SYNC
-- Description: Timing signals based on external horizontal counter
--------------------------------------------------------------------------
       H_TIMIMG_GEN_EXT_SYNC:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_activex         <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN
                     IF(s_h_counterx < s_h_blank) THEN
                            s_h_activex       <= '0';
                     ELSE
                            s_h_activex       <= '1';
                     END IF;
              END IF;
       END PROCESS;              

--------------------------------------------------------------------------
-- Name       : V_COUNTER_EXT_SYNC
-- Description: Counter to detect external vertical line generation
--------------------------------------------------------------------------
       V_COUNTER_EXT_SYNC:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_h_activex_dly       <= '0';
                     s_h_activex_fe       <= '0';
                     s_v_counterx       <= (OTHERS=>'0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     s_h_activex_dly       <= s_h_activex;
                     s_h_activex_fe              <= NOT(s_h_activex) AND (s_h_activex_dly);
                     IF(ENABLE_I = '1')THEN
                            IF(s_h_activex_fe = '1') THEN
                                   IF(s_v_counterx < s_v_total) THEN
                                          s_v_counterx <= s_v_counterx + '1';
                                   ELSE
                                          s_v_counterx <= (OTHERS=>'0');
                                   END IF;
                            END IF;                            
                     ELSE
                            s_v_counterx <= s_v_blank - '1';
                     END IF;
              END IF;
       END PROCESS;


       --------------------------------------------------------------------------
       -- Name       : V_TIMIMG_GEN_EXT_SYNC
       -- Description: Timing signals based on external vertical counter
       --------------------------------------------------------------------------
       V_TIMIMG_GEN_EXT_SYNC:
       PROCESS(SYS_CLK_I,RESETN_I)
       BEGIN
              IF RESETN_I = '0' THEN
                     s_v_activex  <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN       
                     IF(s_v_counterx < s_v_blank) THEN
                            s_v_activex <= '0';
                     ELSE
                            s_v_activex <= '1';
                     END IF;
              END IF;
       END PROCESS;

       --------------------------------------------------------------------------
       -- Description: FSM for generating SDI codes in blanking period
       --------------------------------------------------------------------------       
       pg_state_update: process(SYS_CLK_I, RESETN_I)
       begin
              IF(RESETN_I = '0') THEN
                     fsm_state <= pg_idle1_st;
              ELSIF rising_edge(SYS_CLK_I) THEN
                     case fsm_state is
                            -- idle states
                            when pg_idle1_st =>
                                   fsm_state <= eav1_t1_st;

                            -- eav states
                            when eav1_t1_st =>
                                   fsm_state <= eav2_t1_st;                            

                            when eav2_t1_st =>
                                   fsm_state <= eav3_t1_st;                            

                            when eav3_t1_st =>
                                   fsm_state <= eav4_t1_st;

                            when eav4_t1_st =>
                                   fsm_state <= ln0_t1_st;

                            -- line number states
                            when ln0_t1_st =>
                                   fsm_state <= ln1_t1_st;

                            when ln1_t1_st =>
                                   fsm_state <= cr0_t1_st;

                            -- crc states
                            when cr0_t1_st =>
                                   fsm_state <= cr1_t1_st;

                            when cr1_t1_st =>
                                   fsm_state <= hanc_t1_st;

                            -- hanc states                                   
                            when hanc_t1_st =>
                                   if(s_h_counterx = (s_h_blank  - x"0003")) then
                                          fsm_state <= sav1_t1_st;
                                   else
                                          fsm_state <= hanc_t1_st;
                                   end if;

                            -- SAV states
                            when sav1_t1_st =>
                                   fsm_state <= sav2_t1_st;

                            when sav2_t1_st =>
                                   fsm_state <= sav3_t1_st;

                            when sav3_t1_st =>
                                   fsm_state <= sav4_t1_st;

                            when sav4_t1_st =>
                                   if(s_v_activex = '0') then
                                          fsm_state <= vanc_t1_st;
                                   else
                                          fsm_state <= av_t1_st;
                                   end if;

                            -- vanc states
                            when vanc_t1_st =>
                                   if(s_h_activex = '0') then
                                          fsm_state <= eav1_t1_st;
                                   else
                                          fsm_state <= vanc_t1_st;
                                   end if;

                            -- av states
                            when av_t1_st =>
                                   if(s_h_activex = '0') then
                                          fsm_state <= eav1_t1_st;
                                   else
                                          fsm_state <= av_t1_st;
                                   end if;

                            when others => 
                                   fsm_state <= pg_idle1_st;
                     end case;
              end if;
       end process;

       --------------------------------------------------------------------------
       -- Description: Generation of s_h_bit
       --------------------------------------------------------------------------              

       h_bit_gen: process(SYS_CLK_I, RESETN_I)
       begin
              IF(RESETN_I = '0') THEN
                     s_h_bit <= '0';
              ELSIF rising_edge(SYS_CLK_I) THEN
                     if(fsm_state = eav1_t1_st) then
                            s_h_bit <= '1';
                     elsif(fsm_state = sav1_t1_st) then
                            s_h_bit <= '0';
                     end if;
              end if;
       end process;

       ds_cy_gen: process(SYS_CLK_I, RESETN_I)
       begin
              IF(RESETN_I = '0') THEN
                     DS1_O <= (others => '0');
                     DS2_O <= (others => '0');
                     DS3_O <= (others => '0');
                     DS4_O <= (others => '0');
                     DS5_O <= (others => '0');
                     DS6_O <= (others => '0');
                     DS7_O <= (others => '0');
                     DS8_O <= (others => '0');
              ELSIF rising_edge(SYS_CLK_I) THEN
                     case fsm_state is
                            when pg_idle1_st => 
                                   DS1_O <= (others => '0');
                                   DS2_O <= (others => '0');
                                   DS3_O <= (others => '0');
                                   DS4_O <= (others => '0');
                                   DS5_O <= (others => '0');
                                   DS6_O <= (others => '0');
                                   DS7_O <= (others => '0');
                                   DS8_O <= (others => '0');
                            when eav1_t1_st | eav1_t2_st | sav1_t1_st | sav1_t2_st =>
                                   DS1_O <= SDI_3FF; -- 3FF(Y) 
                                   DS2_O <= SDI_3FF; -- 3FF(C) 
                                   DS3_O <= SDI_3FF; -- 3FF(Y) 
                                   DS4_O <= SDI_3FF; -- 3FF(C) 
                                   DS5_O <= SDI_3FF; -- 3FF(Y) 
                                   DS6_O <= SDI_3FF; -- 3FF(C) 
                                   DS7_O <= SDI_3FF; -- 3FF(Y) 
                                   DS8_O <= SDI_3FF; -- 3FF(C) 
                            when eav2_t1_st | eav2_t2_st | sav2_t1_st | sav2_t2_st =>
                                   DS1_O <= SDI_000; -- 000(Y)
                                   DS2_O <= SDI_000; -- 000(C)
                                   DS3_O <= SDI_000; -- 000(Y)
                                   DS4_O <= SDI_000; -- 000(C)
                                   DS5_O <= SDI_000; -- 000(Y)
                                   DS6_O <= SDI_000; -- 000(C)
                                   DS7_O <= SDI_000; -- 000(Y)
                                   DS8_O <= SDI_000; -- 000(C)
                            when eav3_t1_st | eav3_t2_st | sav3_t1_st | sav3_t2_st =>
                                   DS1_O <= SDI_000; -- 000(Y)
                                   DS2_O <= SDI_000; -- 000(C)
                                   DS3_O <= SDI_000; -- 000(Y)
                                   DS4_O <= SDI_000; -- 000(C)
                                   DS5_O <= SDI_000; -- 000(Y)
                                   DS6_O <= SDI_000; -- 000(C)
                                   DS7_O <= SDI_000; -- 000(Y)
                                   DS8_O <= SDI_000; -- 000(C)
                            when eav4_t1_st | eav4_t2_st | sav4_t1_st | sav4_t2_st =>
                                   DS1_O <= XYZ_DSx; -- XYZ(Y)
                                   DS2_O <= XYZ_DSx; -- XYZ(C)
                                   DS3_O <= XYZ_DSx; -- XYZ(Y)
                                   DS4_O <= XYZ_DSx; -- XYZ(C)
                                   DS5_O <= XYZ_DSx; -- XYZ(Y)
                                   DS6_O <= XYZ_DSx; -- XYZ(C)
                                   DS7_O <= XYZ_DSx; -- XYZ(Y)
                                   DS8_O <= XYZ_DSx; -- XYZ(C)
                            when  ln0_t1_st |  ln0_t2_st  =>
                                   DS1_O <= LN0_DSx; -- LN0
                                   DS2_O <= LN0_DSx; -- LN0
                                   DS3_O <= LN0_DSx; -- LN0
                                   DS4_O <= LN0_DSx; -- LN0
                                   DS5_O <= LN0_DSx; -- LN0
                                   DS6_O <= LN0_DSx; -- LN0
                                   DS7_O <= LN0_DSx; -- LN0
                                   DS8_O <= LN0_DSx; -- LN0
                            when  ln1_t1_st |  ln1_t2_st  =>
                                   DS1_O <= LN1_DSx; -- LN1
                                   DS2_O <= LN1_DSx; -- LN1
                                   DS3_O <= LN1_DSx; -- LN1
                                   DS4_O <= LN1_DSx; -- LN1
                                   DS5_O <= LN1_DSx; -- LN1
                                   DS6_O <= LN1_DSx; -- LN1
                                   DS7_O <= LN1_DSx; -- LN1
                                   DS8_O <= LN1_DSx; -- LN1
                            when  cr0_t1_st |  cr0_t2_st |  cr1_t1_st |  cr1_t2_st =>
                                   DS1_O <= CRC_DSx; -- CRC(Y)
                                   DS2_O <= CRC_DSx; -- CRC(C)
                                   DS3_O <= CRC_DSx; -- CRC(Y)
                                   DS4_O <= CRC_DSx; -- CRC(C)
                                   DS5_O <= CRC_DSx; -- CRC(Y)
                                   DS6_O <= CRC_DSx; -- CRC(C)
                                   DS7_O <= CRC_DSx; -- CRC(Y)
                                   DS8_O <= CRC_DSx; -- CRC(C)
                            when hanc_t1_st | vanc_t1_st =>
                                   DS1_O <= ANC_Y_DS_DATA; -- ANC(Y)
                                   DS2_O <= ANC_C_DS_DATA; -- ANC(C)
                                   DS3_O <= ANC_Y_DS_DATA; -- ANC(Y)
                                   DS4_O <= ANC_C_DS_DATA; -- ANC(C)
                                   DS5_O <= ANC_Y_DS_DATA; -- ANC(Y)
                                   DS6_O <= ANC_C_DS_DATA; -- ANC(C)
                                   DS7_O <= ANC_Y_DS_DATA; -- ANC(Y)
                                   DS8_O <= ANC_C_DS_DATA; -- ANC(C)
                            when av_t1_st =>                            
                                   if (s_h_counterx(0)='0') then  
                                          DS1_O <= Y11_I;
                                          DS2_O <= Cb11_I; 
                                          DS3_O <= Y12_I;
                                          DS4_O <= Cb12_I; 
                                          DS5_O <= Y21_I;
                                          DS6_O <= Cb21_I; 
                                          DS7_O <= Y22_I;
                                          DS8_O <= Cb22_I; 
                                   else
                                          DS1_O <= Y11_I;
                                          DS2_O <= Cr11_I; 
                                          DS3_O <= Y12_I;
                                          DS4_O <= Cr12_I; 
                                          DS5_O <= Y21_I;
                                          DS6_O <= Cr21_I; 
                                          DS7_O <= Y22_I;
                                          DS8_O <= Cr22_I; 
                                   end if;
                            when others => 
                                   DS1_O <= (others => '0');
                                   DS2_O <= (others => '0');
                                   DS3_O <= (others => '0');
                                   DS4_O <= (others => '0');
                                   DS5_O <= (others => '0');
                                   DS6_O <= (others => '0');
                                   DS7_O <= (others => '0');
                                   DS8_O <= (others => '0');
                     end case;
              end if;
       end process;

--=================================================================================================
-- Component Instantiations
--=================================================================================================
--NA--
END SDI_interface_12G422;
