
#####  START OF RAM REPORT  #####

#####  LSRAM REPORT  #####

INSTANTIATED     RTL_INSTANCE                                                                                                              PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE                                                                                                           DEPTH_X_WIDTH(A/B)     LOW-POWER_MODE     ECC     A_DOUT_PIPE_REG(EN/ARST/SRST)     B_DOUT_PIPE_REG(EN/ARST/SRST)     WRITE_MODE(A/B)          
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NO               CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil[35:0]                                                  RAM                DEFAULT            CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_0                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_1                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_2                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_3                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_4                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_5                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_6                                        4KX5_4KX5              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEo01lI.CORETSEIIil_CORETSEIIil_0_7                                        4KX4_4KX4              0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
NO               CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEl01lI.CORETSEIIil[39:0]                                                  RAM                DEFAULT            CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEl01lI.CORETSEIIil_CORETSEIIil_0_0                                        2KX10_2KX10            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEl01lI.CORETSEIIil_CORETSEIIil_0_1                                        2KX10_2KX10            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEl01lI.CORETSEIIil_CORETSEIIil_0_2                                        2KX10_2KX10            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEl01lI.CORETSEIIil_CORETSEIIil_0_3                                        2KX10_2KX10            0                  0       0(0/0/0)                          0(0/0/0)                          (WRITE_FIRST/WRITE_FIRST)
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R0C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R10C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R11C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R12C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R13C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R14C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R16C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R17C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R18C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R18C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R19C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R19C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R1C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R20C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R20C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R21C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R21C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R22C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R22C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R23C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R23C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R24C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R24C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R25C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R25C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R26C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R26C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R27C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R27C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R28C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R28C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R29C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R29C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R2C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R30C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R30C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0     NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0     512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R3C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R4C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R5C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R6C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R7C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R8C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
                                                                                                                                                                                                                                                                                                                                                                                                                                                          
YES              MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0      NA                 NA                 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R9C0      512X40_512X40          NA                 0       0(0/0/0)                          0(0/0/0)                          (NO_CHANGE/NO_CHANGE)    
==========================================================================================================================================================================================================================================================================================================================================================================================================================================================

#####  URAM REPORT  #####

INSTANTIATED     RTL_INSTANCE                                                                                                          PRIMITIVE_TYPE     USER_ATTRIBUTE     MAPPED_INSTANCE                                                                                                           DEPTH_X_WIDTH     LOW-POWER_MODE     ECC     R_ADDR_REG(EN/ARST/SRST)     R_DATA_PIPE_REG(EN/ARST/SRST)
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
NO               MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem[31:0]       RAM                DEFAULT            MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_mem_0_0         64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                             MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_mem_0_1         64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                             MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_mem_0_2         64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                                                                                                                                                                                                                                                              
NO               MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_1[31:0]     RAM                DEFAULT            MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_1_mem_1_0_0     64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                             MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_1_mem_1_0_1     64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                             MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.gen_gpr_ram\.u_gpr_0.gen_gpr\.u_gpr_array_0.mem_1_mem_1_0_2     64X12             0                  0       0(0/0/0)                     1(0/0/1)                     
                                                                                                                                                                                                                                                                                                                                                                                                              
NO               CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[15:0]                                                                    RAM                DEFAULT            CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_0                                                               64X12             0                  0       0(0/0/0)                     0(0/0/0)                     
                 CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q[16]                                                                      RAM                                   CORESPI_0_0.CORESPI_0_0.USPI.URXF.fifo_mem_q_fifo_mem_q_0_1                                                               64X12             0                  0       0(0/0/0)                     0(0/0/0)                     
                                                                                                                                                                                                                                                                                                                                                                                                              
NO               CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[15:0]                                                                    RAM                DEFAULT            CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_0                                                               64X12             0                  0       0(0/0/0)                     0(0/0/0)                     
                 CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q[16]                                                                      RAM                                   CORESPI_0_0.CORESPI_0_0.USPI.UTXF.fifo_mem_q_fifo_mem_q_0_1                                                               64X12             0                  0       0(0/0/0)                     0(0/0/0)                     
==============================================================================================================================================================================================================================================================================================================================================================================================================

#####  END OF RAM REPORT  #####

