#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: DESKTOP-3MQ3L41 # Thu Feb 25 12:40:26 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\polarfire_syn_comps.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_clockmux.v" (library CORESPI_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v" (library CORESPI_LIB) @W:CG1337 : spi_chanctrl.v(805) | Net resetn_rx_s is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_fifo.v" (library CORESPI_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v" (library CORESPI_LIB) @N:CG347 : spi_rf.v(160) | Read a parallel_case directive. @N:CG347 : spi_rf.v(223) | Read a parallel_case directive. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_control.v" (library CORESPI_LIB) @N:CG347 : spi_control.v(69) | Read a parallel_case directive. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v" (library CORESPI_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\corespi.v" (library CORESPI_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORESPI_0\CORESPI_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\rx4096x36.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_clkrst.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvrxi.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvrxo.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvtxi.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvtxo.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\peanx_sync.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\r10b8b.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v" (library work) @W:CG1337 : perex_pcs.v(662) | Net CORETSEI1li is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petbm.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\t8b10b.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petex_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_tbi.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_core.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif_clkrst.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif_hst.v" (library work) @W:CG1337 : amcxfif_hst.v(2346) | Net CORETSEiIIOI is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_sys.v" (library work) @W:CG1337 : amcxrfif_sys.v(1858) | Net CORETSEll0OI is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_fab.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_wtm.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\decoder.v" (library work) @I:"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\decoder.v":"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\include.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v" (library work) @W:CG1337 : tsm_sysreg.v(290) | Net CORETSEioil is not declared. @W:CG1337 : tsm_sysreg.v(305) | Net CORETSEOiil is not declared. @W:CG1337 : tsm_sysreg.v(387) | Net CORETSEol10 is not declared. @W:CG1337 : tsm_sysreg.v(407) | Net CORETSEil10 is not declared. @W:CG1337 : tsm_sysreg.v(427) | Net CORETSEO010 is not declared. @W:CG1337 : tsm_sysreg.v(447) | Net CORETSEI010 is not declared. @W:CG1337 : tsm_sysreg.v(467) | Net CORETSEl010 is not declared. @W:CG1337 : tsm_sysreg.v(487) | Net CORETSEo010 is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mmcxwol.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_eim.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_ladd.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_linc.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sadd.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sinchd.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sincnf.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sinc.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_store.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pecar.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemgt.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pecrc.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v" (library work) @W:CG1337 : perfn_top.v(2449) | Net CORETSEio1 is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\permc_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petmc_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac_core.v" (library work) @W:CG1337 : pe_mcxmac_core.v(1247) | Net CORETSEooI1 is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac.v" (library work) @W:CG1337 : pe_mcxmac.v(983) | Net CORETSEoOI1 is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\sib_sync_2flp.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\sib_sync_pulse.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\si_sal.v" (library work) @W:CG1337 : si_sal.v(935) | Net CORETSEIiil is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v" (library work) @W:CG1337 : tsmac_top.v(2145) | Net CORETSEIiolI is not declared. @W:CG1337 : tsmac_top.v(2152) | Net CORETSEliolI is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tx2048x40.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE.v" (library work) @W:CG1337 : CoreTSE.v(253) | Net CORETSEioil is not declared. @W:CG1337 : CoreTSE.v(268) | Net CORETSEOiil is not declared. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_muxptob3.v" (library COREAPB3_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3_iaddr_reg.v" (library COREAPB3_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v" (library COREAPB3_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreAPB3_0\CoreAPB3_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Clock_gen.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Rx_async.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\fifo_256x8_g5.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\Core_reset_pf\Core_reset_pf_0\core\corereset_pf.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\Core_reset_pf\Core_reset_pf.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_mnemonics_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_core_cfg_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_bist_shared_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_bist_seq_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v" (library work) @N:CG334 : miv_rv32_core_merged.v(18458) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(18491) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(18993) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(19009) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(19385) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(19438) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(22432) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(22440) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(22749) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(22757) | Read directive translate_on. @W:CS138 : miv_rv32_core_merged.v(23965) | Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine. @W:CS138 : miv_rv32_core_merged.v(23966) | Macro definition for RAM_BIST_VIEW not found. Cannot undefine. @N:CG334 : miv_rv32_core_merged.v(24190) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(24193) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(24203) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(24213) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(24218) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(24276) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(25152) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(25155) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(25165) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(25175) | Read directive translate_on. @N:CG334 : miv_rv32_core_merged.v(25180) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(25238) | Read directive translate_on. @W:CS141 : miv_rv32_core_merged.v(25840) | Unrecognized synthesis directive dc_script_begin. Verify the correct directive name. @W:CS141 : miv_rv32_core_merged.v(25843) | Unrecognized synthesis directive dc_script_end. Verify the correct directive name. @N:CG334 : miv_rv32_core_merged.v(25860) | Read directive translate_off. @N:CG333 : miv_rv32_core_merged.v(25862) | Read directive translate_on. @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_opsrv_debug_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_opsrv_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\miv_rv32_opsrv_cfg_pkg.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp_ecc.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_CCC_0\PF_CCC_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORECDR4_CNTL_TIP\2.0.100\rtl\vlog\core\corecdr4_cntl_tip.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_C0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREDELAYCODE_TIP\2.1.100\rtl\vlog\core\CoreDelayCode_TIP.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CLK_DIV_0\PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_IOD_CDR_CCC_C0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug_ujtag_wrapper.v" (library COREJTAGDEBUG_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug_bufd.v" (library COREJTAGDEBUG_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug_uj_jtag.v" (library COREJTAGDEBUG_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v" (library COREJTAGDEBUG_LIB) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\core_jatg_debug_0\core_jatg_debug_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0.v" (library work) @I::"F:\DG0799_final\Libero_Project\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! Options changed - recompiling @N:CG364 : miv_rv32_mnemonics_pkg.v(58) | Synthesizing module miv_rv32_mnemonic_pkg in library work. @N:CG364 : miv_rv32_pkg.v(74) | Synthesizing module miv_rv32_pkg in library work. @N:CG364 : miv_rv32_core_cfg_pkg.v(70) | Synthesizing module miv_rv32_core_cfg_pkg in library work. @N:CG364 : miv_rv32_bist_shared_pkg.v(166) | Synthesizing module miv_rv32_bist_shared_pkg in library work. @N:CG364 : miv_rv32_bist_seq_pkg.v(159) | Synthesizing module miv_rv32_bist_seq_pkg in library work. @N:CG364 : miv_rv32_opsrv_debug_pkg.v(67) | Synthesizing module miv_rv32_opsrv_debug_pkg in library work. @N:CG364 : miv_rv32_opsrv_pkg.v(69) | Synthesizing module miv_rv32_opsrv_pkg in library work. @N:CG364 : miv_rv32_opsrv_cfg_pkg.v(69) | Synthesizing module miv_rv32_opsrv_cfg_pkg in library work. @N:CG364 : miv_rv32_core_merged.v(314) | Synthesizing module work_F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v_unit in library work. @N:CG364 : miv_rv32_opsrv_merged.v(74) | Synthesizing module work_F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v_unit in library work. Selecting top level module top @N:CG364 : acg5.v(121) | Synthesizing module AND2 in library work. Running optimization stage 1 on AND2 ....... @N:CG364 : acg5.v(333) | Synthesizing module BIBUF in library work. Running optimization stage 1 on BIBUF ....... @N:CG775 : corejtagdebug.v(22) | Component COREJTAGDEBUG not found in library "work" or "__hyper__lib__", but found in library COREJTAGDEBUG_LIB @N:CG364 : corejtagdebug.v(22) | Synthesizing module COREJTAGDEBUG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 NUM_DEBUG_TGTS=32'b00000000000000000000000000000001 TGT_ACTIVE_HIGH_RESET_0=32'b00000000000000000000000000000000 IR_CODE_TGT_0=8'b01010101 TGT_ACTIVE_HIGH_RESET_1=32'b00000000000000000000000000000001 IR_CODE_TGT_1=8'b01010110 TGT_ACTIVE_HIGH_RESET_2=32'b00000000000000000000000000000001 IR_CODE_TGT_2=8'b01010111 TGT_ACTIVE_HIGH_RESET_3=32'b00000000000000000000000000000001 IR_CODE_TGT_3=8'b01011000 TGT_ACTIVE_HIGH_RESET_4=32'b00000000000000000000000000000001 IR_CODE_TGT_4=8'b01011001 TGT_ACTIVE_HIGH_RESET_5=32'b00000000000000000000000000000001 IR_CODE_TGT_5=8'b01011010 TGT_ACTIVE_HIGH_RESET_6=32'b00000000000000000000000000000001 IR_CODE_TGT_6=8'b01011011 TGT_ACTIVE_HIGH_RESET_7=32'b00000000000000000000000000000001 IR_CODE_TGT_7=8'b01011100 TGT_ACTIVE_HIGH_RESET_8=32'b00000000000000000000000000000001 IR_CODE_TGT_8=8'b01011101 TGT_ACTIVE_HIGH_RESET_9=32'b00000000000000000000000000000001 IR_CODE_TGT_9=8'b01011110 TGT_ACTIVE_HIGH_RESET_10=32'b00000000000000000000000000000001 IR_CODE_TGT_10=8'b01011111 TGT_ACTIVE_HIGH_RESET_11=32'b00000000000000000000000000000001 IR_CODE_TGT_11=8'b01100000 TGT_ACTIVE_HIGH_RESET_12=32'b00000000000000000000000000000001 IR_CODE_TGT_12=8'b01100001 TGT_ACTIVE_HIGH_RESET_13=32'b00000000000000000000000000000001 IR_CODE_TGT_13=8'b01100010 TGT_ACTIVE_HIGH_RESET_14=32'b00000000000000000000000000000001 IR_CODE_TGT_14=8'b01100011 TGT_ACTIVE_HIGH_RESET_15=32'b00000000000000000000000000000001 IR_CODE_TGT_15=8'b01100100 UJTAG_BYPASS=32'b00000000000000000000000000000000 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=128'b01100100011000110110001001100001011000000101111101011110010111010101110001011011010110100101100101011000010101110101011001010101 TGT_ACTIVE_HIGH_RESET=16'b1111111111111110 USE_NEW_UJTAG=32'b00000000000000000000000000000001 USE_UJTAG_WRAPPER=32'b00000000000000000000000000000000 Generated name = COREJTAGDEBUG_Z1 @N:CG364 : acg5.v(1442) | Synthesizing module UJTAG in library work. Running optimization stage 1 on UJTAG ....... @N:CG364 : corejtagdebug_bufd.v(20) | Synthesizing module corejtagdebug_bufd in library COREJTAGDEBUG_LIB. DELAY_NUM=32'b00000000000000000000000000100010 Generated name = corejtagdebug_bufd_34s @N:CG364 : acg5.v(229) | Synthesizing module BUFD in library work. Running optimization stage 1 on BUFD ....... Running optimization stage 1 on corejtagdebug_bufd_34s ....... @N:CG364 : corejtagdebug_uj_jtag.v(47) | Synthesizing module COREJTAGDEBUG_UJ_JTAG in library COREJTAGDEBUG_LIB. FAMILY=32'b00000000000000000000000000011010 SYNC_RESET=32'b00000000000000000000000000000000 DELAY_NUM=32'b00000000000000000000000000100010 IR_CODE_TGT=8'b01010101 NUM_LEAD_PAD_BITS=8'b00000000 NUM_TRAIL_PAD_BITS=8'b00000000 Generated name = COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 Running optimization stage 1 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... @N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @W:CG360 : corejtagdebug.v(147) | Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it. @W:CG360 : corejtagdebug.v(154) | Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it. @W:CG360 : corejtagdebug.v(161) | Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it. @W:CG360 : corejtagdebug.v(168) | Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it. @W:CG360 : corejtagdebug.v(218) | Removing wire iURSTB_inv, as there is no assignment to it. Running optimization stage 1 on COREJTAGDEBUG_Z1 ....... @N:CG364 : core_jatg_debug_0.v(55) | Synthesizing module core_jatg_debug_0 in library work. Running optimization stage 1 on core_jatg_debug_0 ....... @N:CG364 : corereset_pf.v(21) | Synthesizing module Core_reset_pf_Core_reset_pf_0_CORERESET_PF in library work. Running optimization stage 1 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... @N:CG364 : Core_reset_pf.v(21) | Synthesizing module Core_reset_pf in library work. Running optimization stage 1 on Core_reset_pf ....... @N:CG775 : coreapb3.v(31) | Component CoreAPB3 not found in library "work" or "__hyper__lib__", but found in library COREAPB3_LIB @N:CG364 : coreapb3_muxptob3.v(30) | Synthesizing module COREAPB3_MUXPTOB3 in library COREAPB3_LIB. Running optimization stage 1 on COREAPB3_MUXPTOB3 ....... @N:CG364 : coreapb3.v(31) | Synthesizing module CoreAPB3 in library COREAPB3_LIB. APB_DWIDTH=6'b100000 IADDR_OPTION=32'b00000000000000000000000000000000 APBSLOT0ENABLE=1'b1 APBSLOT1ENABLE=1'b1 APBSLOT2ENABLE=1'b1 APBSLOT3ENABLE=1'b0 APBSLOT4ENABLE=1'b0 APBSLOT5ENABLE=1'b0 APBSLOT6ENABLE=1'b0 APBSLOT7ENABLE=1'b0 APBSLOT8ENABLE=1'b0 APBSLOT9ENABLE=1'b0 APBSLOT10ENABLE=1'b0 APBSLOT11ENABLE=1'b0 APBSLOT12ENABLE=1'b0 APBSLOT13ENABLE=1'b0 APBSLOT14ENABLE=1'b0 APBSLOT15ENABLE=1'b0 SC_0=1'b0 SC_1=1'b0 SC_2=1'b0 SC_3=1'b0 SC_4=1'b0 SC_5=1'b0 SC_6=1'b0 SC_7=1'b0 SC_8=1'b0 SC_9=1'b0 SC_10=1'b0 SC_11=1'b0 SC_12=1'b0 SC_13=1'b0 SC_14=1'b0 SC_15=1'b0 MADDR_BITS=6'b010000 UPR_NIBBLE_POSN=4'b0110 FAMILY=32'b00000000000000000000000000010011 SYNC_RESET=32'b00000000000000000000000000000000 IADDR_NOTINUSE=32'b00000000000000000000000000000000 IADDR_EXTERNAL=32'b00000000000000000000000000000001 IADDR_SLOT0=32'b00000000000000000000000000000010 IADDR_SLOT1=32'b00000000000000000000000000000011 IADDR_SLOT2=32'b00000000000000000000000000000100 IADDR_SLOT3=32'b00000000000000000000000000000101 IADDR_SLOT4=32'b00000000000000000000000000000110 IADDR_SLOT5=32'b00000000000000000000000000000111 IADDR_SLOT6=32'b00000000000000000000000000001000 IADDR_SLOT7=32'b00000000000000000000000000001001 IADDR_SLOT8=32'b00000000000000000000000000001010 IADDR_SLOT9=32'b00000000000000000000000000001011 IADDR_SLOT10=32'b00000000000000000000000000001100 IADDR_SLOT11=32'b00000000000000000000000000001101 IADDR_SLOT12=32'b00000000000000000000000000001110 IADDR_SLOT13=32'b00000000000000000000000000001111 IADDR_SLOT14=32'b00000000000000000000000000010000 IADDR_SLOT15=32'b00000000000000000000000000010001 SL0=16'b0000000000000001 SL1=16'b0000000000000010 SL2=16'b0000000000000100 SL3=16'b0000000000000000 SL4=16'b0000000000000000 SL5=16'b0000000000000000 SL6=16'b0000000000000000 SL7=16'b0000000000000000 SL8=16'b0000000000000000 SL9=16'b0000000000000000 SL10=16'b0000000000000000 SL11=16'b0000000000000000 SL12=16'b0000000000000000 SL13=16'b0000000000000000 SL14=16'b0000000000000000 SL15=16'b0000000000000000 SC=16'b0000000000000000 SC_qual=16'b0000000000000000 Generated name = CoreAPB3_Z2 @W:CG360 : coreapb3.v(244) | Removing wire IA_PRDATA, as there is no assignment to it. Running optimization stage 1 on CoreAPB3_Z2 ....... @N:CG364 : CoreAPB3_0.v(57) | Synthesizing module CoreAPB3_0 in library work. Running optimization stage 1 on CoreAPB3_0 ....... @N:CG775 : corespi.v(27) | Component CORESPI not found in library "work" or "__hyper__lib__", but found in library CORESPI_LIB @N:CG364 : spi_rf.v(31) | Synthesizing module spi_rf in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000000111 ZEROS=32'b00000000000000000000000000000000 Generated name = spi_rf_32s_7s_0 Running optimization stage 1 on spi_rf_32s_7s_0 ....... @W:CL208 : spi_rf.v(134) | All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization. @N:CG364 : spi_control.v(24) | Synthesizing module spi_control in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 Generated name = spi_control_16s Running optimization stage 1 on spi_control_16s ....... @N:CG364 : spi_fifo.v(25) | Synthesizing module spi_fifo in library CORESPI_LIB. CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 PTR_WIDTH=32'b00000000000000000000000000000101 Generated name = spi_fifo_16s_32s_5 Running optimization stage 1 on spi_fifo_16s_32s_5 ....... @N:CG364 : spi_clockmux.v(24) | Synthesizing module spi_clockmux in library CORESPI_LIB. Running optimization stage 1 on spi_clockmux ....... @N:CG364 : spi_chanctrl.v(29) | Synthesizing module spi_chanctrl in library CORESPI_LIB. SPH=1'b0 SPO=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 CFG_CLKRATE=32'b00000000000000000000000000000111 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000000100 MTX_IDLE1=4'b0000 MTX_IDLE2=4'b0001 MTX_MOTSTART=4'b0010 MTX_TISTART1=4'b0011 MTX_TISTART2=4'b0100 MTX_NSCSTART1=4'b0101 MTX_NSCSTART2=4'b0110 MTX_SHIFT1=4'b0111 MTX_SHIFT2=4'b1000 MTX_END=4'b1001 STXS_IDLE=1'b0 STXS_SHIFT=1'b1 MOTMODE=1'b1 TIMODE=1'b0 NSCMODE=1'b0 MOTNOSSEL=1'b1 NSCNOSSEL=1'b0 cfg_framesizeM1=32'b00000000000000000000000000001111 Generated name = spi_chanctrl_Z3 @W:CG1340 : spi_chanctrl.v(416) | Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible. @W:CG133 : spi_chanctrl.v(195) | Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : spi_chanctrl.v(196) | Removing wire resetn_rx_p, as there is no assignment to it. @W:CG360 : spi_chanctrl.v(200) | Removing wire resetn_rx_r, as there is no assignment to it. @W:CG133 : spi_chanctrl.v(222) | Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on spi_chanctrl_Z3 ....... @W:CL169 : spi_chanctrl.v(1130) | Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(823) | Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(719) | Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers. @W:CL169 : spi_chanctrl.v(416) | Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers. @W:CL177 : spi_chanctrl.v(343) | Sharing sequential element cfg_enable_P1. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : spi.v(29) | Synthesizing module spi in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000000111 SPO=1'b0 SPH=1'b0 SPS=1'b1 CFG_MODE=32'b00000000000000000000000000000000 Generated name = spi_32s_16s_32s_7s_0_0_1_0s Running optimization stage 1 on spi_32s_16s_32s_7s_0_0_1_0s ....... @N:CG364 : corespi.v(27) | Synthesizing module CORESPI in library CORESPI_LIB. APB_DWIDTH=32'b00000000000000000000000000100000 CFG_FRAME_SIZE=32'b00000000000000000000000000010000 CFG_FIFO_DEPTH=32'b00000000000000000000000000100000 CFG_CLK=32'b00000000000000000000000000000111 CFG_MODE=32'b00000000000000000000000000000000 CFG_MOT_MODE=32'b00000000000000000000000000000000 CFG_MOT_SSEL=32'b00000000000000000000000000000001 CFG_TI_NSC_CUSTOM=32'b00000000000000000000000000000000 CFG_TI_NSC_FRC=32'b00000000000000000000000000000000 CFG_TI_JMB_FRAMES=32'b00000000000000000000000000000000 CFG_NSC_OPERATION=32'b00000000000000000000000000000000 SPS=1'b1 SPO=1'b0 SPH=1'b0 Generated name = CORESPI_Z4 Running optimization stage 1 on CORESPI_Z4 ....... @N:CG364 : CORESPI_0.v(32) | Synthesizing module CORESPI_0 in library work. Running optimization stage 1 on CORESPI_0 ....... @N:CG364 : decoder.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_DECODER in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_DECODER ....... @N:CG364 : tsm_sysreg.v(4) | Synthesizing module CORETSE_0_CORETSE_0_0_TSM_SYSREG in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEoO00=32'b00000000000000000000000000000001 CORETSEO=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_TSM_SYSREG_26s_1s_0s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_TSM_SYSREG_26s_1s_0s ....... @N:CG364 : mapbe_hst_cnv.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MAPBE_HST_CNV in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEO=32'b00000000000000000000000000000000 CORETSEoO00=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_MAPBE_HST_CNV_26s_0s_1s @W:CG360 : mapbe_hst_cnv.v(203) | Removing wire CORETSElioOI, as there is no assignment to it. @W:CG360 : mapbe_hst_cnv.v(206) | Removing wire CORETSEoioOI, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MAPBE_HST_CNV_26s_0s_1s ....... @W:CL169 : mapbe_hst_cnv.v(301) | Pruning unused register CORETSEli1lI. Make sure that there are no unused intermediate registers. @W:CG1283 : amcxfif.v(1047) | Type of parameter CORETSEO10i on the instance CORETSEI0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxtfif_fab.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB in library work. FAMILY=32'b00000000000000000000000000011010 TABITS=32'b00000000000000000000000000001011 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEol0OI=11'b00000000000 CORETSEOlIOI=12'b000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... @W:CG1283 : amcxfif.v(1233) | Type of parameter CORETSEO10i on the instance CORETSEl0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxtfif_sys.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS in library work. FAMILY=32'b00000000000000000000000000011010 TABITS=32'b00000000000000000000000000001011 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEO=32'b00000000000000000000000000000000 CORETSEOlIOI=12'b000000000000 CORETSEiO1OI=14'b00000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s @W:CG133 : amcxtfif_sys.v(546) | Object CORETSEiOoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(549) | Object CORETSEOIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(552) | Object CORETSEIIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(562) | Object CORETSElIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(572) | Object CORETSEoIoOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : amcxtfif_sys.v(588) | Object CORETSEiIoOI is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... @W:CL271 : amcxtfif_sys.v(2068) | Pruning unused bits 1 to 0 of genblk2.CORETSEl01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1583) | Pruning unused bits 13 to 2 of CORETSEo01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1553) | Pruning unused bits 1 to 0 of CORETSEI01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : amcxtfif_sys.v(1484) | Pruning unused bits 1 to 0 of CORETSEO01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL265 : amcxtfif_sys.v(2019) | Removing unused bit 38 of genblk2.CORETSEI11OI[39:0]. Either assign all bits or reduce the width of the signal. @W:CG1283 : amcxfif.v(1404) | Type of parameter CORETSEO10i on the instance CORETSEo0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxrfif_fab.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB in library work. FAMILY=32'b00000000000000000000000000011010 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOlIOI=13'b0000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s @N:CG179 : amcxrfif_fab.v(1479) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1485) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1491) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1497) | Removing redundant assignment. @N:CG179 : amcxrfif_fab.v(1503) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... @W:CL169 : amcxrfif_fab.v(636) | Pruning unused register CORETSEiiIOI. Make sure that there are no unused intermediate registers. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[36] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[37] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[38] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : amcxrfif_fab.v(2168) | Optimizing register bit CORETSEoloi[39] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : amcxrfif_fab.v(2168) | Pruning register bits 39 to 36 of CORETSEoloi[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL169 : amcxrfif_fab.v(1532) | Pruning unused register CORETSEl0IOI. Make sure that there are no unused intermediate registers. @W:CG1283 : amcxfif.v(1545) | Type of parameter CORETSEO10i on the instance CORETSEi0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxrfif_sys.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEO=32'b00000000000000000000000000000000 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOOlOI=14'b00000000000000 CORETSEIOlOI=13'b0000000000000 CORETSEOlIOI=15'b000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... @W:CL169 : amcxrfif_sys.v(2075) | Pruning unused register CORETSEoI0OI. Make sure that there are no unused intermediate registers. @W:CL169 : amcxrfif_sys.v(1783) | Pruning unused register CORETSElI0OI[14:0]. Make sure that there are no unused intermediate registers. @N:CG364 : amcxtfif_wtm.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM in library work. FAMILY=32'b00000000000000000000000000011010 RABITS=32'b00000000000000000000000000001100 CORETSEOII=32'b00000000000000000000000000000001 CORETSEol0OI=12'b000000000000 CORETSEOlIOI=13'b0000000000000 Generated name = CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0 Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... @W:CG1283 : amcxfif.v(1867) | Type of parameter CORETSEO10i on the instance CORETSEl1ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : amcxfif_hst.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXFIF_HST in library work. FAMILY=32'b00000000000000000000000000011010 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEOII=32'b00000000000000000000000000000001 CORETSEiiii=13'b0000000000000 CORETSEOOOOI=4'b0000 CORETSEIOOOI=19'b0000000000000000000 CORETSElOOOI=12'b111111111111 CORETSEoOOOI=12'b111111111111 CORETSEiOOOI=14'b00000000000000 CORETSEOIOOI=4'b0000 CORETSEIIOOI=3'b000 CORETSElIOOI=18'b000000000000000000 CORETSEoIOOI=13'b1111111111111 CORETSEiIOOI=13'b1111111111111 CORETSEOlOOI=12'b111111111111 Generated name = CORETSE_0_CORETSE_0_0_AMCXFIF_HST_Z5 @W:CG360 : amcxfif_hst.v(909) | Removing wire CORETSEo1OOI, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXFIF_HST_Z5 ....... @N:CG364 : amcxfif_clkrst.v(7) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXFIF_CLKRST in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXFIF_CLKRST ....... @N:CG364 : amcxfif.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_AMCXFIF in library work. FAMILY=32'b00000000000000000000000000011010 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 CORETSEi00i=32'b00000000000000000000000000100000 CORETSEO10i=32'b00000000000000000000000000000010 CORETSEO=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_AMCXFIF_26s_11s_12s_32s_2s_0s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_AMCXFIF_26s_11s_12s_32s_2s_0s ....... @N:CG364 : petmc_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PETMC_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PETMC_TOP_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PETMC_TOP_1s_26s ....... @N:CG364 : pecrc.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PECRC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PECRC_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PECRC_1s_26s ....... @N:CG364 : petfn_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PETFN_TOP in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEI=1'b0 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s @N:CG179 : petfn_top.v(10504) | Removing redundant assignment. @N:CG179 : petfn_top.v(10566) | Removing redundant assignment. @W:CG133 : petfn_top.v(423) | Object CORETSEl0oI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(426) | Removing wire CORETSEo0oI, as there is no assignment to it. @W:CG360 : petfn_top.v(450) | Removing wire CORETSEiOlI, as there is no assignment to it. @W:CG133 : petfn_top.v(510) | Object CORETSEiOiI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(513) | Object CORETSEOIiI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(532) | Object CORETSEOliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(534) | Object CORETSEIliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(537) | Object CORETSElliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petfn_top.v(539) | Object CORETSEoliI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petfn_top.v(977) | Removing wire CORETSEOOll, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s ....... @W:CL169 : petfn_top.v(4448) | Pruning unused register CORETSEioiI[15:0]. Make sure that there are no unused intermediate registers. @W:CL190 : petfn_top.v(4128) | Optimizing register bit CORETSEooOl[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : petfn_top.v(4128) | Optimizing register bit CORETSEooOl[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL279 : petfn_top.v(4128) | Pruning register bits 6 to 5 of CORETSEooOl[6:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @N:CG364 : perfn_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PERFN_TOP in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEO=32'b00000000000000000000000000000000 CORETSEI=1'b0 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s @W:CG360 : perfn_top.v(348) | Removing wire CORETSEI0I, as there is no assignment to it. @W:CG360 : perfn_top.v(655) | Removing wire CORETSEOI1, as there is no assignment to it. @W:CG133 : perfn_top.v(658) | Object CORETSEII1 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s ....... @N:CG364 : permc_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PERMC_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PERMC_TOP_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PERMC_TOP_1s_26s ....... @N:CG364 : pe_mcxmac_core.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PE_MCXMAC_CORE in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=1'b0 CORETSEO=32'b00000000000000000000000000000000 CORETSEIi0I=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_PE_MCXMAC_CORE_26s_0_0s_0s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PE_MCXMAC_CORE_26s_0_0s_0s ....... @N:CG364 : pemgt.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMGT in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMGT_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMGT_1s_26s ....... @N:CG364 : pehst.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEHST in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEHST_1s_26s @W:CG133 : pehst.v(613) | Object CORETSEOlI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(709) | Object CORETSEIlI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(714) | Object CORETSEllI1 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pehst.v(716) | Object CORETSEolI1 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEHST_1s_26s ....... @W:CL169 : pehst.v(2022) | Pruning unused register CORETSEllo1. Make sure that there are no unused intermediate registers. @W:CL169 : pehst.v(1990) | Pruning unused register CORETSEIlo1. Make sure that there are no unused intermediate registers. @W:CL169 : pehst.v(1958) | Pruning unused register CORETSEOlo1. Make sure that there are no unused intermediate registers. @N:CG364 : pecar.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PECAR in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PECAR ....... @N:CG364 : pe_mcxmac.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PE_MCXMAC in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=1'b0 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEO=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_PE_MCXMAC_26s_0_0s_0s @W:CG360 : pe_mcxmac.v(681) | Removing wire CORETSEllO1, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(684) | Removing wire CORETSEOio0, as there is no assignment to it. @W:CG360 : pe_mcxmac.v(687) | Removing wire CORETSEiIo0, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PE_MCXMAC_26s_0_0s_0s ....... @N:CG364 : tsmac_top.v(4) | Synthesizing module CORETSE_0_CORETSE_0_0_TSMAC_TOP in library work. FAMILY=32'b00000000000000000000000000011010 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 MDIO_PHYID=32'b00000000000000000000000000010010 MCXMAC_SAL_ON=32'b00000000000000000000000000000001 MCXMAC_WOL_ON=32'b00000000000000000000000000000001 MCXMAC_STATS_ON=32'b00000000000000000000000000000001 CORETSEO=32'b00000000000000000000000000000000 CORETSEIi0I=32'b00000000000000000000000000000000 CORETSEI=32'b00000000000000000000000000000000 CORETSEo1llI=32'b00000000000000000000000000000001 CORETSEi1llI=32'b00000000000000000000000000000010 CORETSEOollI=32'b00000000000000000000000000000001 CORETSEIollI=32'b00000000000000000000000000000010 CORETSElollI=32'b00000000000000000000000000010010 CORETSEoollI=32'b00000000000000000000000000010010 CORETSEiollI=32'b00000000000000000000000000000101 CORETSEOillI=32'b00000000000000000000000000000101 CORETSEoO00=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6 @N:CG364 : sib_sync_pulse.v(5) | Synthesizing module CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEO0O0=32'b00000000000000000000000000000000 CORETSEiOl0=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE_26s_0s_0s @N:CG364 : sib_sync_2flp.v(5) | Synthesizing module CORETSE_0_CORETSE_0_0_SIB_SYNC_2FLP in library work. CORETSEO0I0=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000010011 CORETSEI0I0=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_SIB_SYNC_2FLP_1s_19s_0s @W:CG133 : sib_sync_2flp.v(77) | Object CORETSEolO0 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_SIB_SYNC_2FLP_1s_19s_0s ....... Running optimization stage 1 on CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE_26s_0s_0s ....... @N:CG364 : pemstat_cntrl.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_CNTRL in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_CNTRL_1s_26s @W:CG360 : pemstat_cntrl.v(113) | Removing wire CORETSElllo, as there is no assignment to it. @W:CG360 : pemstat_cntrl.v(115) | Removing wire CORETSEollo, as there is no assignment to it. @W:CG133 : pemstat_cntrl.v(118) | Object CORETSEillo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(120) | Object CORETSEO0lo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(129) | Object CORETSEi0lo is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : pemstat_cntrl.v(131) | Object CORETSEO1lo is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_CNTRL_1s_26s ....... @N:CG364 : pemstat_linc.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_LINC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_LINC_1s_26s @N:CG179 : pemstat_linc.v(226) | Removing redundant assignment. @N:CG179 : pemstat_linc.v(300) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_LINC_1s_26s ....... @N:CG364 : pemstat_ladd.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_LADD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_LADD_1s_26s @N:CG179 : pemstat_ladd.v(383) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_LADD_1s_26s ....... @N:CG364 : pemstat_sinc.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_SINC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_SINC_1s_26s @N:CG179 : pemstat_sinc.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sinc.v(300) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINC_1s_26s ....... @N:CG364 : pemstat_sinchd.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_SINCHD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_SINCHD_1s_26s @N:CG179 : pemstat_sinchd.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sinchd.v(300) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINCHD_1s_26s ....... @N:CG364 : pemstat_sadd.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_SADD in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_SADD_1s_26s @N:CG179 : pemstat_sadd.v(244) | Removing redundant assignment. @N:CG179 : pemstat_sadd.v(323) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_SADD_1s_26s ....... @N:CG364 : pemstat_sincnf.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_SINCNF in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_SINCNF_1s_26s @N:CG179 : pemstat_sincnf.v(226) | Removing redundant assignment. @N:CG179 : pemstat_sincnf.v(300) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINCNF_1s_26s ....... @N:CG364 : pemstat_store.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_STORE in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_STORE_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_STORE_26s ....... @N:CG364 : pemstat_eim.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT_EIM in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_EIM_26s_1s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_EIM_26s_1s ....... @N:CG364 : pemstat.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEMSTAT in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEMSTAT_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEMSTAT_26s ....... @N:CG364 : mmcxwol.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MMCXWOL in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MMCXWOL_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MMCXWOL_1s_26s ....... @N:CG364 : si_sal.v(4) | Synthesizing module CORETSE_0_CORETSE_0_0_SI_SAL in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_SI_SAL_26s @N:CG179 : si_sal.v(931) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_SI_SAL_26s ....... @W:CG360 : tsmac_top.v(154) | Removing wire CORETSEII1lI, as there is no assignment to it. @W:CG360 : tsmac_top.v(156) | Removing wire CORETSElI1lI, as there is no assignment to it. @W:CG360 : tsmac_top.v(158) | Removing wire CORETSEoI1lI, as there is no assignment to it. @W:CG360 : tsmac_top.v(160) | Removing wire CORETSEiI1lI, as there is no assignment to it. @W:CG360 : tsmac_top.v(162) | Removing wire CORETSEOl1lI, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6 ....... @W:CL318 : tsmac_top.v(154) | *Output CORETSEII1lI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(156) | *Output CORETSElI1lI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(158) | *Output CORETSEoI1lI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(160) | *Output CORETSEiI1lI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : tsmac_top.v(162) | *Output CORETSEOl1lI has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : tx2048x40.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_TX2048X40 in library work. TABITS=32'b00000000000000000000000000001011 CORETSEOII=32'b00000000000000000000000000000001 CORETSEoOil=32'b00000000000000000000000000000001 CORETSEiOil=32'b00000000000000000000000000000100 Generated name = CORETSE_0_CORETSE_0_0_TX2048X40_11s_1s_1s_4s @W:CG133 : tx2048x40.v(93) | Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_TX2048X40_11s_1s_1s_4s ....... @N:CL134 : tx2048x40.v(139) | Found RAM CORETSEIIil, depth=2048, width=40 @N:CG364 : rx4096x36.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_RX4096X36 in library work. RABITS=32'b00000000000000000000000000001100 CORETSEOII=32'b00000000000000000000000000000001 CORETSEoOil=32'b00000000000000000000000000000001 CORETSEiOil=32'b00000000000000000000000000000100 Generated name = CORETSE_0_CORETSE_0_0_RX4096X36_12s_1s_1s_4s @W:CG133 : rx4096x36.v(93) | Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_RX4096X36_12s_1s_1s_4s ....... @N:CL134 : rx4096x36.v(139) | Found RAM CORETSEIIil, depth=4096, width=36 @N:CG364 : CoreTSE_top.v(2) | Synthesizing module CORETSE_0_CORETSE_0_0_CORETSE_TOP in library work. GMII_TBI=32'b00000000000000000000000000000001 TABITS=32'b00000000000000000000000000001011 RABITS=32'b00000000000000000000000000001100 SAL=32'b00000000000000000000000000000001 WoL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 MDIO_PHYID=32'b00000000000000000000000000010010 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s @N:CG364 : msgmii_clkrst.v(7) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CLKRST in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CLKRST ....... @N:CG364 : msgmii_cnvtxi.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CNVTXI in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_CNVTXI_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CNVTXI_26s ....... @W:CL169 : msgmii_cnvtxi.v(364) | Pruning unused register CORETSEO0oII[3:0]. Make sure that there are no unused intermediate registers. @N:CG364 : msgmii_cnvtxo.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO_26s ....... @N:CG364 : t8b10b.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_T8B10B in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_T8B10B ....... @N:CG364 : petex_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PETEX_TOP in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PETEX_TOP_26s_0s_1s @N:CG179 : petex_top.v(2139) | Removing redundant assignment. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PETEX_TOP_26s_0s_1s ....... @W:CL169 : petex_top.v(690) | Pruning unused register CORETSEO1II. Make sure that there are no unused intermediate registers. @N:CG364 : perex_pma.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEREX_PMA in library work. FAMILY=32'b00000000000000000000000000011010 SLIP_ENABLE=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 CORETSEiili=3'b000 CORETSEOO0i=3'b001 CORETSEIO0i=3'b010 CORETSElO0i=3'b011 CORETSEoO0i=3'b100 Generated name = CORETSE_0_CORETSE_0_0_PEREX_PMA_26s_0s_1s_0_1_2_3_4 @W:CG133 : perex_pma.v(219) | Object CORETSEiOo0 is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(188) | Object CORETSEiO0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(196) | Object CORETSEOI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(199) | Object CORETSEII0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(202) | Object CORETSElI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(205) | Object CORETSEoI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : perex_pma.v(213) | Object CORETSEiI0i is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : perex_pma.v(216) | Removing wire CORETSEOl0i, as there is no assignment to it. @W:CG133 : perex_pma.v(222) | Object CORETSEIl0i is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... @W:CL169 : perex_pma.v(2085) | Pruning unused register CORETSEll0i. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1890) | Pruning unused register CORETSEIili. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1854) | Pruning unused register CORETSEOili. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pma.v(1818) | Pruning unused register CORETSEioli. Make sure that there are no unused intermediate registers. @N:CG364 : r10b8b.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_R10B8B in library work. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_R10B8B ....... @N:CG364 : perex_pcs.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEREX_PCS in library work. CORETSEI=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s ....... @W:CL169 : perex_pcs.v(4321) | Pruning unused register CORETSElIli. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pcs.v(4260) | Pruning unused register CORETSEOIli. Make sure that there are no unused intermediate registers. @W:CL169 : perex_pcs.v(4101) | Pruning unused register CORETSEI1lI. Make sure that there are no unused intermediate registers. @W:CL265 : perex_pcs.v(1303) | Removing unused bit 3 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : perex_pcs.v(1303) | Removing unused bit 1 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : peanx_sync.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PEANX_SYNC in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_PEANX_SYNC_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PEANX_SYNC_1s_26s ....... @N:CG364 : msgmii_peanx_top.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP in library work. CORETSEOII=32'b00000000000000000000000000000001 FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s ....... @W:CL169 : msgmii_peanx_top.v(3121) | Pruning unused register CORETSEiIIlI. Make sure that there are no unused intermediate registers. @W:CL265 : msgmii_peanx_top.v(3041) | Removing unused bit 14 of CORETSElIIlI[15:0]. Either assign all bits or reduce the width of the signal. @W:CL265 : msgmii_peanx_top.v(2437) | Removing unused bit 14 of CORETSEl1OlI[15:0]. Either assign all bits or reduce the width of the signal. @W:CL177 : msgmii_peanx_top.v(2361) | Sharing sequential element CORETSEI0OlI. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : petbm.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_PETBM in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_PETBM_26s_0s_1s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PETBM_26s_0s_1s ....... @W:CL169 : petbm.v(2544) | Pruning unused register CORETSEIIio. Make sure that there are no unused intermediate registers. @N:CG364 : petcr.v(7) | Synthesizing module CORETSE_0_CORETSE_0_0_PETCR in library work. @W:CG133 : petcr.v(145) | Object CORETSEIiOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : petcr.v(147) | Object CORETSEliOI is declared but not assigned. Either assign a value or remove the declaration. @W:CG360 : petcr.v(150) | Removing wire CORETSEoiOI, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_PETCR ....... @W:CL177 : petcr.v(319) | Sharing sequential element CORETSEooOI. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(422) | Sharing sequential element CORETSEoOII. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : msgmii_tbi.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_TBI in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=32'b00000000000000000000000000000000 SLIP_ENABLE=32'b00000000000000000000000000000000 CORETSEOII=32'b00000000000000000000000000000001 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_TBI_26s_0s_0s_1s @W:CG360 : msgmii_tbi.v(411) | Removing wire CORETSEIio0, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_TBI_26s_0s_0s_1s ....... @N:CG364 : msgmii_cnvrxi.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CNVRXI in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_CNVRXI_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CNVRXI_26s ....... @W:CL169 : msgmii_cnvrxi.v(496) | Pruning unused register CORETSEIl1II[1:0]. Make sure that there are no unused intermediate registers. @N:CG364 : msgmii_cnvrxo.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CNVRXO in library work. FAMILY=32'b00000000000000000000000000011010 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_CNVRXO_26s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CNVRXO_26s ....... @N:CG364 : msgmii_core.v(6) | Synthesizing module CORETSE_0_CORETSE_0_0_MSGMII_CORE in library work. FAMILY=32'b00000000000000000000000000011010 CORETSEI=32'b00000000000000000000000000000000 MDIO_PHYID=32'b00000000000000000000000000010010 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s Running optimization stage 1 on CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s ....... @W:CG781 : CoreTSE_top.v(825) | Input CORETSEIO1lI on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(829) | Input CORETSElO1lI on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(833) | Input CORETSEoO1lI on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(837) | Input CORETSEiO1lI on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(841) | Input CORETSEOI1lI on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : CoreTSE_top.v(865) | Input CORETSEOl00 on instance CORETSEIillI is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG360 : CoreTSE_top.v(90) | Removing wire TXD, as there is no assignment to it. @W:CG360 : CoreTSE_top.v(92) | Removing wire TXEN, as there is no assignment to it. @W:CG360 : CoreTSE_top.v(94) | Removing wire TXER, as there is no assignment to it. @W:CG360 : CoreTSE_top.v(364) | Removing wire CORETSEl0llI, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s ....... @W:CL318 : CoreTSE_top.v(90) | *Output TXD has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : CoreTSE_top.v(92) | *Output TXEN has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : CoreTSE_top.v(94) | *Output TXER has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : CoreTSE.v(2) | Synthesizing module CORETSE_0_CORETSE_0_0_CORETSE in library work. FAMILY=32'b00000000000000000000000000011010 GMII_TBI=32'b00000000000000000000000000000001 SAL=32'b00000000000000000000000000000001 WoL=32'b00000000000000000000000000000001 STATS=32'b00000000000000000000000000000001 MDIO_PHYID=32'b00000000000000000000000000010010 PACKET_SIZE=32'b00000000000000000000000000001011 SLIP_ENABLE=32'b00000000000000000000000000000000 Generated name = CORETSE_0_CORETSE_0_0_CORETSE_26s_1s_1s_1s_1s_18s_11s_0s @W:CG360 : CoreTSE.v(247) | Removing wire CORETSElo1, as there is no assignment to it. @W:CG360 : CoreTSE.v(250) | Removing wire CORETSEoo1, as there is no assignment to it. Running optimization stage 1 on CORETSE_0_CORETSE_0_0_CORETSE_26s_1s_1s_1s_1s_18s_11s_0s ....... @N:CG364 : CORETSE_0.v(28) | Synthesizing module CORETSE_0 in library work. Running optimization stage 1 on CORETSE_0 ....... @N:CG364 : Clock_gen.v(30) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... @N:CG364 : Tx_async.v(14) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000000 CUARTI1ll=32'b00000000000000000000000000000000 CUARTl1ll=32'b00000000000000000000000000000001 CUARTOO0l=32'b00000000000000000000000000000010 CUARTIO0l=32'b00000000000000000000000000000011 CUARTlO0l=32'b00000000000000000000000000000100 CUARTOI0l=32'b00000000000000000000000000000101 CUARTII0l=32'b00000000000000000000000000000110 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s @W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible. @W:CG1340 : Tx_async.v(605) | Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible. @N:CG179 : Tx_async.v(870) | Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @W:CL190 : Tx_async.v(301) | Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : Tx_async.v(301) | Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers. @N:CG364 : Rx_async.v(14) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 CUARTOIIl=32'b00000000000000000000000000000000 CUARTIIIl=32'b00000000000000000000000000000001 CUARTlIIl=32'b00000000000000000000000000000010 CUARTOlIl=32'b00000000000000000000000000000011 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s @N:CG179 : Rx_async.v(750) | Removing redundant assignment. @N:CG179 : Rx_async.v(857) | Removing redundant assignment. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @W:CL177 : Rx_async.v(1613) | Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : CoreUART.v(14) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s @N:CG179 : CoreUART.v(1338) | Removing redundant assignment. @W:CG133 : CoreUART.v(333) | Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... @W:CL169 : CoreUART.v(1268) | Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(1159) | Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(1106) | Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(984) | Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(936) | Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(936) | Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(888) | Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(888) | Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(405) | Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers. @N:CG364 : CoreUARTapb.v(14) | Synthesizing module CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb in library work. FAMILY=32'b00000000000000000000000000011010 TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 BAUD_VALUE=32'b00000000000000000000000000000001 FIXEDMODE=32'b00000000000000000000000000000000 PRG_BIT8=32'b00000000000000000000000000000000 PRG_PARITY=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN=32'b00000000000000000000000000000000 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000000 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z7 @N:CG179 : CoreUARTapb.v(785) | Removing redundant assignment. @N:CG179 : CoreUARTapb.v(868) | Removing redundant assignment. @W:CG133 : CoreUARTapb.v(283) | Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z7 ....... @N:CG364 : CoreUARTapb_0.v(31) | Synthesizing module CoreUARTapb_0 in library work. Running optimization stage 1 on CoreUARTapb_0 ....... @N:CG364 : acg5.v(357) | Synthesizing module INBUF_DIFF in library work. Running optimization stage 1 on INBUF_DIFF ....... @W:CG1283 : miv_rv32.v(432) | Type of parameter RAM_SB_IN_WIDTH on the instance u_opsrv_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : miv_rv32.v(432) | Type of parameter RAM_SB_OUT_WIDTH on the instance u_opsrv_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : miv_rv32_core_merged.v(15936) | Synthesizing module miv_rv32_ifu_iab in library work. I_ADDR_WIDTH=32'b00000000000000000000000000100000 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_BUFF_DEPTH=32'b00000000000000000000000000000010 Generated name = miv_rv32_ifu_iab_32s_2s_3s_2s Running optimization stage 1 on miv_rv32_ifu_iab_32s_2s_3s_2s ....... @N:CG364 : miv_rv32_core_merged.v(10933) | Synthesizing module miv_rv32_fetch_unit in library work. I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_reset_vector=32'b10000000000000000000000000000000 IAB_BUFF_DEPTH=32'b00000000000000000000000000000011 LOG2_IAB_BUFF_DEPTH=32'b00000000000000000000000000000010 MAX_IFU_EMI_OS=32'b00000000000000000000000000000011 LOG2_MAX_IFU_EMI_OS=32'b00000000000000000000000000000010 RESP_ERROR_WIDTH=32'b00000000000000000000000000000010 IFU_MEM_ERROR_BIT=32'b00000000000000000000000000000000 IFU_PARITY_ERROR_BIT=32'b00000000000000000000000000000001 Generated name = miv_rv32_fetch_unit_32s_2147483648_3s_2s_3s_2s_2s_0s_1s Running optimization stage 1 on miv_rv32_fetch_unit_32s_2147483648_3s_2s_3s_2s_2s_0s_1s ....... @N:CG364 : miv_rv32_core_merged.v(16373) | Synthesizing module miv_rv32_lsu in library work. D_ADDR_WIDTH=32'b00000000000000000000000000100000 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 OS_COUNT_WIDTH=32'b00000000000000000000000000000010 MAX_OS=32'b00000000000000000000000000000010 Generated name = miv_rv32_lsu_32s_2s_1s_2s_2s @W:CG133 : miv_rv32_core_merged.v(16466) | Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16474) | Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16477) | Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16478) | Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16479) | Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16480) | Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16481) | Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16482) | Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16483) | Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(16484) | Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... @N:CG364 : miv_rv32_core_merged.v(11814) | Synthesizing module miv_rv32_idecode in library work. GEN_DECODE_RV32I=1'b1 GEN_DECODE_RV32M=32'b00000000000000000000000000000000 GEN_DECODE_RV32C=32'b00000000000000000000000000000000 Generated name = miv_rv32_idecode_1_0s_0s Running optimization stage 1 on miv_rv32_idecode_1_0s_0s ....... Only the first 100 messages of id 'CG364' are reported. To see all messages use 'report_messages -log F:\DG0799_final\Libero_Project\Libero_Project\synthesis\synlog\top_compiler.srr -id CG364' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG364} -count unlimited' in the Tcl shell. CHECK_ILLEGAL=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_decode_1s_0s Running optimization stage 1 on miv_rv32_csr_decode_1s_0s ....... USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 l_core_cfg_hw_debug=1'b1 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 cfg_div_en=32'b00000000000000000000000000000000 cfg_fast_mul=32'b00000000000000000000000000000000 cfg_slow_mul=32'b00000000000000000000000000000000 Generated name = miv_rv32_exu_1s_1s_1_0s_0s_0_0_0 Running optimization stage 1 on miv_rv32_exu_1s_1s_1_0s_0s_0_0_0 ....... @W:CL169 : miv_rv32_core_merged.v(10641) | Pruning unused register div_divisor[62:0]. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10641) | Pruning unused register dividend[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10641) | Pruning unused register res_pos_neg. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10641) | Pruning unused register quotient[31:0]. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10633) | Pruning unused register div_ack. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10623) | Pruning unused register slow_mul_ack. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(10615) | Pruning unused register mul_div_cnt[31:0]. Make sure that there are no unused intermediate registers. @W:CL271 : miv_rv32_core_merged.v(10661) | Pruning unused bits 64 to 32 of exu_result_reg_int[64:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 1 on miv_rv32_bcu ....... IRQ_STICKY_CAPTURE=32'b00000000000000000000000000000000 Generated name = miv_rv32_irq_reg_0s Running optimization stage 1 on miv_rv32_irq_reg_0s ....... l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 Generated name = miv_rv32_priv_irq_8_0_0 Running optimization stage 1 on miv_rv32_priv_irq_8_0_0 ....... CHECK_ILLEGAL=32'b00000000000000000000000000000000 l_core_cfg_hw_debug=1'b1 Generated name = miv_rv32_csr_decode_0s_1 Running optimization stage 1 on miv_rv32_csr_decode_0s_1 ....... WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_1s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... WIDTH=32'b00000000000000000000000000000001 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_1s_0s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... WIDTH=32'b00000000000000000000000000011111 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_31s_0s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... WIDTH=32'b00000000000000000000000000000101 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=5'b00000 Generated name = miv_rv32_csr_gpr_state_reg_5s_1s_0 @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000000 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_0s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... I_ADDR_WIDTH=32'b00000000000000000000000000100000 l_core_cfg_hw_debug=1'b1 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 Generated name = miv_rv32_csr_privarch_Z8 WIDTH=32'b00000000000000000000000000011110 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_30s_1s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_30s_1s_0s ....... WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_0 @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... @W:CG133 : miv_rv32_core_merged.v(3976) | Object machine_init_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3977) | Object machine_init_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3978) | Object machine_sw_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3979) | Object machine_sw_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3989) | Object machine_init_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3990) | Object machine_init_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3991) | Object machine_sw_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3992) | Object machine_sw_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3996) | Object tdata1_mcontrol_action_reg is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3997) | Object machine_init_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3998) | Object machine_init_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3999) | Object machine_sw_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4000) | Object machine_sw_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4004) | Object machine_init_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4005) | Object machine_init_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4006) | Object machine_sw_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4007) | Object machine_sw_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3976) | Object machine_init_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3977) | Object machine_init_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3978) | Object machine_sw_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3979) | Object machine_sw_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3989) | Object machine_init_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3990) | Object machine_init_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3991) | Object machine_sw_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3992) | Object machine_sw_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3996) | Object tdata1_mcontrol_action_reg is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3997) | Object machine_init_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3998) | Object machine_init_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(3999) | Object machine_sw_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4000) | Object machine_sw_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4004) | Object machine_init_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4005) | Object machine_init_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4006) | Object machine_sw_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(4007) | Object machine_sw_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration. WIDTH=32'b00000000000000000000000000000011 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b00000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_3s_1s_0s @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... WIDTH=32'b00000000000000000000000000100000 FIELD_RESET_EN=32'b00000000000000000000000000000001 FIELD_RESET_VAL=32'b10000000000000000000000000000000 Generated name = miv_rv32_csr_gpr_state_reg_32s_1s_2147483648 @W:CG133 : miv_rv32_core_merged.v(5448) | Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on miv_rv32_csr_gpr_state_reg_32s_1s_2147483648 ....... @W:CG133 : miv_rv32_core_merged.v(1815) | Object irq_m_swi is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(1992) | Object mcause_sw_rd_sel is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(1993) | Object mcause_sw_wr_sel is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(2096) | Object sw_rd_en_valid is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(2101) | Object ext_msip_retime is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(2102) | Object ext_mtip_retime is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(2103) | Object ext_meip_retime is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : miv_rv32_core_merged.v(2121) | Object debugger_rd_en_valid is declared but not assigned. Either assign a value or remove the declaration. Only the first 100 messages of id 'CG133' are reported. To see all messages use 'report_messages -log F:\DG0799_final\Libero_Project\Libero_Project\synthesis\synlog\top_compiler.srr -id CG133' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CG133} -count unlimited' in the Tcl shell. Running optimization stage 1 on miv_rv32_csr_privarch_Z8 ....... @W:CL168 : miv_rv32_core_merged.v(4093) | Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=1'b1 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 l_core_cfg_trigger_bus_width=32'b00000000000000000000000000000010 l_core_cfg_gpr_ecc_uncorrectable_irq=1'b0 l_core_cfg_gpr_ecc_correctable_irq=1'b0 l_core_cfg_gpr_fwd_hzd=1'b0 Generated name = miv_rv32_expipe_Z9 ECC_ENABLE=32'b00000000000000000000000000000000 l_core_cfg_gpr_fwd_hzd=1'b0 Generated name = miv_rv32_gpr_ram_0s_0 @N:CG179 : miv_rv32_core_merged.v(5850) | Removing redundant assignment. @N:CG179 : miv_rv32_core_merged.v(5851) | Removing redundant assignment. d_width=32'b00000000000000000000000000100000 addr_width_gpr=32'b00000000000000000000000000000101 mem_depth=32'b00000000000000000000000000100000 Generated name = miv_rv32_gpr_ram_array_32s_5s_32s Running optimization stage 1 on miv_rv32_gpr_ram_array_32s_5s_32s ....... @N:CL214 : miv_rv32_core_merged.v(6037) | Found multi-write port RAM mem, number of write ports=2, depth=32, width=32 @N:CL214 : miv_rv32_core_merged.v(6036) | Found multi-write port RAM mem, number of write ports=2, depth=32, width=32 Running optimization stage 1 on miv_rv32_gpr_ram_0s_0 ....... @W:CL169 : miv_rv32_core_merged.v(5838) | Pruning unused register gpr_wr_sel_reg[4:0]. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_core_merged.v(5838) | Pruning unused register gpr_wr_valid_reg. Make sure that there are no unused intermediate registers. Running optimization stage 1 on miv_rv32_expipe_Z9 ....... I_ADDR_WIDTH=32'b00000000000000000000000000100000 D_ADDR_WIDTH=32'b00000000000000000000000000100000 I_DATA_BYTES=32'b00000000000000000000000000000100 D_DATA_BYTES=32'b00000000000000000000000000000100 l_core_cfg_hw_debug=1'b1 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 Generated name = miv_rv32_core_Z10 Running optimization stage 1 on miv_rv32_core_Z10 ....... BUFF_WIDTH=32'b00000000000000000000000000000110 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_6s_2s_1s_1s Running optimization stage 1 on miv_rv32_buffer_6s_2s_1s_1s ....... BUFF_WIDTH=32'b00000000000000000000000000001011 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_11s_2s_1s_1s Running optimization stage 1 on miv_rv32_buffer_11s_2s_1s_1s ....... BUFF_WIDTH=32'b00000000000000000000000000000100 BUFF_SIZE=32'b00000000000000000000000000000010 PTR_SIZE=32'b00000000000000000000000000000001 BUFF_MAX=32'b00000000000000000000000000000001 Generated name = miv_rv32_buffer_4s_2s_1s_1s Running optimization stage 1 on miv_rv32_buffer_4s_2s_1s_1s ....... REGS_ADDR_WIDTH=32'b00000000000000000000000000001100 ECC_ENABLE=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm0_present=32'b00000000000000000000000000000001 l_opsrv_cfg_axi_mstr_present=32'b00000000000000000000000000000000 REQ_BUFF_WIDTH=32'b00000000000000000000000000000100 REQ_BUFF_DEPTH=32'b00000000000000000000000000000010 LOG2_REQ_BUFF_DEPTH=32'b00000000000000000000000000000001 Generated name = miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s Running optimization stage 1 on miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s ....... @W:CL168 : miv_rv32_opsrv_merged.v(13773) | Removing instance u_opsrv_core_gpr_ded_reset_reg because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 ECC_ENABLE=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm0_present=32'b00000000000000000000000000000001 l_opsrv_cfg_tcm1_present=32'b00000000000000000000000000000000 l_opsrv_cfg_axi_mstr_present=32'b00000000000000000000000000000000 l_opsrv_cfg_ahb_mstr_present=32'b00000000000000000000000000000000 MAX_OS_I_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_I_TRX=32'b00000000000000000000000000000001 MAX_OS_D_TRX=32'b00000000000000000000000000000010 LOG2_MAX_OS_D_TRX=32'b00000000000000000000000000000001 Generated name = miv_rv32_opsrv_interconnect_Z11 Running optimization stage 1 on miv_rv32_opsrv_interconnect_Z11 ....... FAMILY=32'b00000000000000000000000000011010 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_MSTR_REGISTER_IO=32'b00000000000000000000000000000001 AHB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 OPSRV_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_DAP_ADDR_WIDTH=32'b00000000000000000000000000100000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_axi_mstr_start_addr=32'b00001111111111111111111111100110 l_axi_mstr_end_addr=32'b00001111111111111111111111100111 l_apb_mstr_start_addr=32'b01100000000000000000000000000000 l_apb_mstr_end_addr=32'b01101111111111111111111111111111 l_ahb_mstr_start_addr=32'b00001111111111111111111111101000 l_ahb_mstr_end_addr=32'b00001111111111111111111111101001 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_opsrv_cfg_start_addr=32'b00000000000000000110000000000000 l_opsrv_cfg_end_addr=32'b00000000000000000110111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001111111111111111 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_dap_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_dap_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_tcm_dap_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_dap_tcm0_end_addr=32'b00001111111111111111111111100101 l_tcm_dap_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_dap_tcm1_end_addr=32'b00001111111111111111111111101101 l_opsrv_cfg_tcm_dap_present=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm0_dap_present=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm0_present=32'b00000000000000000000000000000001 l_opsrv_cfg_tcm1_present=32'b00000000000000000000000000000000 l_opsrv_cfg_axi_mstr_present=32'b00000000000000000000000000000000 l_opsrv_cfg_ahb_mstr_present=32'b00000000000000000000000000000000 l_opsrv_cfg_apb_mstr_present=32'b00000000000000000000000000000001 l_opsrv_cfg_core_debug=1'b1 l_core_cfg_hw_debug=1'b1 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 ECC_ENABLE=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000000 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000000 MTIME_PRESCALER=32'b00000000000000000000000001100100 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 TCM0_DEPTH=32'b00000000000000000100000000000000 TCM1_DEPTH=32'b00000000000000000000000010000001 Generated name = miv_rv32_opsrv_Z12 l_opsrv_cfg_core_debug=1'b1 Generated name = miv_rv32_opsrv_dtm_jtag_1 @N:CG179 : miv_rv32_opsrv_merged.v(12880) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(12888) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(12908) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(12909) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(12910) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(12911) | Removing redundant assignment. @N:CG179 : miv_rv32_opsrv_merged.v(13087) | Removing redundant assignment. Running optimization stage 1 on miv_rv32_opsrv_dtm_jtag_1 ....... DEPTH_LG_2=32'b00000000000000000000000000000001 WIDTH=32'b00000000000000000000000000101001 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 ECC_ENABLE=32'b00000000000000000000000000000000 DEPTH=32'b00000000000000000000000000000010 Generated name = miv_rv32_opsrv_debug_fifo_1s_41s_1s_0s_2s Running optimization stage 1 on miv_rv32_opsrv_debug_fifo_1s_41s_1s_0s_2s ....... @N:CL134 : miv_rv32_opsrv_merged.v(12426) | Found RAM fifoMem, depth=2, width=41 DEPTH_LG_2=32'b00000000000000000000000000000001 WIDTH=32'b00000000000000000000000000100010 RESET_SYNC_WR_2_RD=32'b00000000000000000000000000000001 ECC_ENABLE=32'b00000000000000000000000000000000 DEPTH=32'b00000000000000000000000000000010 Generated name = miv_rv32_opsrv_debug_fifo_1s_34s_1s_0s_2s Running optimization stage 1 on miv_rv32_opsrv_debug_fifo_1s_34s_1s_0s_2s ....... @N:CL134 : miv_rv32_opsrv_merged.v(12426) | Found RAM fifoMem, depth=2, width=34 Running optimization stage 1 on miv_rv32_opsrv_debug_sba ....... Running optimization stage 1 on miv_rv32_opsrv_debug_du ....... @W:CL265 : miv_rv32_opsrv_merged.v(10991) | Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : miv_rv32_opsrv_merged.v(10991) | Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL190 : miv_rv32_opsrv_merged.v(10991) | Optimizing register bit abstractcs_busyerr to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : miv_rv32_opsrv_merged.v(10991) | Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers. l_opsrv_cfg_core_debug=1'b1 Generated name = miv_rv32_opsrv_debug_1 Running optimization stage 1 on miv_rv32_opsrv_debug_1 ....... NUM_REQS=32'b00000000000000000000000000000010 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_2s_1s_1s NUM_REQS=32'b00000000000000000000000000000010 Generated name = miv_rv32_fixed_arb_2s Running optimization stage 1 on miv_rv32_fixed_arb_2s ....... Running optimization stage 1 on miv_rv32_rr_pri_arb_2s_1s_1s ....... APB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_MSTR_REGISTER_IO=32'b00000000000000000000000000000001 l_opsrv_cfg_apb_byte_shim=1'b1 IDLE_ST=3'b000 SETUP_ST=3'b001 ACCESS_ST=3'b010 BH_READ_0_ST=3'b011 BH_READ_1_ST=3'b100 BH_WRITE_ST=3'b101 Generated name = miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5 @N:CG179 : miv_rv32_opsrv_merged.v(6149) | Removing redundant assignment. Running optimization stage 1 on miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5 ....... NUM_REQS=32'b00000000000000000000000000000011 USE_FORMAL=32'b00000000000000000000000000000001 USE_SIM=32'b00000000000000000000000000000001 Generated name = miv_rv32_rr_pri_arb_3s_1s_1s NUM_REQS=32'b00000000000000000000000000000011 Generated name = miv_rv32_fixed_arb_3s Running optimization stage 1 on miv_rv32_fixed_arb_3s ....... Running optimization stage 1 on miv_rv32_rr_pri_arb_3s_1s_1s ....... FAMILY=32'b00000000000000000000000000011010 TCM_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 TCM_DAP_PRESENT=32'b00000000000000000000000000000000 DEBUG_PRESENT=1'b1 CPU_I_PRESENT=32'b00000000000000000000000000000001 CPU_D_PRESENT=32'b00000000000000000000000000000001 USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 RAM_SB_IN_WIDTH=32'b00000000000000000000000000000100 RAM_SB_OUT_WIDTH=32'b00000000000000000000000000000100 RAM_DEPTH=32'b00000000000000000100000000000000 ECC_ENABLE=32'b00000000000000000000000000000000 ROM=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b00000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b00000000000000000000000000000000 BOOTROM_DEST_ADDR=32'b00000000000000000000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm_byte_shim=32'b00000000000000000000000000000001 RAM_DATA_WIDTH=32'b00000000000000000000000000100000 CPU_D_DEBUG_PRESENT=32'b00000000000000000000000000000001 NUM_REQUESTERS=32'b00000000000000000000000000000010 RAM_WEN_WIDTH=32'b00000000000000000000000000000001 UDMA_DAP_PRESENT=32'b00000000000000000000000000000000 BH_INIT=2'b00 BH_READ=2'b01 BH_WRITE=2'b10 Generated name = miv_rv32_opsrv_tcm_Z13 Running optimization stage 1 on OR4 ....... Running optimization stage 1 on CFG2 ....... Running optimization stage 1 on CFG3 ....... Running optimization stage 1 on OR2 ....... Running optimization stage 1 on RAM1K20 ....... Running optimization stage 1 on INV ....... Running optimization stage 1 on GND ....... Running optimization stage 1 on VCC ....... RAM_DEPTH=32'b00000000000000000100000000000000 Generated name = miv_rv32_ram_singleport_lp_16384 Running optimization stage 1 on miv_rv32_ram_singleport_lp_16384 ....... @W:CL168 : miv_rv32_ram_singleport_lp.v(8807) | Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8734) | Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8645) | Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8564) | Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8534) | Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8428) | Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8318) | Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8262) | Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8259) | Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8222) | Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8170) | Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8132) | Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8122) | Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8073) | Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(8033) | Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7955) | Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7936) | Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7891) | Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7771) | Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7761) | Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7720) | Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7681) | Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7577) | Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7537) | Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7411) | Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7302) | Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7298) | Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7172) | Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7133) | Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7074) | Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(7022) | Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6954) | Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6870) | Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6809) | Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6759) | Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6709) | Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6670) | Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6607) | Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6561) | Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6399) | Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6361) | Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6340) | Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6281) | Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6241) | Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6151) | Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6090) | Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6048) | Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(6002) | Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5940) | Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5934) | Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5869) | Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5825) | Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5779) | Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5702) | Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5599) | Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5529) | Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5462) | Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5416) | Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5266) | Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5257) | Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5212) | Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5117) | Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5114) | Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5107) | Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5083) | Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(5060) | Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4982) | Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4936) | Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4858) | Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4855) | Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4847) | Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4831) | Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4709) | Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4654) | Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4610) | Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4505) | Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4462) | Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4367) | Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4346) | Removing instance \CFG2_BLKX2[27] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4282) | Removing instance miv_rv32_ram_singleport_lp_R91C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4237) | Removing instance miv_rv32_ram_singleport_lp_R83C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4193) | Removing instance miv_rv32_ram_singleport_lp_R113C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4154) | Removing instance miv_rv32_ram_singleport_lp_R110C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4090) | Removing instance miv_rv32_ram_singleport_lp_R112C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4015) | Removing instance miv_rv32_ram_singleport_lp_R67C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(4009) | Removing instance \CFG2_BLKY2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3968) | Removing instance miv_rv32_ram_singleport_lp_R75C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3930) | Removing instance miv_rv32_ram_singleport_lp_R59C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3927) | Removing instance \CFG2_BLKX2[14] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3888) | Removing instance miv_rv32_ram_singleport_lp_R78C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3837) | Removing instance miv_rv32_ram_singleport_lp_R126C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3797) | Removing instance \CFG2_BLKX2[31] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3738) | Removing instance miv_rv32_ram_singleport_lp_R109C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3676) | Removing instance miv_rv32_ram_singleport_lp_R82C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3657) | Removing instance \CFG2_BLKY2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3513) | Removing instance miv_rv32_ram_singleport_lp_R35C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3470) | Removing instance miv_rv32_ram_singleport_lp_R38C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : miv_rv32_ram_singleport_lp.v(3462) | Removing instance CFG3_20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. Only the first 100 messages of id 'CL168' are reported. To see all messages use 'report_messages -log F:\DG0799_final\Libero_Project\Libero_Project\synthesis\synlog\top_compiler.srr -id CL168' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL168} -count unlimited' in the Tcl shell. Running optimization stage 1 on miv_rv32_opsrv_tcm_Z13 ....... @W:CL169 : miv_rv32_opsrv_merged.v(9208) | Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers. @W:CL169 : miv_rv32_opsrv_merged.v(9208) | Pruning unused register tcm_dap_access_disable_reg. Make sure that there are no unused intermediate registers. @W:CL265 : miv_rv32_opsrv_merged.v(9510) | Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal. @W:CL271 : miv_rv32_opsrv_merged.v(9303) | Pruning unused bits 31 to 16 of cpu_d_req_addr_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL271 : miv_rv32_opsrv_merged.v(9303) | Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Running optimization stage 1 on miv_rv32_opsrv_Z12 ....... FAMILY=32'b00000000000000000000000000011010 RESET_VECTOR_ADDR_1=16'b1000000000000000 RESET_VECTOR_ADDR_0=16'b0000000000000000 DEBUGGER=1'b1 AXI_MASTER_TYPE=32'b00000000000000000000000000000000 AXI_SLAVE_MIRROR=32'b00000000000000000000000000000000 AXI_START_ADDR_1=16'b0110000000000000 AXI_START_ADDR_0=16'b0000000000000000 AXI_END_ADDR_1=16'b0110111111111111 AXI_END_ADDR_0=16'b1111111111111111 AHB_MASTER_TYPE=32'b00000000000000000000000000000000 AHB_SLAVE_MIRROR=32'b00000000000000000000000000000001 AHB_START_ADDR_1=16'b1000000000000000 AHB_START_ADDR_0=16'b0000000000000000 AHB_END_ADDR_1=16'b1000111111111111 AHB_END_ADDR_0=16'b1111111111111111 APB_MASTER_TYPE=32'b00000000000000000000000000000001 APB_SLAVE_MIRROR=32'b00000000000000000000000000000000 APB_START_ADDR_1=16'b0110000000000000 APB_START_ADDR_0=16'b0000000000000000 APB_END_ADDR_1=16'b0110111111111111 APB_END_ADDR_0=16'b1111111111111111 TCM_PRESENT=32'b00000000000000000000000000000001 TCM_START_ADDR_1=16'b1000000000000000 TCM_START_ADDR_0=16'b0000000000000000 TCM_END_ADDR_1=16'b1000000000000000 TCM_END_ADDR_0=16'b1111111111111111 TCM_TAS_PRESENT=32'b00000000000000000000000000000000 TAS_START_ADDR_1=16'b0100000000000000 TAS_START_ADDR_0=16'b0000000000000000 TAS_END_ADDR_1=16'b0100000000000000 TAS_END_ADDR_0=16'b0011111111111111 GEN_DECODE_RV32=32'b00000000000000000000000000000000 GEN_MUL_TYPE=32'b00000000000000000000000000000000 VECTORED_INTERRUPTS=32'b00000000000000000000000000000000 NUM_EXT_IRQS=32'b00000000000000000000000000000000 FWD_REGS=32'b00000000000000000000000000000000 ECC_ENABLE=32'b00000000000000000000000000000000 INTERNAL_MTIME=32'b00000000000000000000000000000000 INTERNAL_MTIME_IRQ=32'b00000000000000000000000000000000 MTIME_PRESCALER=32'b00000000000000000000000001100100 GPR_REGS=32'b00000000000000000000000000000000 BOOTROM_PRESENT=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_START_ADDR_LOWER=16'b0000000000000000 BOOTROM_SRC_END_ADDR_UPPER=16'b1000000000000000 BOOTROM_SRC_END_ADDR_LOWER=16'b0011111111111111 BOOTROM_DEST_ADDR_UPPER=16'b0100000000000000 BOOTROM_DEST_ADDR_LOWER=16'b0000000000000000 RECONFIG_BOOTROM=32'b00000000000000000000000000000000 l_hart_id=32'b00000000000000000000000000000000 USE_BUS_PARITY=32'b00000000000000000000000000000000 TCM0_UDMA_PRESENT=32'b00000000000000000000000000000000 APB_MSTR_REGISTER_IO=32'b00000000000000000000000000000001 CPU_ADDR_WIDTH=32'b00000000000000000000000000100000 AXI_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 APB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 AHB_MSTR_ADDR_WIDTH=32'b00000000000000000000000000100000 UDMA_PRESENT=32'b00000000000000000000000000000000 UDMA_CTRL_ADDR_WIDTH=32'b00000000000000000000000000100000 OPSRV_CFG_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM0_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM0_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM0_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 TCM_TAS_ADDR_WIDTH=32'b00000000000000000000000000100000 MAX_EXT_IRQS=32'b00000000000000000000000000000110 TCM1_ADDR_WIDTH=32'b00000000000000000000000000100000 TCM1_CPU_I_PRESENT=32'b00000000000000000000000000000001 TCM1_CPU_D_PRESENT=32'b00000000000000000000000000000001 TCM1_USE_RAM_PARITY_BITS=32'b00000000000000000000000000000000 l_opsrv_cfg_axi_mstr_present=32'b00000000000000000000000000000000 l_opsrv_cfg_ahb_mstr_present=32'b00000000000000000000000000000000 l_opsrv_cfg_apb_mstr_present=32'b00000000000000000000000000000001 l_opsrv_cfg_core_debug=1'b1 l_core_cfg_hw_debug=1'b1 l_core_cfg_num_triggers=32'b00000000000000000000000000000010 l_opsrv_cfg_tcm_tas_present=32'b00000000000000000000000000000000 l_opsrv_cfg_tcm0_tas_present=32'b00000000000000000000000000000000 l_apb_mstr_start_addr=32'b01100000000000000000000000000000 l_apb_mstr_end_addr=32'b01101111111111111111111111111111 l_tcm0_start_addr=32'b10000000000000000000000000000000 l_tcm0_end_addr=32'b10000000000000001111111111111111 l_tcm_tas_tcm0_start_addr=32'b00001111111111111111111111100100 l_tcm_tas_tcm0_end_addr=32'b00001111111111111111111111100101 l_axi_mstr_start_addr=32'b00001111111111111111111111100110 l_axi_mstr_end_addr=32'b00001111111111111111111111100111 l_ahb_mstr_start_addr=32'b00001111111111111111111111101000 l_ahb_mstr_end_addr=32'b00001111111111111111111111101001 l_tcm1_start_addr=32'b00000000000000001010000000000000 l_tcm1_end_addr=32'b00000000000000001010001000000000 l_tcm_tas_tcm1_start_addr=32'b00001111111111111111111111101100 l_tcm_tas_tcm1_end_addr=32'b00001111111111111111111111101101 l_tcm_tas_udma_ctrl_start_addr=32'b00001111111111111111111111101110 l_tcm_tas_udma_ctrl_end_addr=32'b00001111111111111111111111101111 l_udma_ctrl_start_addr=32'b00001111111111111111111111100000 l_udma_ctrl_end_addr=32'b00001111111111111111111111110001 l_opsrv_cfg_start_addr=32'b00000000000000000110000000000000 l_opsrv_cfg_end_addr=32'b00000000000000000110111111111111 l_core_cfg_time_count_width=32'b00000000000000000000000001000000 l_opsrv_cfg_tcm0_present=32'b00000000000000000000000000000001 l_opsrv_cfg_tcm1_present=32'b00000000000000000000000000000000 BOOTROM_SRC_START_ADDR=32'b10000000000000000000000000000000 BOOTROM_SRC_END_ADDR=32'b10000000000000000011111111111111 BOOTROM_DEST_ADDR=32'b01000000000000000000000000000000 l_core_reset_vector=32'b10000000000000000000000000000000 l_core_mtvec_offset=28'b0000000000000000000000000100 l_core_static_mtvec_base=32'b10000000000000000000000000000100 l_core_cfg_static_mtvec_base=1'b0 l_core_cfg_static_mtvec_mode=1'b1 l_core_static_mtvec_mode=2'b00 l_core_cfg_hw_multiply_divide=32'b00000000000000000000000000000000 l_core_cfg_hw_compressed=32'b00000000000000000000000000000000 l_core_cfg_hw_macc_multiplier=32'b00000000000000000000000000000000 l_core_num_sys_ext_irqs=4'b1000 l_core_cfg_lsu_fwd=1'b0 l_core_cfg_csr_fwd=1'b0 l_core_cfg_exu_fwd=1'b0 l_core_cfg_gpr_type=1'b0 Generated name = MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z14 @W:CG360 : miv_rv32.v(315) | Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it. @W:CG360 : miv_rv32.v(319) | Removing wire APB_MSTR_PRDATA_P, as there is no assignment to it. Running optimization stage 1 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z14 ....... @W:CS263 : MIV_RV32_C0.v(285) | Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port. Running optimization stage 1 on MIV_RV32_C0 ....... @W:CG1283 : PF_CCC_0_PF_CCC_0_0_PF_CCC.v(39) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on PLL ....... Running optimization stage 1 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Running optimization stage 1 on PF_CCC_0 ....... @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on INIT ....... @W:CG1283 : pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v(50) | Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on BANKEN ....... Running optimization stage 1 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Running optimization stage 1 on pf_init_monitor_0 ....... ST_RSWT=2'b00 ST_RWAT=2'b01 ST_LSWT=2'b10 ST_LWAT=2'b11 STEP=32'b00000000000000000000000000000011 COMP0_STEP=32'b00000000000000000000000000000000 COMP1_STEP=32'b00000000000000000000000000000100 COMP2_STEP=32'b00000000000000000000000000000001 COMP3_STEP=32'b00000000000000000000000000000001 EYEWIDTH=3'b001 Generated name = CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 Running optimization stage 1 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... Running optimization stage 1 on OUTBUF_DIFF ....... Running optimization stage 1 on IOD ....... @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(70) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v(64) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v(67) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(49) | Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(50) | Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(51) | Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(52) | Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54) | Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(54) | Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(59) | Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94) | Input RX_P on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. @W:CG781 : PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v(94) | Input RX_N on instance I_IOD_0 is undriven; assigning to 0. Simulation mismatch possible. Either assign the input or remove the declaration. Running optimization stage 1 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Running optimization stage 1 on LANECTRL ....... ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 @W:CG360 : PF_LANECTRL_PAUSE_SYNC.v(21) | Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Running optimization stage 1 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Running optimization stage 1 on RCLKINT ....... Running optimization stage 1 on PF_IOD_CDR_C0 ....... Running optimization stage 1 on HS_IO_CLK ....... @W:CG1283 : PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v(47) | Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on DLL ....... @W:CG1283 : PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v(87) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Running optimization stage 1 on ICB_CLKDIV ....... Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Running optimization stage 1 on COREDELAYCODE_TIP ....... ENABLE_PAUSE_EXTENSION=2'b00 Generated name = PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 @W:CG360 : PF_LANECTRL_PAUSE_SYNC.v(21) | Removing wire pause_sync_0_i, as there is no assignment to it. Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... Running optimization stage 1 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Running optimization stage 1 on PF_IOD_CDR_CCC_C0 ....... Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on PF_IOD_CDR_CCC_C0 ....... Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL ....... Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input CLK is unused. @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input RESET is unused. Running optimization stage 2 on COREDELAYCODE_TIP ....... @N:CL201 : CoreDelayCode_TIP.v(59) | Trying to extract state machine for register state. Extracted state machine for register state State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV ....... Running optimization stage 2 on ICB_CLKDIV ....... Running optimization stage 2 on PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC ....... Running optimization stage 2 on DLL ....... Running optimization stage 2 on HS_IO_CLK ....... Running optimization stage 2 on PF_IOD_CDR_C0 ....... @N:CL159 : PF_IOD_CDR_C0.v(69) | Input DLL_LOCK is unused. @N:CL159 : PF_IOD_CDR_C0.v(76) | Input PLL_LOCK is unused. Running optimization stage 2 on RCLKINT ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0 ....... @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input CLK is unused. @N:CL159 : PF_LANECTRL_PAUSE_SYNC.v(15) | Input RESET is unused. Running optimization stage 2 on LANECTRL ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD ....... Running optimization stage 2 on PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD ....... @N:CL159 : PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v(31) | Input FAB_CLK is unused. Running optimization stage 2 on IOD ....... Running optimization stage 2 on OUTBUF_DIFF ....... Running optimization stage 2 on CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1 ....... @N:CL201 : corecdr4_cntl_tip.v(117) | Trying to extract state machine for register tune_st. Extracted state machine for register tune_st State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on pf_init_monitor_0 ....... Running optimization stage 2 on pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR ....... Running optimization stage 2 on BANKEN ....... Running optimization stage 2 on INIT ....... Running optimization stage 2 on PF_CCC_0 ....... Running optimization stage 2 on PF_CCC_0_PF_CCC_0_0_PF_CCC ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on MIV_RV32_C0 ....... Running optimization stage 2 on MIV_RV32_C0_MIV_RV32_C0_0_MIV_RV32_Z14 ....... @W:CL156 : miv_rv32.v(319) | *Input APB_MSTR_PRDATA_P[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : miv_rv32.v(465) | *Input tcm1_dap_access_disable to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Running optimization stage 2 on miv_rv32_ram_singleport_lp_16384 ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on INV ....... Running optimization stage 2 on RAM1K20 ....... Running optimization stage 2 on OR2 ....... Running optimization stage 2 on CFG3 ....... Running optimization stage 2 on CFG2 ....... Running optimization stage 2 on OR4 ....... Running optimization stage 2 on miv_rv32_opsrv_tcm_Z13 ....... @N:CL201 : miv_rv32_opsrv_merged.v(9303) | Trying to extract state machine for register cpu_d_wr_rd_state. Extracted state machine for register cpu_d_wr_rd_state State machine has 3 reachable states with original encodings of: 00 01 10 @W:CL279 : miv_rv32_opsrv_merged.v(9303) | Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL246 : miv_rv32_opsrv_merged.v(9075) | Input port bits 31 to 16 of cpu_i_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(9075) | Input port bits 1 to 0 of cpu_i_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(9088) | Input port bits 31 to 16 of cpu_d_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(9088) | Input port bits 1 to 0 of cpu_d_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : miv_rv32_opsrv_merged.v(9133) | *Unassigned bits of tcm_ram_sb_out[3:0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : miv_rv32_opsrv_merged.v(9065) | Input opsrv_parity_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9074) | Input cpu_i_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9076) | Input cpu_i_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9078) | Input cpu_i_resp_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9084) | Input cpu_d_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9086) | Input cpu_d_req_read is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9087) | Input cpu_d_req_write is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9089) | Input cpu_d_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9091) | Input cpu_d_req_wr_data_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9093) | Input cpu_d_resp_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9099) | Input udma_req_valid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9101) | Input udma_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9102) | Input udma_req_wr_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9103) | Input udma_req_read is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9104) | Input udma_req_write is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9105) | Input udma_req_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9106) | Input udma_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9107) | Input udma_req_len is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9108) | Input udma_req_wr_data is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9109) | Input udma_req_wr_data_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9111) | Input udma_resp_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9118) | Input tcm_dma_access_disable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9119) | Input tcm_dap_access_disable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9120) | Input tcm_dap_req_valid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9122) | Input tcm_dap_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9123) | Input tcm_dap_req_wr_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9124) | Input tcm_dap_req_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9125) | Input tcm_dap_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9126) | Input tcm_dap_req_wr_data is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9127) | Input tcm_dap_req_wr_data_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9129) | Input tcm_dap_resp_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(9134) | Input tcm_ram_sb_in is unused. Running optimization stage 2 on miv_rv32_fixed_arb_3s ....... Running optimization stage 2 on miv_rv32_rr_pri_arb_3s_1s_1s ....... @N:CL201 : miv_rv32_opsrv_merged.v(14288) | Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 7 reachable states with original encodings of: 001 010 011 100 101 110 111 Running optimization stage 2 on miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5 ....... @N:CL201 : miv_rv32_opsrv_merged.v(6099) | Trying to extract state machine for register gen_apb_byte_shim.apb_st. Extracted state machine for register gen_apb_byte_shim.apb_st State machine has 6 reachable states with original encodings of: 000 001 010 011 100 101 @N:CL159 : miv_rv32_opsrv_merged.v(5931) | Input opsrv_parity_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5938) | Input cpu_i_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5940) | Input cpu_i_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5942) | Input cpu_i_resp_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5948) | Input cpu_d_req_rd_byte_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5951) | Input cpu_d_req_addr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(5955) | Input cpu_d_resp_ready is unused. Running optimization stage 2 on miv_rv32_fixed_arb_2s ....... Running optimization stage 2 on miv_rv32_rr_pri_arb_2s_1s_1s ....... @N:CL201 : miv_rv32_opsrv_merged.v(14288) | Trying to extract state machine for register hipri_req_ptr. Extracted state machine for register hipri_req_ptr State machine has 3 reachable states with original encodings of: 01 10 11 Running optimization stage 2 on miv_rv32_opsrv_debug_1 ....... Running optimization stage 2 on miv_rv32_opsrv_debug_du ....... @N:CL201 : miv_rv32_opsrv_merged.v(11381) | Trying to extract state machine for register debug_state. Extracted state machine for register debug_state State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 @N:CL201 : miv_rv32_opsrv_merged.v(10991) | Trying to extract state machine for register command_reg_state. @N:CL159 : miv_rv32_opsrv_merged.v(10455) | Input dmi_resp_ready is unused. Running optimization stage 2 on miv_rv32_opsrv_debug_sba ....... @N:CL201 : miv_rv32_opsrv_merged.v(11826) | Trying to extract state machine for register sba_state. Extracted state machine for register sba_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on miv_rv32_opsrv_debug_fifo_1s_34s_1s_0s_2s ....... Running optimization stage 2 on miv_rv32_opsrv_debug_fifo_1s_41s_1s_0s_2s ....... Running optimization stage 2 on miv_rv32_opsrv_dtm_jtag_1 ....... @N:CL201 : miv_rv32_opsrv_merged.v(12852) | Trying to extract state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat. Extracted state machine for register gen_shift_register_active_high.gen_shift_register_active_low.dtmcs_dmistat State machine has 4 reachable states with original encodings of: 00 01 10 11 @N:CL201 : miv_rv32_opsrv_merged.v(12732) | Trying to extract state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState. Extracted state machine for register gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState State machine has 16 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 @N:CL159 : miv_rv32_opsrv_merged.v(12661) | Input dtm_req_ready is unused. Running optimization stage 2 on miv_rv32_opsrv_Z12 ....... @N:CL159 : miv_rv32_opsrv_merged.v(208) | Input tcm1_cpu_access_disable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(209) | Input tcm1_dma_access_disable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(210) | Input tcm1_dap_access_disable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(211) | Input tcm_dap_apb_slv_paddr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(212) | Input tcm_dap_apb_slv_paddr_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(213) | Input tcm_dap_apb_slv_pprot is unused. @N:CL159 : miv_rv32_opsrv_merged.v(214) | Input tcm_dap_apb_slv_psel is unused. @N:CL159 : miv_rv32_opsrv_merged.v(215) | Input tcm_dap_apb_slv_penable is unused. @N:CL159 : miv_rv32_opsrv_merged.v(216) | Input tcm_dap_apb_slv_pwrite is unused. @N:CL159 : miv_rv32_opsrv_merged.v(217) | Input tcm_dap_apb_slv_pwdata is unused. @N:CL159 : miv_rv32_opsrv_merged.v(218) | Input tcm_dap_apb_slv_pwdata_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(229) | Input tcm1_ram_sb_in is unused. @N:CL159 : miv_rv32_opsrv_merged.v(233) | Input axi_mstr_aclk_en is unused. @N:CL159 : miv_rv32_opsrv_merged.v(242) | Input axi_mstr_arready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(245) | Input axi_mstr_rresp is unused. @N:CL159 : miv_rv32_opsrv_merged.v(246) | Input axi_mstr_rdata is unused. @N:CL159 : miv_rv32_opsrv_merged.v(247) | Input axi_mstr_rlast is unused. @N:CL159 : miv_rv32_opsrv_merged.v(248) | Input axi_mstr_rid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(250) | Input axi_mstr_rvalid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(251) | Input axi_mstr_r_data_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(261) | Input axi_mstr_awready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(267) | Input axi_mstr_wready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(270) | Input axi_mstr_bresp is unused. @N:CL159 : miv_rv32_opsrv_merged.v(271) | Input axi_mstr_bid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(273) | Input axi_mstr_bvalid is unused. @N:CL159 : miv_rv32_opsrv_merged.v(286) | Input ahb_mstr_hrdata is unused. @N:CL159 : miv_rv32_opsrv_merged.v(287) | Input ahb_mstr_hrdata_p is unused. @N:CL159 : miv_rv32_opsrv_merged.v(288) | Input ahb_mstr_hready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(289) | Input ahb_mstr_hresp is unused. Running optimization stage 2 on miv_rv32_opsrv_interconnect_Z11 ....... @W:CL246 : miv_rv32_opsrv_merged.v(7098) | Input port bits 11 to 0 of cfg_apb_mstr_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(7099) | Input port bits 11 to 0 of cfg_apb_mstr_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(7104) | Input port bits 11 to 0 of cfg_opsrv_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(7105) | Input port bits 11 to 0 of cfg_opsrv_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(7106) | Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(7107) | Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size. @N:CL159 : miv_rv32_opsrv_merged.v(7096) | Input cfg_axi_mstr_start_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7097) | Input cfg_axi_mstr_end_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7100) | Input cfg_ahb_mstr_start_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7101) | Input cfg_ahb_mstr_end_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7102) | Input cfg_udma_ctrl_start_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7103) | Input cfg_udma_ctrl_end_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7108) | Input cfg_tcm1_start_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7109) | Input cfg_tcm1_end_addr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7179) | Input apb_mstr_trx_os_d_rd is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7180) | Input apb_mstr_trx_os_d_wr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7208) | Input tcm0_trx_os_d_rd is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7209) | Input tcm0_trx_os_d_wr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7215) | Input tcm1_i_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7225) | Input tcm1_d_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7239) | Input tcm1_trx_os_d_rd is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7240) | Input tcm1_trx_os_d_wr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7246) | Input axi_mstr_i_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7256) | Input axi_mstr_d_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7271) | Input axi_mstr_trx_os_d_rd is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7272) | Input axi_mstr_trx_os_d_wr is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7276) | Input ahb_mstr_i_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7286) | Input ahb_mstr_d_req_ready is unused. @N:CL159 : miv_rv32_opsrv_merged.v(7300) | Input ahb_mstr_trx_os_d_rd is unused. Only the first 100 messages of id 'CL159' are reported. To see all messages use 'report_messages -log F:\DG0799_final\Libero_Project\Libero_Project\synthesis\synlog\top_compiler.srr -id CL159' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL159} -count unlimited' in the Tcl shell. Running optimization stage 2 on miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s ....... @W:CL246 : miv_rv32_opsrv_merged.v(13201) | Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_opsrv_merged.v(13206) | Input port bits 31 to 2 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on miv_rv32_buffer_4s_2s_1s_1s ....... Running optimization stage 2 on miv_rv32_buffer_11s_2s_1s_1s ....... Running optimization stage 2 on miv_rv32_buffer_6s_2s_1s_1s ....... Running optimization stage 2 on miv_rv32_core_Z10 ....... Running optimization stage 2 on miv_rv32_gpr_ram_array_32s_5s_32s ....... Running optimization stage 2 on miv_rv32_gpr_ram_0s_0 ....... Running optimization stage 2 on miv_rv32_expipe_Z9 ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_2147483648 ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_3s_1s_0s ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_1s_0 ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_30s_1s_0s ....... Running optimization stage 2 on miv_rv32_csr_privarch_Z8 ....... @W:CL247 : miv_rv32_core_merged.v(1738) | Input port bit 1 of excpt_trigger[1:0] is unused Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_32s_0s_0s ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_5s_1s_0 ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_31s_0s_0s ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_0s_0s ....... Running optimization stage 2 on miv_rv32_csr_gpr_state_reg_1s_1s_0s ....... Running optimization stage 2 on miv_rv32_csr_decode_0s_1 ....... Running optimization stage 2 on miv_rv32_priv_irq_8_0_0 ....... @W:CL246 : miv_rv32_core_merged.v(6537) | Input port bits 23 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_core_merged.v(6537) | Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_core_merged.v(6537) | Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : miv_rv32_core_merged.v(6537) | Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on miv_rv32_irq_reg_0s ....... Running optimization stage 2 on miv_rv32_bcu ....... Running optimization stage 2 on miv_rv32_exu_1s_1s_1_0s_0s_0_0_0 ....... Running optimization stage 2 on miv_rv32_csr_decode_1s_0s ....... Running optimization stage 2 on miv_rv32_idecode_1_0s_0s ....... Running optimization stage 2 on miv_rv32_lsu_32s_2s_1s_2s_2s ....... @W:CL260 : miv_rv32_core_merged.v(16782) | Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_core_merged.v(16782) | Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL190 : miv_rv32_core_merged.v(16782) | Optimizing register bit gen_req_buff_loop[0].req_buff_resp_fault[0][1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL190 : miv_rv32_core_merged.v(16782) | Optimizing register bit gen_req_buff_loop[1].req_buff_resp_fault[1][1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : miv_rv32_core_merged.v(16782) | Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @W:CL260 : miv_rv32_core_merged.v(16782) | Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on miv_rv32_fetch_unit_32s_2147483648_3s_2s_3s_2s_2s_0s_1s ....... Running optimization stage 2 on miv_rv32_ifu_iab_32s_2s_3s_2s ....... @N:CL134 : miv_rv32_core_merged.v(16192) | Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=16 @N:CL134 : miv_rv32_core_merged.v(16192) | Found RAM gen_buff_loop[0].buff_entry_data_resp, depth=3, width=32 @N:CL134 : miv_rv32_core_merged.v(16192) | Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 @N:CL134 : miv_rv32_core_merged.v(16192) | Found RAM gen_buff_loop[0].buff_entry_error_resp, depth=3, width=2 Running optimization stage 2 on INBUF_DIFF ....... Running optimization stage 2 on CoreUARTapb_0 ....... Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_CoreUARTapb_Z7 ....... @W:CL246 : CoreUARTapb.v(126) | Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size. @A:CL153 : CoreUARTapb.v(283) | *Unassigned bits of CUARTI1OI[2:0] are referenced and tied to 0 -- simulation mismatch possible. Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_COREUART_0s_0s_0s_26s_0s_0s ....... Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @N:CL201 : Rx_async.v(871) | Trying to extract state machine for register CUARTll0. Extracted state machine for register CUARTll0 State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @N:CL201 : Tx_async.v(301) | Trying to extract state machine for register CUARTlI0l. Extracted state machine for register CUARTlI0l State machine has 6 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 Running optimization stage 2 on CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s ....... Running optimization stage 2 on CORETSE_0 ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_CORETSE_26s_1s_1s_1s_1s_18s_11s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CNVRXO_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CNVRXI_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_TBI_26s_0s_0s_1s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PETCR ....... @N:CL135 : petcr.v(377) | Found sequential shift CORETSEo0OI with address depth of 3 words and data bit width of 1. @W:CL177 : petcr.v(333) | Sharing sequential element CORETSEioOI. Add a syn_preserve attribute to the element to prevent sharing. @W:CL177 : petcr.v(436) | Sharing sequential element CORETSEiOII. Add a syn_preserve attribute to the element to prevent sharing. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PETBM_26s_0s_1s ....... @W:CL190 : petbm.v(714) | Optimizing register bit CORETSEIi1o[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : petbm.v(714) | Pruning register bit 5 of CORETSEIi1o[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s ....... @N:CL201 : msgmii_peanx_top.v(3461) | Trying to extract state machine for register CORETSEilIlI. @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 14 of CORETSEo0o0[15:0] is unused @W:CL247 : msgmii_peanx_top.v(113) | Input port bit 11 of CORETSEo0o0[15:0] is unused Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEANX_SYNC_1s_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s ....... @N:CL201 : perex_pcs.v(4925) | Trying to extract state machine for register CORETSEIo10. Extracted state machine for register CORETSEIo10 State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on CORETSE_0_CORETSE_0_0_R10B8B ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEREX_PMA_26s_0s_1s_0_1_2_3_4 ....... @A:CL153 : perex_pma.v(219) | *Unassigned bits of CORETSEiOo0 are referenced and tied to 0 -- simulation mismatch possible. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PETEX_TOP_26s_0s_1s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_T8B10B ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CNVTXI_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MSGMII_CLKRST ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_RX4096X36_12s_1s_1s_4s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_TX2048X40_11s_1s_1s_4s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_SI_SAL_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MMCXWOL_1s_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_EIM_26s_1s ....... @W:CL246 : pemstat_eim.v(156) | Input port bits 24 to 20 of CORETSEo1Oo[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_STORE_26s ....... @W:CL247 : pemstat_store.v(181) | Input port bit 31 of CORETSEOllo[31:0] is unused Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINCNF_1s_26s ....... @W:CL246 : pemstat_sincnf.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_SADD_1s_26s ....... @W:CL246 : pemstat_sadd.v(54) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINCHD_1s_26s ....... @W:CL246 : pemstat_sinchd.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_SINC_1s_26s ....... @W:CL246 : pemstat_sinc.v(44) | Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_LADD_1s_26s ....... @W:CL246 : pemstat_ladd.v(54) | Input port bits 30 to 24 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_LINC_1s_26s ....... @W:CL246 : pemstat_linc.v(44) | Input port bits 30 to 18 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMSTAT_CNTRL_1s_26s ....... @W:CL247 : pemstat_cntrl.v(51) | Input port bit 22 of CORETSEoo[30:0] is unused @W:CL246 : pemstat_cntrl.v(51) | Input port bits 17 to 16 of CORETSEoo[30:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 31 to 30 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : pemstat_cntrl.v(62) | Input port bits 23 to 21 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_SIB_SYNC_2FLP_1s_19s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE_26s_0s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6 ....... @W:CL246 : tsmac_top.v(180) | Input port bits 31 to 10 of CORETSEl00lI[31:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : tsmac_top.v(180) | Input port bits 1 to 0 of CORETSEl00lI[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PE_MCXMAC_26s_0_0s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PECAR ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEHST_1s_26s ....... @A:CL153 : pehst.v(613) | *Unassigned bits of CORETSEOlI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(709) | *Unassigned bits of CORETSEIlI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(714) | *Unassigned bits of CORETSEllI1 are referenced and tied to 0 -- simulation mismatch possible. @A:CL153 : pehst.v(716) | *Unassigned bits of CORETSEolI1 are referenced and tied to 0 -- simulation mismatch possible. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PEMGT_1s_26s ....... @N:CL201 : pemgt.v(588) | Trying to extract state machine for register CORETSEo0o1. Extracted state machine for register CORETSEo0o1 State machine has 32 reachable states with original encodings of: 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PE_MCXMAC_CORE_26s_0_0s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PERMC_TOP_1s_26s ....... @W:CL247 : permc_top.v(98) | Input port bit 0 of CORETSEiI[1:0] is unused Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s ....... @W:CL138 : perfn_top.v(3490) | Removing register 'CORETSEOo' because it is only assigned 0 or its original value. @N:CL201 : perfn_top.v(5295) | Trying to extract state machine for register CORETSEoo. @W:CL246 : perfn_top.v(147) | Input port bits 1 to 0 of CORETSEil[7:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s ....... @N:CL135 : petfn_top.v(6630) | Found sequential shift CORETSEoIll with address depth of 3 words and data bit width of 8. @N:CL135 : petfn_top.v(7633) | Found sequential shift CORETSEilll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(7496) | Found sequential shift CORETSEllll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(7755) | Found sequential shift CORETSEI0ll with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(2998) | Found sequential shift CORETSEOoiI with address depth of 3 words and data bit width of 1. @N:CL135 : petfn_top.v(3171) | Found sequential shift CORETSEoOOl with address depth of 3 words and data bit width of 4. @N:CL135 : petfn_top.v(8862) | Found sequential shift CORETSEoIII with address depth of 4 words and data bit width of 1. @N:CL135 : petfn_top.v(8161) | Found sequential shift CORETSEIIII with address depth of 4 words and data bit width of 1. @N:CL201 : petfn_top.v(10871) | Trying to extract state machine for register CORETSEoIoI. @W:CL246 : petfn_top.v(219) | Input port bits 1 to 0 of CORETSEil1I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(221) | Input port bits 1 to 0 of CORETSEO01I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(223) | Input port bits 1 to 0 of CORETSEI01I[6:0] are unused. Assign logic for all port bits or change the input port size. @W:CL246 : petfn_top.v(231) | Input port bits 9 to 6 of CORETSEl01I[9:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PECRC_1s_26s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_PETMC_TOP_1s_26s ....... @W:CL247 : petmc_top.v(113) | Input port bit 0 of CORETSEiI[1:0] is unused Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXFIF_26s_11s_12s_32s_2s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXFIF_CLKRST ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXFIF_HST_Z5 ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0 ....... @N:CL201 : amcxtfif_wtm.v(309) | Trying to extract state machine for register CORETSEOloOI. Extracted state machine for register CORETSEOloOI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s ....... @W:CL246 : amcxrfif_sys.v(239) | Input port bits 39 to 36 of CORETSEoIii[39:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s ....... @N:CL135 : amcxrfif_fab.v(1591) | Found sequential shift CORETSElOoi with address depth of 3 words and data bit width of 1. @N:CL201 : amcxrfif_fab.v(1094) | Trying to extract state machine for register genblk1.CORETSEooIOI. Extracted state machine for register genblk1.CORETSEooIOI State machine has 5 reachable states with original encodings of: 0000 1000 1100 1110 1111 @W:CL247 : amcxrfif_fab.v(128) | Input port bit 12 of CORETSEiIii[13:0] is unused Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s ....... @N:CL201 : amcxtfif_sys.v(896) | Trying to extract state machine for register CORETSEOI1OI. Extracted state machine for register CORETSEOI1OI State machine has 6 reachable states with original encodings of: 000001 000010 000100 001000 010000 100000 Running optimization stage 2 on CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_MAPBE_HST_CNV_26s_0s_1s ....... @W:CL156 : mapbe_hst_cnv.v(203) | *Input CORETSElioOI[31:0] to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. @W:CL156 : mapbe_hst_cnv.v(206) | *Input CORETSEoioOI to expression [instance] has undriven bits; assigning undriven bits to 0. Simulation mismatch possible. Assign all bits of the input. Running optimization stage 2 on CORETSE_0_CORETSE_0_0_TSM_SYSREG_26s_1s_0s ....... Running optimization stage 2 on CORETSE_0_CORETSE_0_0_DECODER ....... Running optimization stage 2 on CORESPI_0 ....... Running optimization stage 2 on CORESPI_Z4 ....... Running optimization stage 2 on spi_32s_16s_32s_7s_0_0_1_0s ....... @W:CL246 : spi.v(70) | Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on spi_chanctrl_Z3 ....... @W:CL190 : spi_chanctrl.v(823) | Optimizing register bit stxs_bitsel[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL260 : spi_chanctrl.v(823) | Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. @N:CL201 : spi_chanctrl.v(416) | Trying to extract state machine for register mtx_state. Extracted state machine for register mtx_state State machine has 6 reachable states with original encodings of: 0000 0001 0010 0111 1000 1001 Running optimization stage 2 on spi_clockmux ....... Running optimization stage 2 on spi_fifo_16s_32s_5 ....... @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=1 @N:CL134 : spi_fifo.v(101) | Found RAM fifo_mem_q, depth=32, width=16 Running optimization stage 2 on spi_control_16s ....... Running optimization stage 2 on spi_rf_32s_7s_0 ....... @W:CL246 : spi_rf.v(42) | Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on CoreAPB3_0 ....... Running optimization stage 2 on CoreAPB3_Z2 ....... @W:CL246 : coreapb3.v(75) | Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on COREAPB3_MUXPTOB3 ....... Running optimization stage 2 on Core_reset_pf ....... Running optimization stage 2 on Core_reset_pf_Core_reset_pf_0_CORERESET_PF ....... @N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1. Running optimization stage 2 on core_jatg_debug_0 ....... Running optimization stage 2 on CLKINT ....... Running optimization stage 2 on COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0 ....... Running optimization stage 2 on BUFD ....... Running optimization stage 2 on corejtagdebug_bufd_34s ....... Running optimization stage 2 on UJTAG ....... Running optimization stage 2 on COREJTAGDEBUG_Z1 ....... Running optimization stage 2 on BIBUF ....... Running optimization stage 2 on AND2 ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:53s; CPU Time elapsed 0h:00m:48s; Memory used current: 239MB peak: 259MB) Process took 0h:00m:53s realtime, 0h:00m:48s cputime Process completed successfully. # Thu Feb 25 12:41:20 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File \\hyd-fs\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_Q202003MSP1\bin64\syn_nfilter.exe changed - recompiling File D:\Sreeja\DG0799_final\Libero_Project\Libero_Project\synthesis\synwork\layer0.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 129MB peak: 129MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Feb 25 12:41:22 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:55s; CPU Time elapsed 0h:00m:50s; Memory used current: 22MB peak: 23MB) Process took 0h:00m:55s realtime, 0h:00m:50s cputime Process completed successfully. # Thu Feb 25 12:41:22 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode File \\hyd-fs\sqatest5\releases\production\Synopsys\Synplify\pc\synplify_Q202003MSP1\bin64\syn_nfilter.exe changed - recompiling File D:\Sreeja\DG0799_final\Libero_Project\Libero_Project\synthesis\synwork\top_comp.srs changed - recompiling At syn_nfilter Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 146MB peak: 146MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Thu Feb 25 12:41:25 2021 ###########################################################] Premap Report # Thu Feb 25 12:41:26 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) Reading constraint file: F:\DG0799_final\Libero_Project\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "F:\DG0799_final\Libero_Project\Libero_Project\synthesis\top_scck.rpt" @W:BN544 : synthesis.fdc(12) | create_generated_clock with both -multiply_by and -divide_by not supported for this target technology @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 184MB peak: 184MB) Start loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 188MB) Finished loading timing files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 188MB peak: 190MB) @W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance Core_reset_pf_0.Core_reset_pf_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @N:FX1171 : mapbe_hst_cnv.v(469) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEIo1lI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(301) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEIi1lI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(301) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSElOiOI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(469) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEOOolI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(469) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEIOolI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(469) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEoi1lI[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(301) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEi11lI with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : mapbe_hst_cnv.v(301) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEloolI.CORETSEOooOI[7:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : petmc_top.v(2099) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEIoI1.CORETSEoO1I because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEIoI1.CORETSEiO1I. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : petfn_top.v(6558) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEi1II because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoI. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : petfn_top.v(6509) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEli1I because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEOlIl. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : perfn_top.v(4317) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEiO1 because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEioI1.CORETSEIo. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : permc_top.v(1915) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEO1i because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEOiI1.CORETSEl0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:FX1171 : msgmii_clkrst.v(195) | Found instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEOi0II with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : perex_pcs.v(3772) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEIiIi because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEIIo0. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_step.gen_bit_reset.state_val[0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_mtvec_base_writable.u_csr_gpr_state_reg_mtvec_base.gen_bit_reset.state_val[29:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.u_csr_gpr_state_reg_mcause_excpt_code.gen_bit_reset.state_val[4:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dcsr_cause.gen_bit_reset.state_val[2:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : miv_rv32_core_merged.v(5485) | Found instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_debug.u_csr_gpr_state_reg_dpc_pc.gen_bit_reset.state_val[31:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : miv_rv32_opsrv_merged.v(11140) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.miv_rv32_opsrv_debug_du_0.debug_gpr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.miv_rv32_opsrv_debug_du_0.debug_gpr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_opsrv_merged.v(11140) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.miv_rv32_opsrv_debug_du_0.debug_csr_rd_data_ready because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.miv_rv32_opsrv_debug_du_0.debug_csr_rd_en. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO111 : corejtagdebug.v(147) | Tristate driver UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) on net UJTAG_BYPASS_TDO_0_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(154) | Tristate driver UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) on net UJTAG_BYPASS_TDO_1_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(161) | Tristate driver UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) on net UJTAG_BYPASS_TDO_2_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) has its enable tied to GND. @N:MO111 : corejtagdebug.v(168) | Tristate driver UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) on net UJTAG_BYPASS_TDO_3_1 (in view: COREJTAGDEBUG_LIB.COREJTAGDEBUG_Z1(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(154) | Tristate driver CORETSEII1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEII1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(162) | Tristate driver CORETSEOl1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEOl1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(160) | Tristate driver CORETSEiI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEiI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(156) | Tristate driver CORETSElI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSElI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(158) | Tristate driver CORETSEoI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEoI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(90) | Tristate driver TXD_1 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXD_1 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[2\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_3(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[3\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_1(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[4\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_4(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[5\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_2(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[6\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_0(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[7\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_5(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[0\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_7(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6740) | Removing instance gen_ext_sys_irq\[1\]\.gen_ext_sys_irq_bit\.u_miv_rv32_irq_reg_ext_sys (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_6(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6666) | Removing instance u_miv_rv32_irq_reg_ext (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_10(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_core_merged.v(6687) | Removing instance u_miv_rv32_irq_reg_timer (in view: work.miv_rv32_priv_irq_8_0_0(verilog)) of type view:work.miv_rv32_irq_reg_0s_9(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_opsrv_merged.v(13336) | Removing instance u_opsrv_parity_en_reg (in view: work.miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s(verilog)) of type view:work.miv_rv32_csr_gpr_state_reg_1s_1s_0s_14(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_opsrv_merged.v(13539) | Removing instance gen_tcm0_irq_pend\.u_opsrv_irq_tcm0_ecc_err_corr_pend_reg (in view: work.miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s(verilog)) of type view:work.miv_rv32_csr_gpr_state_reg_1s_1s_0s_13(verilog) because it does not drive other instances. @N:BN115 : miv_rv32_opsrv_merged.v(13558) | Removing instance gen_tcm0_irq_pend\.u_opsrv_irq_tcm0_ecc_err_uncorr_pend_reg (in view: work.miv_rv32_opsrv_regs_12s_0s_1s_0s_4s_2s_1s(verilog)) of type view:work.miv_rv32_csr_gpr_state_reg_1s_1s_0s_12(verilog) because it does not drive other instances. @N:BN115 : pf_iod_cdr_c0_pf_lanectrl_0_pf_lanectrl.v(107) | Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL(verilog)) of type view:work.PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL_PAUSE_SYNC_0(verilog) because it does not drive other instances. @N:BN115 : pf_iod_cdr_ccc_c0_pf_lanectrl_core_reader_0_pf_lanectrl.v(93) | Removing instance I_LANECTRL_PAUSE_SYNC (in view: work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL(verilog)) of type view:work.PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL_PAUSE_SYNC_0(verilog) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance full_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_fifo.v(111) | Removing sequential instance empty_next_out (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pemgt.v(2294) | Removing sequential instance CORETSEoII1 (in view: work.CORETSE_0_CORETSE_0_0_PEMGT_1s_26s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_async.v(1613) | Removing sequential instance CUARTI0I (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN362 : rx_async.v(1613) | Removing sequential instance CUARTIO0 (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(14358) | Removing sequential instance sel_reg[2:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(630) | Removing sequential instance CORETSEOoOI (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(683) | Removing sequential instance CORETSEioOI (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1196) | Removing sequential instance CORETSEIO11 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1240) | Removing sequential instance CORETSEiO11 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(262) | Removing sequential instance CORETSEo1l0\.CORETSEI0l0 (in view: work.CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE_26s_0s_0s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : sib_sync_pulse.v(262) | Removing sequential instance CORETSEo1l0\.CORETSEI0l0 (in view: work.CORETSE_0_CORETSE_0_0_SIB_SYNC_PULSE_26s_0s_0s_0(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr_p (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : pecar.v(616) | Removing sequential instance CORETSEi1OI (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(669) | Removing sequential instance CORETSEooOI (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1182) | Removing sequential instance CORETSEOO11 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1226) | Removing sequential instance CORETSEoO11 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(420) | Removing sequential instance CORETSElol1 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(471) | Removing sequential instance CORETSEIil1 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pemgt.v(2778) | Removing sequential instance CORETSEIlOo (in view: work.CORETSE_0_CORETSE_0_0_PEMGT_1s_26s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(406) | Removing sequential instance CORETSEIol1 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(457) | Removing sequential instance CORETSEOil1 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1099) | Removing sequential instance CORETSEio01 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1143) | Removing sequential instance CORETSEli01 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_core_merged.v(9087) | Removing sequential instance ex_retr_pipe_implicit_pseudo_instr_retr (in view: work.miv_rv32_expipe_Z9(verilog)) of type view:PrimLib.dffe(prim) because it does not drive other instances. @N:BN362 : pecar.v(1085) | Removing sequential instance CORETSEoo01 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : pecar.v(1129) | Removing sequential instance CORETSEIi01 (in view: work.CORETSE_0_CORETSE_0_0_PECAR(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(13015) | Removing sequential instance genblk3\.gen_ir_and_Instruction_register_active_high\.gen_ir_and_Instruction_register_active_low\.dr_tdo (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(630) | Removing sequential instance mtx_spi_data_oen (in view: CORESPI_LIB.spi_chanctrl_Z3(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(1046) | Removing sequential instance CORETSElO1i (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(416) | Removing sequential instance mtx_oen (in view: CORESPI_LIB.spi_chanctrl_Z3(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(1082) | Removing sequential instance CORETSEoo0OI[10:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(1132) | Removing sequential instance CORETSEio0OI[11:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : amcxtfif_fab.v(992) | Removing sequential instance CORETSEIo0OI (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=952 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 245MB peak: 245MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load ----------------------------------------------------------------------------------------------------------------------------------------------------------------- 0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1 1 . PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 12.500 generated (from REF_CLK_0) (multiple) 4280 2 .. PHY_MDC_CLOCK 2.9 MHz 350.000 generated (from REF_CLK_0) default_clkgroup 0 0 - REFCLK_P 125.0 MHz 8.000 declared default_clkgroup 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT0_GRP 3 2 .. PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 8.000 generated (from REFCLK_P) Y_DIV_GRP 1208 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT1_GRP 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT2_GRP 1 1 . PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz 1.600 generated (from REFCLK_P) NWC_PLL_OUT3_GRP 1 0 - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 8.000 declared SGMII_CDR_0_0_CLK_OUT_GRP 1194 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - TCK 10.0 MHz 100.000 declared JTAG_Async_2 0 0 - COREJTAGDEBUG_Z1|iUDRCK_inferred_clock 100.0 MHz 10.000 inferred Inferred_clkgroup_2 188 0 - PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep 100.0 MHz 10.000 inferred Inferred_clkgroup_0 2 ================================================================================================================================================================= Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- REF_CLK_0 1 REF_CLK_0(port) PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.REF_CLK_0 - - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 4280 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0.OUT0(PLL) MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.resp_dest[1:0].C - PF_CCC_0_0.PF_CCC_0_0.clkint_0.I(BUFG) PHY_MDC_CLOCK 0 - - - - REFCLK_P 1 REFCLK_P(port) PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.REF_CLK_0 - INBUF_DIFF_0.PADP(INBUF_DIFF) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 3 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT0(PLL) PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.A - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3.A(HS_IO_CLK) PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 1208 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD.Y_DIV(ICB_CLKDIV) PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1:0].C - - PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT1(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[1] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7.A(HS_IO_CLK) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT2(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[2] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.REF_CLK(DLL) PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0.OUT3(PLL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK[3] - PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15.A(HS_IO_CLK) PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 1194 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R(LANECTRL) PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.FAB_CLK - PF_IOD_CDR_C0_0.RCLKINT_0.A(RCLKINT) System 0 - - - - TCK 0 TCK(port) - - - COREJTAGDEBUG_Z1|iUDRCK_inferred_clock 188 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst.UDRCK(UJTAG) MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.debug_resp_fifo.genblk1\.reset_sync_reg[1:0].C - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.un1_jtag_tck.I[0](inv) PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK(LANECTRL) PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.CDR_CLK - - ===================================================================================================================================================================================================================================================================================================================================================================================================================== @W:MT530 : pf_iod_cdr_c0_pf_iod_cdr_rx_n_0_pf_iod.v(48) | Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep which controls 2 sequential elements including PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0. This clock has no specified timing constraint which may adversely impact design performance. @W:MT530 : corejtagdebug_uj_jtag.v(215) | Found inferred clock COREJTAGDEBUG_Z1|iUDRCK_inferred_clock which controls 188 sequential elements including core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.state[4:0]. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file F:\DG0799_final\Libero_Project\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 234MB peak: 245MB) Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z3(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 Encoding state machine CORETSEOI1OI[5:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine genblk1\.CORETSEooIOI[4:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 Encoding state machine CORETSEOloOI[5:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine CORETSEo0o1[31:0] (in view: work.CORETSE_0_CORETSE_0_0_PEMGT_1s_26s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 Encoding state machine CORETSEIo10_1[3:0] (in view: work.CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4925) | There are no possible illegal states for state machine CORETSEIo10_1[3:0] (in view: work.CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s(verilog)); safe FSM implementation is not required. Encoding state machine CUARTlI0l[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 Encoding state machine CUARTll0[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_opsrv_merged.v(12852) | There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)); safe FSM implementation is not required. Encoding state machine sba_state[3:0] (in view: work.miv_rv32_opsrv_debug_sba(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_opsrv_merged.v(11826) | There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_opsrv_debug_sba(verilog)); safe FSM implementation is not required. Encoding state machine debug_state[5:0] (in view: work.miv_rv32_opsrv_debug_du(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog)) original code -> new code 01 -> 00 10 -> 01 11 -> 10 Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) original code -> new code 001 -> 0000001 010 -> 0000010 011 -> 0000100 100 -> 0001000 101 -> 0010000 110 -> 0100000 111 -> 1000000 Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_opsrv_tcm_Z13(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : corecdr4_cntl_tip.v(117) | There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required. Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coredelaycode_tip.v(59) | There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required. Finished constraint checker preprocessing (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:07s; Memory used current: 241MB peak: 245MB) @W:MF511 : | Found issues with constraints. Please check constraint checker report "F:\DG0799_final\Libero_Project\Libero_Project\synthesis\top_cck.rpt" . Finished constraint checker (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 256MB peak: 257MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:08s; Memory used current: 160MB peak: 257MB) Process took 0h:00m:09s realtime, 0h:00m:08s cputime # Thu Feb 25 12:41:35 2021 ###########################################################] Map & Optimize Report # Thu Feb 25 12:41:36 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: DESKTOP-3MQ3L41 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 119MB peak: 128MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 121MB peak: 128MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:01s; Memory used current: 123MB peak: 128MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 204MB peak: 204MB) @N:MO111 : tsmac_top.v(162) | Tristate driver CORETSEOl1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEOl1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(160) | Tristate driver CORETSEiI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEiI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(158) | Tristate driver CORETSEoI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEoI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(156) | Tristate driver CORETSElI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSElI1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : tsmac_top.v(154) | Tristate driver CORETSEII1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) on net CORETSEII1lI (in view: work.CORETSE_0_CORETSE_0_0_TSMAC_TOP_Z6(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(94) | Tristate driver TXER (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXER (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(92) | Tristate driver TXEN (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXEN (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(90) | Tristate driver TXD_1 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXD_1 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(90) | Tristate driver TXD_2 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXD_2 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:MO111 : coretse_top.v(90) | Tristate driver TXD_3 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) on net TXD_3 (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) has its enable tied to GND. @N:BN362 : pecar.v(951) | Removing sequential instance CORETSEilI1.CORETSEl101 (in view: work.CORETSE_0_CORETSE_0_0_PE_MCXMAC_26s_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : pecar.v(907) | Removing sequential instance CORETSEilI1.CORETSEI101 (in view: work.CORETSE_0_CORETSE_0_0_PE_MCXMAC_26s_0_0s_0s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : petcr.v(206) | Removing sequential instance CORETSElIi0.CORETSEl1OI (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_TBI_26s_0s_0s_1s(verilog)) of type view:PrimLib.sdffr(prim) because it does not drive other instances. @N:BN362 : coretse_top.v(1019) | Removing sequential instance CORETSEi01lI\.CORETSEO11lI[8:0] (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W:BN132 : petfn_top.v(10445) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEl1oI because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEI1oI. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found @W:FA239 : t8b10b.v(148) | ROM CORETSEiol0[5:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEIil0[1:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : t8b10b.v(148) | ROM CORETSEO0ol[7:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSEO0ol[7:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) with 32 words by 8 bits. @W:FA239 : t8b10b.v(148) | ROM CORETSEIil0[1:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : t8b10b.v(148) | Found ROM CORETSEIil0[1:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) with 32 words by 2 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEoiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(3418) | ROM CORETSEiiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEiiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 16 words by 1 bit. @W:FA239 : r10b8b.v(1950) | ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 12 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) with 46 words by 2 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @W:FA239 : r10b8b.v(3418) | ROM CORETSEoiol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(3418) | Found ROM CORETSEoiol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 16 words by 2 bits. @W:FA239 : r10b8b.v(1950) | ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 12 words by 1 bit. @W:FA239 : r10b8b.v(1261) | ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 14 words by 3 bits. @W:FA239 : r10b8b.v(1261) | ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(1261) | Found ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 14 words by 2 bits. @W:FA239 : r10b8b.v(268) | ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : r10b8b.v(268) | Found ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) with 46 words by 2 bits. @W:FA239 : miv_rv32_core_merged.v(16547) | ROM lsu_emi_req_write_1[1:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance. @N:MO106 : miv_rv32_core_merged.v(16547) | Found ROM lsu_emi_req_write_1[1:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) with 10 words by 2 bits. @N:BN362 : pemgt.v(2239) | Removing sequential instance CORETSElII1[4:0] (in view: work.CORETSE_0_CORETSE_0_0_PEMGT_1s_26s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : msgmii_cnvtxo.v(463) | Removing sequential instance CORETSEiioII (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO_26s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6099) | Removing sequential instance gen_apb_byte_shim\.pwdata_p[3:0] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. Finished RTL optimizations (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 216MB peak: 224MB) @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][3] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][8] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][7] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][5] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][8] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][7] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][5] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][3] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(4773) | Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX702 : spi_fifo.v(101) | Found startup values on RAM instance fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)). @N:FX702 : spi_fifo.v(101) | Found startup values on RAM instance fifo_mem_q[16:0] @W:FX107 : spi_fifo.v(101) | RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX702 : spi_fifo.v(101) | Found startup values on RAM instance fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)). @N:FX702 : spi_fifo.v(101) | Found startup values on RAM instance fifo_mem_q[16:0] Encoding state machine mtx_state[5:0] (in view: CORESPI_LIB.spi_chanctrl_Z3(verilog)) original code -> new code 0000 -> 000001 0001 -> 000010 0010 -> 000100 0111 -> 001000 1000 -> 010000 1001 -> 100000 @N:MO231 : spi_chanctrl.v(823) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z3(verilog) instance stxs_bitcnt[4:0] @N:MO231 : spi_chanctrl.v(286) | Found counter in view:CORESPI_LIB.spi_chanctrl_Z3(verilog) instance spi_clk_count[7:0] @N:FX403 : rx4096x36.v(139) | Property "block_ram" or "no_rw_check" found for RAM CORETSEo01lI.CORETSEIIil[35:0] with specified coding style. Inferring block RAM. @W:FX107 : rx4096x36.v(139) | RAM CORETSEo01lI.CORETSEIIil[35:0] (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : tx2048x40.v(139) | Property "block_ram" or "no_rw_check" found for RAM CORETSEl01lI.CORETSEIIil[39:0] with specified coding style. Inferring block RAM. @W:FX107 : tx2048x40.v(139) | RAM CORETSEl01lI.CORETSEIIil[39:0] (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MO231 : amcxtfif_fab.v(861) | Found counter in view:work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog) instance CORETSEO00OI[11:0] @N:MF179 : amcxtfif_fab.v(809) | Found 11 by 11 bit equality operator ('==') un3_CORETSEollOI (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_FAB_26s_11s_32s_2s_0_0_1s(verilog)) Encoding state machine CORETSEOI1OI[5:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MF179 : amcxtfif_sys.v(2584) | Found 12 by 12 bit equality operator ('==') un1_CORETSEil1OI (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_SYS_26s_11s_32s_2s_0s_0_0_1s(verilog)) Encoding state machine genblk1\.CORETSEooIOI[4:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog)) original code -> new code 0000 -> 00001 1000 -> 00010 1100 -> 00100 1110 -> 01000 1111 -> 10000 @N:MF179 : amcxrfif_fab.v(541) | Found 13 by 13 bit equality operator ('==') un4_CORETSEIlIOI (in view: work.CORETSE_0_CORETSE_0_0_AMCXRFIF_FAB_26s_12s_32s_2s_0_1s(verilog)) @N:MO231 : amcxrfif_sys.v(2334) | Found counter in view:work.CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s(verilog) instance CORETSEiolOI[13:0] @N:MF179 : amcxrfif_sys.v(1440) | Found 12 by 12 bit equality operator ('==') un3_CORETSEollOI (in view: work.CORETSE_0_CORETSE_0_0_AMCXRFIF_SYS_26s_0s_12s_32s_2s_0_0_0_1s(verilog)) Encoding state machine CORETSEOloOI[5:0] (in view: work.CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 @N:MO231 : amcxtfif_wtm.v(569) | Found counter in view:work.CORETSE_0_CORETSE_0_0_AMCXTFIF_WTM_26s_12s_1s_0_0(verilog) instance CORETSEIloOI[15:0] @N:MF179 : | Found 17 by 17 bit equality operator ('==') un12_CORETSEo00l (in view: work.CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(10178) | Found 16 by 16 bit equality operator ('==') un18_CORETSEo00l (in view: work.CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(5508) | Found 10 by 10 bit equality operator ('==') CORETSEl1Il (in view: work.CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s(verilog)) @N:MF179 : petfn_top.v(4660) | Found 16 by 16 bit equality operator ('==') un3_CORETSEiOIl (in view: work.CORETSE_0_CORETSE_0_0_PETFN_TOP_26s_0s_0_1s(verilog)) @N:MO231 : perfn_top.v(2564) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s(verilog) instance CORETSEool[14:0] @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[0] (in view: work.CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : perfn_top.v(3798) | Removing sequential instance CORETSEOOI[1] (in view: work.CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:MF179 : perfn_top.v(4521) | Found 16 by 16 bit equality operator ('==') un6_CORETSEiI1 (in view: work.CORETSE_0_CORETSE_0_0_PERFN_TOP_26s_0s_0_1s(verilog)) Encoding state machine CORETSEo0o1[31:0] (in view: work.CORETSE_0_CORETSE_0_0_PEMGT_1s_26s(verilog)) original code -> new code 00000 -> 00000000000000000000000000000001 00001 -> 00000000000000000000000000000010 00010 -> 00000000000000000000000000000100 00011 -> 00000000000000000000000000001000 00100 -> 00000000000000000000000000010000 00101 -> 00000000000000000000000000100000 00110 -> 00000000000000000000000001000000 00111 -> 00000000000000000000000010000000 01000 -> 00000000000000000000000100000000 01001 -> 00000000000000000000001000000000 01010 -> 00000000000000000000010000000000 01011 -> 00000000000000000000100000000000 01100 -> 00000000000000000001000000000000 01101 -> 00000000000000000010000000000000 01110 -> 00000000000000000100000000000000 01111 -> 00000000000000001000000000000000 10000 -> 00000000000000010000000000000000 10001 -> 00000000000000100000000000000000 10010 -> 00000000000001000000000000000000 10011 -> 00000000000010000000000000000000 10100 -> 00000000000100000000000000000000 10101 -> 00000000001000000000000000000000 10110 -> 00000000010000000000000000000000 10111 -> 00000000100000000000000000000000 11000 -> 00000001000000000000000000000000 11001 -> 00000010000000000000000000000000 11010 -> 00000100000000000000000000000000 11011 -> 00001000000000000000000000000000 11100 -> 00010000000000000000000000000000 11101 -> 00100000000000000000000000000000 11110 -> 01000000000000000000000000000000 11111 -> 10000000000000000000000000000000 @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEoo0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEIi0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEli0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEoi0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEii0o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEOO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEIO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSElO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEoO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEiO1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEOI1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEII1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSElI1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEll1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEol1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEil1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEO01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEI01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEl01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinchd.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEo01o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEO11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sinc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEI11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEl11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEo11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEi11o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEOo1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSEIo1o.CORETSEl00o[11:0] @N:MO231 : pemstat_sincnf.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog) instance CORETSEiIlo.CORETSElo1o.CORETSEl00o[11:0] @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[30] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[29] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[28] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[27] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[26] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[25] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : pemstat_eim.v(1986) | Register bit CORETSEIllo.CORETSEII0o[24] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2224) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[25] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[24]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2224) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[8] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MO231 : pemstat_linc.v(137) | Found counter in view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_LINC_1s_26s(verilog) instance CORETSEl00o[17:0] @N:MO231 : mmcxwol.v(1039) | Found counter in view:work.CORETSE_0_CORETSE_0_0_MMCXWOL_1s_26s(verilog) instance CORETSEIilII[4:0] @N:MO231 : mmcxwol.v(836) | Found counter in view:work.CORETSE_0_CORETSE_0_0_MMCXWOL_1s_26s(verilog) instance CORETSEiolII[4:0] @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[0] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[0] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[1] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[1] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[2] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[2] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[3] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[3] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[4] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[4] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[5] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[5] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[6] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[6] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[7] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[7] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN362 : msgmii_core.v(427) | Removing sequential instance CORETSEiOiII[9] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) because it does not drive other instances. @A:BN291 : msgmii_core.v(427) | Boundary register CORETSEiOiII[9] (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_CORE_26s_0s_18s_0s(verilog)) is packed into a complex cell. To disable register packing, set syn_keep=1 on the net between the register and the complex cell. @N:MO231 : msgmii_cnvtxo.v(312) | Found counter in view:work.CORETSE_0_CORETSE_0_0_MSGMII_CNVTXO_26s(verilog) instance CORETSEol1II[6:0] @N:MO231 : msgmii_cnvrxi.v(539) | Found counter in view:work.CORETSE_0_CORETSE_0_0_MSGMII_CNVRXI_26s(verilog) instance CORETSEol1II[5:0] Encoding state machine CORETSEIo10_1[3:0] (in view: work.CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : perex_pcs.v(4925) | There are no possible illegal states for state machine CORETSEIo10_1[3:0] (in view: work.CORETSE_0_CORETSE_0_0_PEREX_PCS_0s_26s_1s(verilog)); safe FSM implementation is not required. @N:MO231 : msgmii_peanx_top.v(3508) | Found counter in view:work.CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s(verilog) instance CORETSEIiiII[20:0] @N:MF179 : msgmii_peanx_top.v(2473) | Found 15 by 15 bit equality operator ('==') CORETSEo1OlI (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s(verilog)) @N:MF179 : msgmii_peanx_top.v(2764) | Found 16 by 16 bit equality operator ('==') CORETSEoiOlI (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s(verilog)) @N:MF179 : msgmii_peanx_top.v(3094) | Found 15 by 15 bit equality operator ('==') un7_CORETSEoIIlI (in view: work.CORETSE_0_CORETSE_0_0_MSGMII_PEANX_TOP_1s_26s(verilog)) @N:MO231 : clock_gen.v(1011) | Found counter in view:work.CoreUARTapb_0_CoreUARTapb_0_0_Clock_gen_0s_0s(verilog) instance genblk1\.CUARTO0[12:0] Encoding state machine CUARTlI0l[5:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 Encoding state machine CUARTll0[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(871) | There are no possible illegal states for state machine CUARTll0[3:0] (in view: work.CoreUARTapb_0_CoreUARTapb_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. @W:BN132 : rx_async.v(754) | Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.CUARTlOlI.CUARTO01.CUARTIOll[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.CUARTlOlI.CUARTO01.CUARTIOll[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MF135 : miv_rv32_core_merged.v(16192) | RAM gen_buff_loop\[0\]\.buff_entry_error_resp_1[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s(verilog)) is 4 words by 1 bits. @N:MF135 : miv_rv32_core_merged.v(16192) | RAM gen_buff_loop\[0\]\.buff_entry_error_resp[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s(verilog)) is 4 words by 1 bits. @N:MF135 : miv_rv32_core_merged.v(16192) | RAM gen_buff_loop\[0\]\.buff_entry_data_resp_1[31:0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s(verilog)) is 4 words by 32 bits. @N:MF135 : miv_rv32_core_merged.v(16192) | RAM gen_buff_loop\[0\]\.buff_entry_data_resp[15:0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s(verilog)) is 4 words by 16 bits. @N:BN362 : miv_rv32_core_merged.v(16192) | Removing sequential instance gen_buff_loop\[0\]\.buff_entry_error_resp_1.gen_buff_loop\[0\]\.buff_entry_error_resp_1_ram3_[0] (in view: work.miv_rv32_ifu_iab_32s_2s_3s_2s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(16192) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : miv_rv32_core_merged.v(9110) | Removing sequential instance gen_trig_pipe_reg_ex_retr\.ex_retr_pipe_trigger_retr[1] (in view: work.miv_rv32_expipe_Z9(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @W:MO160 : miv_rv32_core_merged.v(8739) | Register bit de_ex_pipe_operand0_mux_sel_ex[1] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_core_merged.v(8739) | Register bit de_ex_pipe_operand1_mux_sel_ex[2] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_core_merged.v(8832) | Register bit de_ex_pipe_bcu_operand0_mux_sel_ex[1] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(8739) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MF179 : miv_rv32_core_merged.v(10369) | Found 32 by 32 bit equality operator ('==') un147_exu_alu_result (in view: work.miv_rv32_exu_1s_1s_1_0s_0s_0_0_0(verilog)) @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_1[31:0] with specified coding style. Inferring block RAM. @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem[31:0] with specified coding style. Inferring block RAM. @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem[31:0] with specified coding style. Inferring block RAM. @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_1[31:0] with specified coding style. Inferring block RAM. @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem_1[31:0] with specified coding style. Inferring block RAM. @W:FX107 : miv_rv32_core_merged.v(5963) | RAM gen_gpr\.u_gpr_array_0.mem_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:FX403 : miv_rv32_core_merged.v(5963) | Property "block_ram" or "no_rw_check" found for RAM gen_gpr\.u_gpr_array_0.mem[31:0] with specified coding style. Inferring block RAM. @W:FX107 : miv_rv32_core_merged.v(5963) | RAM gen_gpr\.u_gpr_array_0.mem[31:0] (in view: work.miv_rv32_gpr_ram_0s_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MF179 : miv_rv32_core_merged.v(4330) | Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[0\]\.un2_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z8(verilog)) @N:MF179 : miv_rv32_core_merged.v(4330) | Found 32 by 32 bit equality operator ('==') gen_tdata1_2\.gen_per_trig_tdata1\[1\]\.un5_trigger_iaddr_match (in view: work.miv_rv32_csr_privarch_Z8(verilog)) Encoding state machine gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[15:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)) original code -> new code 0000 -> 0000000000000001 0001 -> 0000000000000010 0010 -> 0000000000000100 0011 -> 0000000000001000 0100 -> 0000000000010000 0101 -> 0000000000100000 0110 -> 0000000001000000 0111 -> 0000000010000000 1000 -> 0000000100000000 1001 -> 0000001000000000 1010 -> 0000010000000000 1011 -> 0000100000000000 1100 -> 0001000000000000 1101 -> 0010000000000000 1110 -> 0100000000000000 1111 -> 1000000000000000 Encoding state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_opsrv_merged.v(12852) | There are no possible illegal states for state machine gen_shift_register_active_high\.gen_shift_register_active_low\.dtmcs_dmistat[3:0] (in view: work.miv_rv32_opsrv_dtm_jtag_1(verilog)); safe FSM implementation is not required. @N:MF135 : miv_rv32_opsrv_merged.v(12426) | RAM fifoMem[40:0] (in view: work.miv_rv32_opsrv_debug_fifo_1s_41s_1s_0s_2s(verilog)) is 2 words by 41 bits. @W:BN132 : miv_rv32_opsrv_merged.v(12464) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.rdAddrGrayReg_r[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.rdAddrReg_r[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_opsrv_merged.v(12443) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.wrAddrReg_w[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.wrAddrGrayReg_w[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:MF135 : miv_rv32_opsrv_merged.v(12426) | RAM fifoMem[33:0] (in view: work.miv_rv32_opsrv_debug_fifo_1s_34s_1s_0s_2s(verilog)) is 2 words by 34 bits. @W:BN132 : miv_rv32_opsrv_merged.v(12443) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.wrAddrReg_w[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.wrAddrGrayReg_w[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_opsrv_merged.v(12464) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.rdAddrGrayReg_r[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.rdAddrReg_r[1]. To keep the instance, apply constraint syn_preserve=1 on the instance. Encoding state machine debug_state[5:0] (in view: work.miv_rv32_opsrv_debug_du(verilog)) original code -> new code 000001 -> 000001 000010 -> 000010 000100 -> 000100 001000 -> 001000 010000 -> 010000 100000 -> 100000 Encoding state machine sba_state[3:0] (in view: work.miv_rv32_opsrv_debug_sba(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : miv_rv32_opsrv_merged.v(11826) | There are no possible illegal states for state machine sba_state[3:0] (in view: work.miv_rv32_opsrv_debug_sba(verilog)); safe FSM implementation is not required. @N:MO231 : miv_rv32_opsrv_merged.v(12180) | Found counter in view:work.miv_rv32_opsrv_debug_sba(verilog) instance counter[7:0] Encoding state machine gen_apb_byte_shim\.apb_st[5:0] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 011 -> 001000 100 -> 010000 101 -> 100000 @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[0] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[1] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[10] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[11] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[16] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[17] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[18] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[19] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[20] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[21] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[22] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[23] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[24] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[25] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[26] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[27] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[28] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[29] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[30] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(6229) | Removing sequential instance paddr[31] (in view: work.miv_rv32_opsrv_apb_mstr_32s_1s_1_0_1_2_3_4_5(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. Encoding state machine hipri_req_ptr[2:0] (in view: work.miv_rv32_rr_pri_arb_2s_1s_1s(verilog)) original code -> new code 01 -> 00 10 -> 01 11 -> 10 Encoding state machine cpu_d_wr_rd_state[2:0] (in view: work.miv_rv32_opsrv_tcm_Z13(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine hipri_req_ptr[6:0] (in view: work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) original code -> new code 001 -> 0000001 010 -> 0000010 011 -> 0000100 100 -> 0001000 101 -> 0010000 110 -> 0100000 111 -> 1000000 @W:MO160 : miv_rv32_opsrv_merged.v(14288) | Register bit hipri_req_ptr[6] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(14288) | Register bit hipri_req_ptr[4] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : miv_rv32_opsrv_merged.v(14288) | Register bit hipri_req_ptr[2] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : corecdr4_cntl_tip.v(117) | There are no possible illegal states for state machine tune_st[3:0] (in view: work.CORECDR4_CNTL_TIP_0_1_2_3_3s_0s_4s_1s_1s_1(verilog)); safe FSM implementation is not required. Encoding state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : coredelaycode_tip.v(59) | There are no possible illegal states for state machine state[3:0] (in view: work.COREDELAYCODE_TIP(verilog)); safe FSM implementation is not required. @N:MO231 : coredelaycode_tip.v(59) | Found counter in view:work.COREDELAYCODE_TIP(verilog) instance move_cnt[6:0] Starting factoring (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:15s; Memory used current: 248MB peak: 248MB) @N:BN362 : miv_rv32_core_merged.v(8209) | Removing sequential instance de_ex_pipe_i_access_parity_error_ex (in view: work.miv_rv32_expipe_Z9(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:30s; Memory used current: 347MB peak: 347MB) @W:BN132 : msgmii_clkrst.v(298) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEo00II because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEI00II. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : msgmii_clkrst.v(233) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEl00II because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEi00II. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_opsrv_merged.v(12426) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_opsrv_merged.v(12426) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[31] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[30] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9253) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoO0l (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(9154) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSElO0l (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_core_merged.v(8723) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[3] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_core_merged.v(9087) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.ex_retr_pipe_i_access_parity_error_retr (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(14288) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_apb_mstr\.u_apb_master_0.u_apb_mstr_req_arb.hipri_req_ptr[1] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(14288) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.u_TCM_req_arb.hipri_req_ptr[5] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : pemstat_sinc.v(240) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI\.CORETSEoOilI.CORETSEiIlo.CORETSEI11o.CORETSEIoOo (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : pemstat_sinc.v(240) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI\.CORETSEoOilI.CORETSEiIlo.CORETSEO11o.CORETSEIoOo (in view: work.top(verilog)) because it does not drive other instances. Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:47s; CPU Time elapsed 0h:00m:42s; Memory used current: 320MB peak: 386MB) @W:BN132 : petfn_top.v(10871) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[49] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[48]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : miv_rv32_core_merged.v(5485) | Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : pemstat_cntrl.v(2224) | Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[40] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[28]. To keep the instance, apply constraint syn_preserve=1 on the instance. Starting Early Timing Optimization (Real Time elapsed 0h:00m:54s; CPU Time elapsed 0h:00m:48s; Memory used current: 327MB peak: 386MB) Finished Early Timing Optimization (Real Time elapsed 0h:02m:07s; CPU Time elapsed 0h:01m:53s; Memory used current: 653MB peak: 653MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:02m:08s; CPU Time elapsed 0h:01m:55s; Memory used current: 654MB peak: 655MB) @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_2[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_4[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_1[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_6[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_3[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_4[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_1[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_2[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_6[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_3[2:0] (in view: work.top(verilog)) with 1 words by 3 bits. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2 (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEliol_2 (in view: work.top(verilog)) with 64 words by 1 bit. @N:MO106 : r10b8b.v(2472) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEliol_0[1:0] (in view: work.top(verilog)) with 64 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEO0ol_1 (in view: work.top(verilog)) with 46 words by 1 bit. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEO0ol_1 (in view: work.top(verilog)) with 46 words by 1 bit. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_5[2:0] (in view: work.top(verilog)) with 3 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_5[2:0] (in view: work.top(verilog)) with 3 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_0[2:0] (in view: work.top(verilog)) with 3 words by 3 bits. @N:MO106 : r10b8b.v(1950) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_0[2:0] (in view: work.top(verilog)) with 3 words by 3 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEilol_0[1:0] (in view: work.top(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEilol_0[1:0] (in view: work.top(verilog)) with 46 words by 2 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEllol_0[4:0] (in view: work.top(verilog)) with 46 words by 5 bits. @N:MO106 : r10b8b.v(268) | Found ROM CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEllol_0[4:0] (in view: work.top(verilog)) with 46 words by 5 bits. @W:BN132 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_4_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_3_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_4_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_3_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_2_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_1_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_2_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_1_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1923 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1924 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1925 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1926 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1927 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1928 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1929 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance G_1930 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEllol_0_dreg[4:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEllol_0_dreg[4:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEilol_0_dreg[1:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEilol_0_dreg[1:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_0_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_0_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_5_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_5_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEO0ol_1_dreg (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(268) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEO0ol_1_dreg (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(2472) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEliol_0_dreg[1:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(2472) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEliol_2_dreg (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(2472) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2_dreg (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_3_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_6_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_1_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_3_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_6_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_1_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : r10b8b.v(1950) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_dreg[2:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : miv_rv32_opsrv_merged.v(12732) | Removing sequential instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[0] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(3696) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEOl0l (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(6347) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEil0l (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10067) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEl00l (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10211) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEOl1 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[23] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[22] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[21] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : petfn_top.v(10871) | Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[50] (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : spi_chanctrl.v(286) | Removing sequential instance CORESPI_0_0.CORESPI_0_0.USPI.UCC.spi_clk_next (in view: work.top(verilog)) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:02m:17s; CPU Time elapsed 0h:02m:03s; Memory used current: 654MB peak: 656MB) Finished technology mapping (Real Time elapsed 0h:02m:30s; CPU Time elapsed 0h:02m:15s; Memory used current: 729MB peak: 729MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:02m:17s -32.17ns 16070 / 6606 2 0h:02m:18s -32.17ns 14300 / 6606 3 0h:02m:19s -32.17ns 14302 / 6606 4 0h:02m:20s -32.17ns 14302 / 6606 5 0h:02m:26s -32.17ns 14304 / 6606 6 0h:02m:26s -32.17ns 14306 / 6606 7 0h:02m:27s -32.17ns 14307 / 6606 8 0h:02m:28s -32.17ns 14310 / 6606 9 0h:02m:28s -32.17ns 14313 / 6606 10 0h:02m:30s -32.17ns 14324 / 6606 11 0h:02m:30s -32.17ns 14327 / 6606 12 0h:02m:31s -32.17ns 14328 / 6606 13 0h:02m:32s -32.17ns 14332 / 6606 14 0h:02m:33s -32.17ns 14336 / 6606 @N:FP130 : | Promoting Net AND2_2_Y_arst on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3589 @N:FP130 : | Promoting Net PF_IOD_CDR_CCC_C0_0_TX_CLK_G on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3590 @N:FP130 : | Promoting Net dff_arst on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3591 @N:FP130 : | Promoting Net PHY_MDC_c on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3592 @N:FP130 : | Promoting Net core_jatg_debug_0_0.core_jatg_debug_0_0.iUDRCK on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3593 @N:FP130 : | Promoting Net PF_IOD_CDR_C0_0.PF_LANECTRL_0_CDR_CLK on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3594 @N:FP130 : | Promoting Net PF_IOD_CDR_CCC_C0_0_CDR_CLOCKS_HS_IO_CLK_0 on CLKINT CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEi0ii.un3_CORETSEollOI_0_I_1_3595 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:02m:56s; CPU Time elapsed 0h:02m:37s; Memory used current: 742MB peak: 742MB) Finished restoring hierarchy (Real Time elapsed 0h:02m:57s; CPU Time elapsed 0h:02m:39s; Memory used current: 746MB peak: 747MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 4 non-gated/non-generated clock tree(s) driving 1179 clock pin(s) of sequential element(s) 10 gated/generated clock tree(s) driving 5546 clock pin(s) of sequential element(s) 0 instances converted, 5546 sequential instances remain driven by gated/generated clocks ============================================================================================ Non-Gated/Non-Generated Clocks ============================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0011 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG 17 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.UTDODRV ClockId0012 INBUF_DIFF_0 INBUF_DIFF 1 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0 ClockId0013 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL clock definition on LANECTRL 1160 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL ClockId0014 REF_CLK_0 clock definition on port 1 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0 ========================================================================================================================================================================================================================= ======================================================================================================================================================== Gated/Generated Clocks ========================================================================================================================================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEOII1.CORETSEI110 SLE 124 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEI0o0 No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL LANECTRL 2 PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0 No gated clock conversion method for cell cell:work.IOD ClockId0003 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_3 HS_IO_CLK 2 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL No gated clock conversion method for cell cell:work.LANECTRL ClockId0004 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_15 HS_IO_CLK 1 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL No gated clock conversion method for cell cell:work.LANECTRL ClockId0005 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_11 HS_IO_CLK 1 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL No gated clock conversion method for cell cell:work.LANECTRL ClockId0006 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.hs_io_clk_7 HS_IO_CLK 1 PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL No gated clock conversion method for cell cell:work.LANECTRL ClockId0007 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD ICB_CLKDIV 1135 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEo1ii.CORETSEliii No gated clock conversion method for cell cell:ACG4.SLE ClockId0008 PF_CCC_0_0.PF_CCC_0_0.pll_inst_0 PLL 4072 CoreUARTapb_0_inst_0.CoreUARTapb_0_0.CUARTO1OI[1] No gated clock conversion method for cell cell:ACG4.SLE ClockId0009 PF_IOD_CDR_CCC_C0_0.PF_CCC_0.pll_inst_0 PLL 1 PF_IOD_CDR_CCC_C0_0.PF_CLK_DIV_0.I_CD No gated clock conversion method for cell cell:work.ICB_CLKDIV ClockId0010 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.un1_DUT_TCK_0 CFG4 207 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.debug_req_fifo.genblk2\.wrAddrReg_w[0] No gated clock conversion method for cell cell:ACG4.SLE ========================================================================================================================================================================================================================================================================================================================================= ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:02m:59s; CPU Time elapsed 0h:02m:40s; Memory used current: 625MB peak: 747MB) Writing Analyst data base F:\DG0799_final\Libero_Project\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:03m:02s; CPU Time elapsed 0h:02m:44s; Memory used current: 614MB peak: 747MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : synthesis.fdc(47) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(48) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(49) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(50) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(51) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(52) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(53) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : synthesis.fdc(54) | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. @W:BW150 : | Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:03m:09s; CPU Time elapsed 0h:02m:50s; Memory used current: 616MB peak: 747MB) Start final timing analysis (Real Time elapsed 0h:03m:11s; CPU Time elapsed 0h:02m:52s; Memory used current: 597MB peak: 747MB) @W:MT246 : pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v(40) | Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock REF_CLK_0 with period 20.00ns @N:MT615 : | Found clock PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R with period 8.00ns @N:MT615 : | Found clock REFCLK_P with period 8.00ns @N:MT615 : | Found clock TCK with period 100.00ns @N:MT615 : | Found clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 with period 12.50ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 with period 1.60ns @N:MT615 : | Found clock PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV with period 8.00ns @N:MT615 : | Found clock PHY_MDC_CLOCK with period 350.00ns @W:MT420 : | Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK. @W:MT420 : | Found inferred clock COREJTAGDEBUG_Z1|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net core_jatg_debug_0_0.core_jatg_debug_0_0.iUDRCK_0. ##### START OF TIMING REPORT #####[ # Timing report written on Thu Feb 25 12:44:48 2021 # Top view: top Requested Frequency: 2.9 MHz Wire load mode: top Paths requested: 5 Constraint File(s): F:\DG0799_final\Libero_Project\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. Performance Summary ******************* Worst slack in design: -32.246 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- COREJTAGDEBUG_Z1|iUDRCK_inferred_clock 100.0 MHz 13.4 MHz 10.000 74.491 -32.246 inferred Inferred_clkgroup_2 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 80.0 MHz 58.9 MHz 12.500 16.984 -4.484 generated (from REF_CLK_0) (multiple) PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 125.0 MHz 155.3 MHz 8.000 6.437 1.563 declared SGMII_CDR_0_0_CLK_OUT_GRP PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep 100.0 MHz NA 10.000 NA NA inferred Inferred_clkgroup_0 PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT0_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT1_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT2_GRP PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 625.0 MHz NA 1.600 NA NA generated (from REFCLK_P) NWC_PLL_OUT3_GRP PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 125.0 MHz 256.0 MHz 8.000 3.905 4.095 generated (from REFCLK_P) Y_DIV_GRP PHY_MDC_CLOCK 2.9 MHz NA 350.000 NA NA generated (from REF_CLK_0) default_clkgroup REFCLK_P 125.0 MHz NA 8.000 NA NA declared default_clkgroup REF_CLK_0 50.0 MHz NA 20.000 NA NA declared default_clkgroup TCK 10.0 MHz NA 100.000 NA NA declared JTAG_Async_2 System 100.0 MHz 226.1 MHz 10.000 4.424 5.576 system system_clkgroup ===================================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 10.000 5.576 | No paths - | No paths - | No paths - System PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 3.350 | No paths - | No paths - | No paths - System PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 9.470 | No paths - | No paths - | No paths - System PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 4.441 | No paths - | No paths - | No paths - System COREJTAGDEBUG_Z1|iUDRCK_inferred_clock | 10.000 -27.793 | No paths - | 10.000 7.683 | No paths - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | 8.000 1.563 | 8.000 3.297 | 3.200 1.907 | 4.800 3.427 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 System | 12.500 10.396 | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | 12.500 -4.484 | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 PHY_MDC_CLOCK | Diff grp - | No paths - | No paths - | No paths - PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 COREJTAGDEBUG_Z1|iUDRCK_inferred_clock | Diff grp - | No paths - | Diff grp - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV System | 8.000 6.348 | No paths - | No paths - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R | Diff grp - | No paths - | Diff grp - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV | 8.000 4.095 | No paths - | No paths - | No paths - PHY_MDC_CLOCK PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | No paths - COREJTAGDEBUG_Z1|iUDRCK_inferred_clock System | 10.000 8.633 | No paths - | No paths - | No paths - COREJTAGDEBUG_Z1|iUDRCK_inferred_clock PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 | Diff grp - | No paths - | No paths - | Diff grp - COREJTAGDEBUG_Z1|iUDRCK_inferred_clock COREJTAGDEBUG_Z1|iUDRCK_inferred_clock | 10.000 5.170 | 10.000 5.579 | 5.000 1.336 | 5.000 -32.246 ================================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------- PHY_MDIO PHY_MDC_CLOCK (rising) 20.000 NA NA NA RESET_N REF_CLK_0 (rising) 20.000 NA NA NA ===================================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- PHY_MDIO PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 (rising) 10.000(PHY_MDC_CLOCK rising) 4.556 NA NA =============================================================================================================================== ==================================== Detailed Report for Clock: COREJTAGDEBUG_Z1|iUDRCK_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q tmsenb 0.218 -32.246 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.endofshift COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q endofshift 0.218 -32.148 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[8] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q currTapState[8] 0.218 1.336 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.state[3] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q state[3] 0.218 1.707 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.state[4] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q state[4] 0.201 1.755 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[4] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q irReg[4] 0.218 2.054 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.state[0] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q state[0] 0.218 2.079 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[0] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q irReg[0] 0.218 2.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.ir_and_Instruction_register\.gen_ir_and_Instruction_register_active_low\.irReg[3] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q irReg[3] 0.201 2.100 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_shift_register_active_high\.gen_shift_register_active_low\.shiftDMI[1] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE Q shiftDMI[1] 0.218 2.172 ========================================================================================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D currTapState_ns[1] 5.000 -32.246 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D N_95_i 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_0 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_5 5.000 -32.181 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[4] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_4 5.000 -32.166 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_6 5.000 -32.166 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[3] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D currTapState_ns[3] 5.000 -32.121 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D N_102_i 5.000 -32.121 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[10] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D currTapState_ns[10] 5.000 -32.121 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] COREJTAGDEBUG_Z1|iUDRCK_inferred_clock SLE D gen_N_3_mux_0_2 5.000 -32.121 ================================================================================================================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.246 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -32.246 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] / D The start point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[1] CFG4 D In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[1] CFG4 Y Out 0.212 37.128 f - currTapState_ns[1] Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] SLE D In - 37.246 f - ====================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.246 is 4.070(10.9%) logic and 33.176(89.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.181 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.181 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D The start point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 C In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.148 37.063 r - N_95_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.181 r - ====================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.181 is 4.006(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.181 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.181 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] / D The start point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[12] CFG3 C In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[12] CFG3 Y Out 0.148 37.063 r - gen_N_3_mux_0_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] SLE D In - 37.181 r - ======================================================================================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 37.181 is 4.006(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.181 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.181 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] / D The start point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[5] CFG3 C In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[5] CFG3 Y Out 0.148 37.063 r - gen_N_3_mux_0_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] SLE D In - 37.181 r - ====================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.181 is 4.006(10.8%) logic and 33.176(89.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 37.166 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -32.166 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb / Q Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] / D The start point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.tmsenb SLE Q Out 0.218 0.218 r - tmsenb Net - - 0.118 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 C In - 0.336 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.148 0.484 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.432 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 1.535 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 2.483 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 2.586 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 3.534 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 3.636 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 4.584 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 4.687 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 5.635 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 5.738 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 6.686 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 6.788 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 7.736 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 7.839 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 8.787 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 8.890 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 9.838 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 9.940 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 10.888 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 10.991 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 11.939 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.042 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 12.990 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.092 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.040 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.143 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.091 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.194 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.142 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.245 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.193 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.295 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.243 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.346 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.294 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.397 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.345 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.447 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.395 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 21.498 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.446 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 22.549 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 23.497 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 23.599 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 24.547 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 24.650 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 25.598 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 25.701 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 26.649 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 26.752 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 27.700 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 27.802 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 28.750 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 28.853 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 29.801 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 29.904 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 30.852 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 30.954 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 31.902 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.005 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 32.953 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.056 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.004 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.106 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.054 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.157 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.105 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.208 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[11] CFG4 C In - 36.916 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[11] CFG4 Y Out 0.132 37.048 f - gen_N_3_mux_0_6 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] SLE D In - 37.166 f - ======================================================================================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 37.166 is 3.990(10.7%) logic and 33.176(89.3%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R31C0_B_DOUT[0] 2.241 -4.484 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R31C0_B_DOUT[1] 2.241 -4.465 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R27C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R27C0_B_DOUT[0] 2.241 -4.453 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R30C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R30C0_B_DOUT[0] 2.241 -4.453 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R27C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R27C0_B_DOUT[1] 2.241 -4.433 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R30C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R30C0_B_DOUT[1] 2.241 -4.433 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R26C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R26C0_B_DOUT[0] 2.241 -4.422 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[0] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[0] 2.241 -4.418 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R26C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R26C0_B_DOUT[1] 2.241 -4.402 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R15C0 PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 RAM1K20 B_DOUT[1] miv_rv32_ram_singleport_lp_R15C0_B_DOUT[1] 2.241 -4.398 =============================================================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE D N_1273_i 12.500 -4.484 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[1] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE D de_ex_pipe_alu_op_sel_ex_1[1] 12.500 -4.262 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[4] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE D de_ex_pipe_alu_op_sel_ex_1[4] 12.500 -4.161 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_alu_op_sel_ex[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE D de_ex_pipe_alu_op_sel_ex_1[0] 12.500 -4.114 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[0] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[1] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[2] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[3] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[4] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_curr_instr_enc_ex[5] PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 SLE EN instr_accepted_ex_0_a2_i_1_0_RNIVN46S1 12.373 -4.096 ======================================================================================================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 12.500 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.500 - Propagation time: 16.984 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -4.484 Number of logic level(s): 20 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 / B_DOUT[0] Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex / D The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin B_CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 RAM1K20 B_DOUT[0] Out 2.241 2.241 r - miv_rv32_ram_singleport_lp_R31C0_B_DOUT[0] Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 D In - 3.189 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 Y Out 0.282 3.471 r - OR4_248_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 D In - 4.419 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 Y Out 0.282 4.701 r - OR4_1019_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 B In - 5.649 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 Y Out 0.169 5.819 r - OR4_1080_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 A In - 6.767 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 Y Out 0.103 6.869 r - tcm0_d_resp_rd_data_net[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 C In - 7.416 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 Y Out 0.148 7.564 r - cpu_i_resp_rd_data_net[0] Net - - 0.609 - 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 D In - 8.173 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 Y Out 0.168 8.341 r - emi_resp_head_uncompressed_full Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 C In - 8.920 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 Y Out 0.132 9.052 f - N_723 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 C In - 9.760 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 Y Out 0.145 9.905 f - m312_i_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 D In - 10.023 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 Y Out 0.192 10.215 f - N_94 Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 D In - 11.107 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 Y Out 0.232 11.339 r - N_310_i Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 B In - 11.886 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 Y Out 0.088 11.973 f - rv32i_dec_mnemonic3470_0_a2_1_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 D In - 12.091 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 Y Out 0.232 12.323 r - rv32i_dec_mnemonic3470 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 D In - 12.870 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 Y Out 0.212 13.082 f - un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 B In - 13.200 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 Y Out 0.077 13.277 f - N_298_i Net - - 0.697 - 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 A In - 13.974 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 Y Out 0.047 14.021 r - case_dec_bcu_op_sel_0_sqmuxa Net - - 0.962 - 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 C In - 14.984 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 Y Out 0.132 15.116 f - N_16_1 Net - - 0.781 - 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 C In - 15.897 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 Y Out 0.145 16.042 f - g2_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 D In - 16.160 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 Y Out 0.192 16.352 f - N_732_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 C In - 16.470 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 Y Out 0.130 16.600 r - g0_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 C In - 16.718 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 Y Out 0.148 16.866 r - N_1273_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex SLE D In - 16.984 r - ================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 16.984 is 5.497(32.4%) logic and 11.487(67.6%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 12.500 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.500 - Propagation time: 16.967 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -4.467 Number of logic level(s): 20 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 / B_DOUT[0] Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex / D The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin B_CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 RAM1K20 B_DOUT[0] Out 2.241 2.241 r - miv_rv32_ram_singleport_lp_R31C0_B_DOUT[0] Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 D In - 3.189 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 Y Out 0.282 3.471 r - OR4_248_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 D In - 4.419 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 Y Out 0.282 4.701 r - OR4_1019_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 B In - 5.649 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 Y Out 0.169 5.819 r - OR4_1080_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 A In - 6.767 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 Y Out 0.103 6.869 r - tcm0_d_resp_rd_data_net[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 C In - 7.416 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 Y Out 0.148 7.564 r - cpu_i_resp_rd_data_net[0] Net - - 0.609 - 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 D In - 8.173 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 Y Out 0.168 8.341 r - emi_resp_head_uncompressed_full Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 C In - 8.920 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 Y Out 0.132 9.052 f - N_723 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 C In - 9.760 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 Y Out 0.145 9.905 f - m312_i_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 D In - 10.023 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 Y Out 0.192 10.215 f - N_94 Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 D In - 11.107 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 Y Out 0.232 11.339 r - N_310_i Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 B In - 11.886 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 Y Out 0.088 11.973 f - rv32i_dec_mnemonic3470_0_a2_1_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 D In - 12.091 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 Y Out 0.232 12.323 r - rv32i_dec_mnemonic3470 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 D In - 12.870 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 Y Out 0.212 13.082 f - un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 B In - 13.200 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 Y Out 0.077 13.277 f - N_298_i Net - - 0.697 - 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 A In - 13.974 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 Y Out 0.047 14.021 r - case_dec_bcu_op_sel_0_sqmuxa Net - - 0.962 - 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 C In - 14.984 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 Y Out 0.132 15.116 f - N_16_1 Net - - 0.781 - 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 CFG4 D In - 15.897 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 CFG4 Y Out 0.232 16.128 r - de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2 CFG4 D In - 16.247 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2 CFG4 Y Out 0.168 16.414 r - N_776 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 A In - 16.532 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 Y Out 0.051 16.583 r - g0_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 C In - 16.701 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 Y Out 0.148 16.849 r - N_1273_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex SLE D In - 16.967 r - ================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 16.967 is 5.480(32.3%) logic and 11.487(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 12.500 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.500 - Propagation time: 16.965 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -4.465 Number of logic level(s): 20 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 / B_DOUT[1] Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex / D The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin B_CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 RAM1K20 B_DOUT[1] Out 2.241 2.241 r - miv_rv32_ram_singleport_lp_R31C0_B_DOUT[1] Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_230 OR4 D In - 3.189 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_230 OR4 Y Out 0.282 3.471 r - OR4_230_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_16 OR4 D In - 4.419 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_16 OR4 Y Out 0.282 4.701 r - OR4_16_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1061 OR4 B In - 5.649 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1061 OR4 Y Out 0.169 5.819 r - OR4_1061_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[1\] OR4 A In - 6.767 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[1\] OR4 Y Out 0.103 6.869 r - tcm0_d_resp_rd_data_net[1] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[1] CFG4 C In - 7.416 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[1] CFG4 Y Out 0.148 7.564 r - cpu_i_resp_rd_data_net[1] Net - - 0.609 - 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 C In - 8.173 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 Y Out 0.148 8.321 r - emi_resp_head_uncompressed_full Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 C In - 8.900 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3_0[2] CFG4 Y Out 0.132 9.032 f - N_723 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 C In - 9.740 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 Y Out 0.145 9.886 f - m312_i_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 D In - 10.004 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 Y Out 0.192 10.195 f - N_94 Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 D In - 11.087 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 Y Out 0.232 11.319 r - N_310_i Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 B In - 11.866 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 Y Out 0.088 11.954 f - rv32i_dec_mnemonic3470_0_a2_1_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 D In - 12.072 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 Y Out 0.232 12.303 r - rv32i_dec_mnemonic3470 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 D In - 12.850 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 Y Out 0.212 13.062 f - un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 B In - 13.180 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 Y Out 0.077 13.258 f - N_298_i Net - - 0.697 - 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 A In - 13.955 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 Y Out 0.047 14.002 r - case_dec_bcu_op_sel_0_sqmuxa Net - - 0.962 - 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 C In - 14.964 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 Y Out 0.132 15.096 f - N_16_1 Net - - 0.781 - 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 C In - 15.877 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 Y Out 0.145 16.023 f - g2_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 D In - 16.140 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 Y Out 0.192 16.332 f - N_732_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 C In - 16.450 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 Y Out 0.130 16.581 r - g0_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 C In - 16.699 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 Y Out 0.148 16.846 r - N_1273_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex SLE D In - 16.965 r - ================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 16.965 is 5.478(32.3%) logic and 11.487(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 12.500 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.500 - Propagation time: 16.959 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -4.459 Number of logic level(s): 20 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 / B_DOUT[0] Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex / D The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin B_CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 RAM1K20 B_DOUT[0] Out 2.241 2.241 r - miv_rv32_ram_singleport_lp_R31C0_B_DOUT[0] Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 D In - 3.189 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 Y Out 0.282 3.471 r - OR4_248_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 D In - 4.419 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 Y Out 0.282 4.701 r - OR4_1019_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 B In - 5.649 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 Y Out 0.169 5.819 r - OR4_1080_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 A In - 6.767 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 Y Out 0.103 6.869 r - tcm0_d_resp_rd_data_net[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 C In - 7.416 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 Y Out 0.148 7.564 r - cpu_i_resp_rd_data_net[0] Net - - 0.609 - 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 D In - 8.173 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 Y Out 0.168 8.341 r - emi_resp_head_uncompressed_full Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3[2] CFG4 C In - 8.920 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3[2] CFG4 Y Out 0.148 9.068 r - N_725 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 D In - 9.776 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 Y Out 0.168 9.943 r - m312_i_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 D In - 10.061 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 Y Out 0.168 10.229 r - N_94 Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 D In - 11.121 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 Y Out 0.212 11.333 f - N_310_i Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 B In - 11.880 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 Y Out 0.084 11.964 r - rv32i_dec_mnemonic3470_0_a2_1_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 D In - 12.082 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 Y Out 0.212 12.294 f - rv32i_dec_mnemonic3470 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 D In - 12.841 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 Y Out 0.232 13.072 r - un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 B In - 13.190 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 Y Out 0.083 13.273 r - N_298_i Net - - 0.697 - 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 A In - 13.970 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 Y Out 0.046 14.016 f - case_dec_bcu_op_sel_0_sqmuxa Net - - 0.962 - 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 C In - 14.979 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 Y Out 0.130 15.109 r - N_16_1 Net - - 0.781 - 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 CFG4 D In - 15.890 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 CFG4 Y Out 0.212 16.102 f - de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_o2_1_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2 CFG4 D In - 16.220 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2 CFG4 Y Out 0.192 16.412 f - N_776 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 A In - 16.530 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 Y Out 0.048 16.577 f - g0_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 C In - 16.695 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 Y Out 0.145 16.841 f - N_1273_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex SLE D In - 16.959 f - ================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 16.959 is 5.472(32.3%) logic and 11.487(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 12.500 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 12.500 - Propagation time: 16.955 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -4.455 Number of logic level(s): 20 Starting point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 / B_DOUT[0] Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex / D The start point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin B_CLK The end point is clocked by PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=6.250 period=12.500) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.miv_rv32_ram_singleport_lp_R31C0 RAM1K20 B_DOUT[0] Out 2.241 2.241 r - miv_rv32_ram_singleport_lp_R31C0_B_DOUT[0] Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 D In - 3.189 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_248 OR4 Y Out 0.282 3.471 r - OR4_248_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 D In - 4.419 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1019 OR4 Y Out 0.282 4.701 r - OR4_1019_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 B In - 5.649 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.OR4_1080 OR4 Y Out 0.169 5.819 r - OR4_1080_Y Net - - 0.948 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 A In - 6.767 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_tcm0\.u_opsrv_TCM_0.tcm_ram_macro\.u_ram_0.\\OR4_R_DATA\[0\] OR4 Y Out 0.103 6.869 r - tcm0_d_resp_rd_data_net[0] Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 C In - 7.416 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.cpu_i_resp_rd_data[0] CFG4 Y Out 0.148 7.564 r - cpu_i_resp_rd_data_net[0] Net - - 0.609 - 7 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 D In - 8.173 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNI6DB52[2] CFG4 Y Out 0.168 8.341 r - emi_resp_head_uncompressed_full Net - - 0.579 - 5 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3[2] CFG4 C In - 8.920 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIKE9A3[2] CFG4 Y Out 0.148 9.068 r - N_725 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 D In - 9.776 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[2\]\.buff_entry_hword_high_only_req_RNIJPLC7[2] CFG4 Y Out 0.168 9.943 r - m312_i_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 D In - 10.061 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop\[0\]\.buff_entry_data_resp.gen_buff_loop\[0\]\.buff_entry_data_resp_ram1__RNIAOQ721[13] CFG4 Y Out 0.168 10.229 r - N_94 Net - - 0.892 - 42 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 D In - 11.121 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.rv32i_dec_branch_cond_i_m_i_o2_0_i_a2[0] CFG4 Y Out 0.212 11.333 f - N_310_i Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 B In - 11.880 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2_1_0 CFG3 Y Out 0.084 11.964 r - rv32i_dec_mnemonic3470_0_a2_1_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 D In - 12.082 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3470_0_a2 CFG4 Y Out 0.212 12.294 f - rv32i_dec_mnemonic3470 Net - - 0.547 - 3 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 D In - 12.841 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 CFG4 Y Out 0.232 13.072 r - un1_rv32i_dec_mnemonic3474_1_i_7_0_4_RNIKDFC1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 B In - 13.190 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.gen_decode_rv32i\.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8 CFG4 Y Out 0.083 13.273 r - N_298_i Net - - 0.697 - 14 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 A In - 13.970 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.case_dec_bcu_op_sel_0_sqmuxa_0_a2_0_a2 CFG2 Y Out 0.046 14.016 f - case_dec_bcu_op_sel_0_sqmuxa Net - - 0.962 - 63 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 C In - 14.979 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1[1] CFG4 Y Out 0.130 15.109 r - N_16_1 Net - - 0.781 - 23 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 C In - 15.890 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIRHESM[1] CFG3 Y Out 0.148 16.038 r - g2_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 D In - 16.156 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.sw_csr_wr_op_i_1_RNIPJI0LC[1] CFG4 Y Out 0.168 16.324 r - N_732_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 C In - 16.442 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_16_i_a2_RNI3F33LC CFG3 Y Out 0.132 16.574 f - g0_1 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 C In - 16.692 f - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_idecode_0.de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J CFG4 Y Out 0.145 16.837 f - N_1273_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_illegal_instr_ex SLE D In - 16.955 f - ================================================================================================================================================================================================================================================================ Total path delay (propagation time + setup) of 16.955 is 5.468(32.3%) logic and 11.487(67.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEoio0.CORETSElili PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSElili 0.218 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[9] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[9] 0.201 1.623 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[11] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[11] 0.218 1.682 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[10] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[10] 0.218 1.690 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[12] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[12] 0.218 1.700 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[8] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[8] 0.218 1.723 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[13] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[13] 0.218 1.744 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[14] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[14] 0.218 1.774 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[2] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[2] 0.218 1.777 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[15] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE Q CORETSEi0io[15] 0.218 1.785 =============================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEl0io[5] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[26] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_1_iv_i[2] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[27] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_1_iv_i[3] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[28] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_0_iv_i[4] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[29] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_0_iv_i[5] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[31] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_0_iv_i[7] 8.000 1.563 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEi0io[30] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEOiol_1_iv_i[6] 8.000 1.609 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEllI[4] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEIlI[4] 8.000 1.623 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEllI[6] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEIlI[6] 8.000 1.623 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEllI[7] PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R SLE D CORETSEIlI[7] 8.000 1.623 ====================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.000 - Propagation time: 6.437 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 1.563 Number of logic level(s): 10 Starting point: CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEoio0.CORETSElili / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] / D The start point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R [rising] (rise=0.000 fall=3.200 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEoio0.CORETSElili SLE Q Out 0.218 0.218 r - CORETSElili Net - - 0.939 - 55 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEoio0.CORETSEooo0[5] CFG3 C In - 1.158 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEoio0.CORETSEooo0[5] CFG3 Y Out 0.148 1.306 r - CORETSEooo0[5] Net - - 0.888 - 41 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2.m9 CFG4 D In - 2.193 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2.m9 CFG4 Y Out 0.232 2.425 r - m9_3 Net - - 0.563 - 4 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2.i4_mux_i CFG3 A In - 2.988 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEIiol_2.i4_mux_i CFG3 Y Out 0.051 3.039 f - CORETSEIiol Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 D In - 3.157 f - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0_1[1] CFG4 Y Out 0.192 3.349 f - CORETSEiOol_0_1[1] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 D In - 3.467 f - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEiOol_0[1] CFG4 Y Out 0.192 3.658 f - CORETSEiOol[1] Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 C In - 4.267 f - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.un12_CORETSEo1ol CFG4 Y Out 0.148 4.415 f - un12_CORETSEo1ol Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol_8 CFG4 B In - 4.533 f - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol_8 CFG4 Y Out 0.084 4.617 r - CORETSEo1ol_8 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 B In - 4.735 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEo1ol CFG4 Y Out 0.083 4.818 r - CORETSEo1ol Net - - 0.674 - 12 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51 CFG3 B In - 5.492 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEoool51 CFG3 Y Out 0.088 5.580 f - CORETSEoool51 Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEIIol_f0[2] CFG3 C In - 6.189 f - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEIIol_f0[2] CFG3 Y Out 0.130 6.319 r - CORETSEl0io[5] Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEIIol[11] SLE D In - 6.437 r - =============================================================================================================================================================================================== Total path delay (propagation time + setup) of 6.437 is 1.565(24.3%) logic and 4.873(75.7%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEo01OI[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEo01OI[0] 0.218 4.095 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEo01OI[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEo01OI[1] 0.218 4.266 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSElio0.CORETSEO00I[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEO00I[0] 0.218 4.289 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSElio0.CORETSEO00I[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEO00I[2] 0.218 4.361 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSElio0.CORETSEO00I[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEO00I[1] 0.218 4.364 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSElio0.CORETSElI0I[2] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSElI0I[2] 0.218 4.394 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSElio0.CORETSElI0I[3] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSElI0I[3] 0.218 4.395 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEIOIl[12] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSEIOIl[12] 0.201 4.423 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSElIiII.CORETSElIoII[0] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSElIoII[0] 0.218 4.459 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSElIiII.CORETSElIoII[1] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE Q CORETSElIoII[1] 0.218 4.494 ======================================================================================================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEoI1OI PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSElI1OI 8.000 4.095 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEO01OI[13] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEO01OI_4[13] 8.000 4.150 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEi01OI[13] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[13] 8.000 4.161 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEil1OI[13] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[13] 8.000 4.161 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEi01OI[12] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[12] 8.000 4.169 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEil1OI[12] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[12] 8.000 4.169 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEi01OI[11] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[11] 8.000 4.177 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEil1OI[11] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[11] 8.000 4.177 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEi01OI[10] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[10] 8.000 4.185 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEil1OI[10] PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV SLE D CORETSEilIOI[10] 8.000 4.185 =============================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 8.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 8.000 - Propagation time: 3.905 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 4.095 Number of logic level(s): 15 Starting point: CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEo01OI[0] / Q Ending point: CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEoI1OI / D The start point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK The end point is clocked by PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV [rising] (rise=0.000 fall=4.800 period=8.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------- CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEo01OI[0] SLE Q Out 0.218 0.218 r - CORETSEo01OI[0] Net - - 0.738 - 18 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElo1OI_1 CFG4 D In - 0.956 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElo1OI_1 CFG4 Y Out 0.232 1.188 r - CORETSElo1OI_1 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElo1OI CFG4 B In - 1.306 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElo1OI CFG4 Y Out 0.083 1.389 r - CORETSElo1OI Net - - 0.609 - 7 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un2_CORETSEilIOI_i_0 CFG4 B In - 1.998 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un2_CORETSEilIOI_i_0 CFG4 Y Out 0.083 2.081 r - N_51_i Net - - 0.869 - 37 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_0 ARI1 D In - 2.950 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_0 ARI1 FCO Out 0.492 3.442 r - un7_CORETSElI1OI_cry_0 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_1 ARI1 FCI In - 3.442 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_1 ARI1 FCO Out 0.008 3.450 r - un7_CORETSElI1OI_cry_1 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_2 ARI1 FCI In - 3.450 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_2 ARI1 FCO Out 0.008 3.458 r - un7_CORETSElI1OI_cry_2 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_3 ARI1 FCI In - 3.458 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_3 ARI1 FCO Out 0.008 3.466 r - un7_CORETSElI1OI_cry_3 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_4 ARI1 FCI In - 3.466 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_4 ARI1 FCO Out 0.008 3.474 r - un7_CORETSElI1OI_cry_4 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_5 ARI1 FCI In - 3.474 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_5 ARI1 FCO Out 0.008 3.482 r - un7_CORETSElI1OI_cry_5 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_6 ARI1 FCI In - 3.482 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_6 ARI1 FCO Out 0.008 3.490 r - un7_CORETSElI1OI_cry_6 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_7 ARI1 FCI In - 3.490 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_7 ARI1 FCO Out 0.008 3.498 r - un7_CORETSElI1OI_cry_7 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_8 ARI1 FCI In - 3.498 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_8 ARI1 FCO Out 0.008 3.506 r - un7_CORETSElI1OI_cry_8 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_9 ARI1 FCI In - 3.506 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_9 ARI1 FCO Out 0.008 3.514 r - un7_CORETSElI1OI_cry_9 Net - - 0.000 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_10 ARI1 FCI In - 3.514 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.un7_CORETSElI1OI_cry_10 ARI1 FCO Out 0.008 3.522 r - un7_CORETSElI1OI_cry_10 Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElI1OI CFG3 C In - 3.640 r - CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSElI1OI CFG3 Y Out 0.148 3.788 r - CORETSElI1OI Net - - 0.118 - 1 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEooolI.CORETSEl0ii.CORETSEoI1OI SLE D In - 3.905 r - ====================================================================================================================================================================== Total path delay (propagation time + setup) of 3.905 is 1.336(34.2%) logic and 2.570(65.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst System UJTAG UTDI UTDIInt 0.000 -27.793 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEloo0 System SLE Q CORETSEloo0 0.218 3.350 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEllII System SLE Q CORETSEllII 0.218 4.441 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEilo0 System SLE Q CORETSEOi10 0.218 4.819 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEiIII System SLE Q CORETSEiIII 0.218 4.967 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEio10 System SLE Q CORETSEio10 0.218 4.994 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEO0II[0] System SLE Q CORETSEO0II[0] 0.218 5.242 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEO0II[1] System SLE Q CORETSEO0II[1] 0.218 5.298 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEO0II[2] System SLE Q CORETSEO0II[2] 0.218 5.327 CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI\.CORETSEI11lI.CORETSEoIiII.CORETSEiOi0.CORETSEIi1o[3] System SLE Q CORETSEIi1o[3] 0.201 5.576 ======================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] System SLE D currTapState_ns[1] 10.000 -27.793 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] System SLE D N_95_i 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] System SLE D gen_N_3_mux_0_0 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] System SLE D gen_N_3_mux_0_5 10.000 -27.728 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[4] System SLE D gen_N_3_mux_0_4 10.000 -27.713 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] System SLE D gen_N_3_mux_0_6 10.000 -27.713 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[3] System SLE D currTapState_ns[3] 10.000 -27.668 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[6] System SLE D N_102_i 10.000 -27.668 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[10] System SLE D currTapState_ns[10] 10.000 -27.668 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[13] System SLE D gen_N_3_mux_0_2 10.000 -27.668 =================================================================================================================================================================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.792 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.792 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 8 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[1] CFG4 D In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[1] CFG4 Y Out 0.212 37.675 f - currTapState_ns[1] Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[1] SLE D In - 37.792 f - ======================================================================================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 37.792 is 3.787(10.0%) logic and 34.006(90.0%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 2: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.728 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.728 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 8 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 C In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[2] CFG4 Y Out 0.148 37.610 r - N_95_i Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[2] SLE D In - 37.728 r - ======================================================================================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 37.728 is 3.723(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 3: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.728 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.728 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 8 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[12] CFG3 C In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[12] CFG3 Y Out 0.148 37.610 r - gen_N_3_mux_0_5 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[12] SLE D In - 37.728 r - ======================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.728 is 3.723(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 4: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.728 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.728 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 8 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[5] CFG3 C In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[5] CFG3 Y Out 0.148 37.610 r - gen_N_3_mux_0_0 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[5] SLE D In - 37.728 r - ======================================================================================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 37.728 is 3.723(9.9%) logic and 34.006(90.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value Path information for path number 5: Requested Period: 10.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.000 - Propagation time: 37.713 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -27.713 Number of logic level(s): 36 Starting point: core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst / UTDI Ending point: MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] / D The start point is clocked by System [rising] The end point is clocked by COREJTAGDEBUG_Z1|iUDRCK_inferred_clock [rising] (rise=0.000 fall=5.000 period=10.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- core_jatg_debug_0_0.core_jatg_debug_0_0.genblk1\.genblk1\.genblk1\.UJTAG_inst UJTAG UTDI Out 0.000 0.000 r - UTDIInt Net - - 0.948 - 8 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 B In - 0.948 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.dut_tms_int CFG3 Y Out 0.083 1.031 r - dut_tms_int Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD A In - 1.979 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[0\]\.BUFD_BLK BUFD Y Out 0.103 2.082 r - delay_sel[1] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD A In - 3.030 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[1\]\.BUFD_BLK BUFD Y Out 0.103 3.132 r - delay_sel[2] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD A In - 4.080 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[2\]\.BUFD_BLK BUFD Y Out 0.103 4.183 r - delay_sel[3] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD A In - 5.131 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[3\]\.BUFD_BLK BUFD Y Out 0.103 5.234 r - delay_sel[4] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD A In - 6.182 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[4\]\.BUFD_BLK BUFD Y Out 0.103 6.285 r - delay_sel[5] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD A In - 7.232 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[5\]\.BUFD_BLK BUFD Y Out 0.103 7.335 r - delay_sel[6] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD A In - 8.283 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[6\]\.BUFD_BLK BUFD Y Out 0.103 8.386 r - delay_sel[7] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD A In - 9.334 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[7\]\.BUFD_BLK BUFD Y Out 0.103 9.437 r - delay_sel[8] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD A In - 10.385 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[8\]\.BUFD_BLK BUFD Y Out 0.103 10.487 r - delay_sel[9] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD A In - 11.435 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[9\]\.BUFD_BLK BUFD Y Out 0.103 11.538 r - delay_sel[10] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD A In - 12.486 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[10\]\.BUFD_BLK BUFD Y Out 0.103 12.589 r - delay_sel[11] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD A In - 13.537 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[11\]\.BUFD_BLK BUFD Y Out 0.103 13.639 r - delay_sel[12] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD A In - 14.587 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[12\]\.BUFD_BLK BUFD Y Out 0.103 14.690 r - delay_sel[13] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD A In - 15.638 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[13\]\.BUFD_BLK BUFD Y Out 0.103 15.741 r - delay_sel[14] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD A In - 16.689 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[14\]\.BUFD_BLK BUFD Y Out 0.103 16.791 r - delay_sel[15] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD A In - 17.739 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[15\]\.BUFD_BLK BUFD Y Out 0.103 17.842 r - delay_sel[16] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD A In - 18.790 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[16\]\.BUFD_BLK BUFD Y Out 0.103 18.893 r - delay_sel[17] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD A In - 19.841 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[17\]\.BUFD_BLK BUFD Y Out 0.103 19.944 r - delay_sel[18] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD A In - 20.892 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[18\]\.BUFD_BLK BUFD Y Out 0.103 20.994 r - delay_sel[19] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD A In - 21.942 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[19\]\.BUFD_BLK BUFD Y Out 0.103 22.045 r - delay_sel[20] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD A In - 22.993 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[20\]\.BUFD_BLK BUFD Y Out 0.103 23.096 r - delay_sel[21] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD A In - 24.044 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[21\]\.BUFD_BLK BUFD Y Out 0.103 24.146 r - delay_sel[22] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD A In - 25.094 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[22\]\.BUFD_BLK BUFD Y Out 0.103 25.197 r - delay_sel[23] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD A In - 26.145 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[23\]\.BUFD_BLK BUFD Y Out 0.103 26.248 r - delay_sel[24] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD A In - 27.196 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[24\]\.BUFD_BLK BUFD Y Out 0.103 27.299 r - delay_sel[25] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD A In - 28.247 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[25\]\.BUFD_BLK BUFD Y Out 0.103 28.349 r - delay_sel[26] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD A In - 29.297 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[26\]\.BUFD_BLK BUFD Y Out 0.103 29.400 r - delay_sel[27] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD A In - 30.348 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[27\]\.BUFD_BLK BUFD Y Out 0.103 30.451 r - delay_sel[28] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD A In - 31.399 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[28\]\.BUFD_BLK BUFD Y Out 0.103 31.501 r - delay_sel[29] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD A In - 32.449 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[29\]\.BUFD_BLK BUFD Y Out 0.103 32.552 r - delay_sel[30] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD A In - 33.500 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[30\]\.BUFD_BLK BUFD Y Out 0.103 33.603 r - delay_sel[31] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD A In - 34.551 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[31\]\.BUFD_BLK BUFD Y Out 0.103 34.653 r - delay_sel[32] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD A In - 35.601 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[32\]\.BUFD_BLK BUFD Y Out 0.103 35.704 r - delay_sel[33] Net - - 0.948 - 1 core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD A In - 36.652 r - core_jatg_debug_0_0.core_jatg_debug_0_0.genblk3\.genblk1\.UJ_JTAG.BUFD_TMS.bufd_gen\[33\]\.BUFD_BLK BUFD Y Out 0.103 36.755 r - core_jatg_debug_0_0_TGT_TMS_0 Net - - 0.708 - 15 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[11] CFG4 C In - 37.462 r - MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState_RNO[11] CFG4 Y Out 0.132 37.595 f - gen_N_3_mux_0_6 Net - - 0.118 - 1 MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug\.u_opsrv_debug_unit_0.MIV_opsrv_debug_transport_module_jtag_0.gen_current_state_register_active_high\.gen_current_state_register_active_low\.currTapState[11] SLE D In - 37.713 f - ======================================================================================================================================================================================================================================================================================== Total path delay (propagation time + setup) of 37.713 is 3.707(9.8%) logic and 34.006(90.2%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied @W:MT447 : synthesis.fdc(25) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(26) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(27) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(29) | Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1] }]) (false path) was not applied to the design because no matching path was synchronous @W:MT447 : synthesis.fdc(30) | Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(31) | Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(32) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(33) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(34) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(35) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(36) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(37) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(38) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(39) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(40) | Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(41) | Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(42) | Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(43) | Timing constraint (to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(44) | Timing constraint (to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design @W:MT447 : synthesis.fdc(45) | Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design None Finished final timing analysis (Real Time elapsed 0h:03m:11s; CPU Time elapsed 0h:02m:52s; Memory used current: 598MB peak: 747MB) Finished timing report (Real Time elapsed 0h:03m:12s; CPU Time elapsed 0h:02m:52s; Memory used current: 598MB peak: 747MB) --------------------------------------- Resource Usage Report for top Mapping to part: mpf300tfcg1152-1 Cell usage: AND2 1 use BANKEN 1 use BUFD 102 uses CLKINT 9 uses DLL 1 use HS_IO_CLK 4 uses ICB_CLKDIV 1 use INIT 1 use INV 4 uses IOD 5 uses LANECTRL 2 uses OR2 32 uses OR4 1344 uses PLL 2 uses RCLKINT 1 use UJTAG 1 use CFG1 86 uses CFG2 1678 uses CFG3 3631 uses CFG4 7097 uses Carry cells: ARI1 1577 uses - used for arithmetic functions ARI1 161 uses - used for Wide-Mux implementation Total ARI1 1738 uses Sequential Cells: SLE 6607 uses DSP Blocks: 0 of 924 (0%) I/O ports: 27 I/O primitives: 19 BIBUF 1 use INBUF 4 uses INBUF_DIFF 2 uses OUTBUF 11 uses OUTBUF_DIFF 1 use Global Clock Buffers: 10 RAM/ROM usage summary Total Block RAMs (RAM1K20) : 44 of 952 (4%) Total Block RAMs (RAM64x12) : 10 of 2772 (0%) Total LUTs: 14230 Extra resources required for RAM and MACC_PA interface logic during P&R: RAM64X12 Interface Logic : SLEs = 120; LUTs = 120; RAM1K20 Interface Logic : SLEs = 1584; LUTs = 1584; MACC_PA Interface Logic : SLEs = 0; LUTs = 0; MACC_PA_BC_ROM Interface Logic : SLEs = 0; LUTs = 0; Total number of SLEs after P&R: 6607 + 120 + 1584 + 0 = 8311; Total number of LUTs after P&R: 14230 + 120 + 1584 + 0 = 15934; Mapper successful! At Mapper Exit (Real Time elapsed 0h:03m:12s; CPU Time elapsed 0h:02m:53s; Memory used current: 401MB peak: 747MB) Process took 0h:03m:12s realtime, 0h:02m:53s cputime # Thu Feb 25 12:44:49 2021 ###########################################################]