Project Settings
Project Name top_syn Device Name synthesis: Microchip PolarFire : MPF300T
Implementation Name synthesis Top Module top
Retiming 0 Resource Sharing 1
Fanout Guide 10000 Disable I/O Insertion 0
Disable Sequential Optimizations 0 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 315 465 0 - 00m:56s - 2/25/2021
12:41:22 PM
(premap)Complete 88 13 0 0m:08s 0m:09s 257MB 2/25/2021
12:41:35 PM
(fpga_mapper)Complete 247 164 0 02m:53s 03m:12s 747MB 2/25/2021
12:44:48 PM
Multi-srs Generator Complete00m:01s2/25/2021
12:41:25 PM

Area Summary
Carry Cells 1738 Sequential Cells 6607
DSP Blocks (dsp_used) 0 I/O Cells 19
Global Clock Buffers 10 RAM1K20 (v_ram) 44
RAM64x12 (v_ram) 10 LUTs (total_luts) 14230

Timing Summary
Clock NameReq FreqEst FreqSlack
COREJTAGDEBUG_Z1|iUDRCK_inferred_clock100.0 MHz13.4 MHz-32.246
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT080.0 MHz58.9 MHz-4.484
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R125.0 MHz155.3 MHz1.563
PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep100.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3625.0 MHzNANA
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV125.0 MHz256.0 MHz4.095
PHY_MDC_CLOCK2.9 MHzNANA
REFCLK_P125.0 MHzNANA
REF_CLK_050.0 MHzNANA
TCK10.0 MHzNANA
System100.0 MHz226.1 MHz5.576

Optimizations Summary
Combined Clock Conversion 4 / 10