@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\petfn_top.v":10445:0:10445:5|Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEl1oI because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEI1oI. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEiol0[5:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEIil0[1:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEO0ol[7:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\t8b10b.v":148:0:148:3|ROM CORETSEIil0[1:0] (in view: work.CORETSE_0_CORETSE_0_0_T8B10B(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEiiol (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_1(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":3418:0:3418:3|ROM CORETSEoiol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|ROM CORETSEIool (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEl0ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEI1ol[2:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1261:0:1261:3|ROM CORETSEO1ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":268:0:268:3|ROM CORETSEI0ol[1:0] (in view: work.CORETSE_0_CORETSE_0_0_R10B8B_0(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: FA239 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16547:4:16547:7|ROM lsu_emi_req_write_1[1:0] (in view: work.miv_rv32_lsu_32s_2s_1s_2s_2s(verilog)) mapped in logic. To map to a technology ROM, apply attribute syn_romstyle on this instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][3] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][1] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][8] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][7] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][5] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][8] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][7] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][5] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_d_trx_os_buffer.gen_buff_loop\[1\]\.buff_data\[1\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][4] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][3] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":4773:4:4773:9|Register bit MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_opsrv_interconnect_0.u_i_trx_os_buffer.gen_buff_loop\[0\]\.buff_data\[0\][1] (in view view:work.top(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_1(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\actel\directcore\corespi\5.2.104\rtl\vlog\core\spi_fifo.v":101:0:101:5|RAM fifo_mem_q[16:0] (in view: CORESPI_LIB.spi_fifo_16s_32s_5_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\rx4096x36.v":139:0:139:5|RAM CORETSEo01lI.CORETSEIIil[35:0] (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\tx2048x40.v":139:0:139:5|RAM CORETSEl01lI.CORETSEIIil[39:0] (in view: work.CORETSE_0_CORETSE_0_0_CORETSE_TOP_1s_11s_12s_1s_1s_1s_26s_18s_0s(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[30] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[29] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[28] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[27] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[26] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[25] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_eim.v":1986:0:1986:5|Register bit CORETSEIllo.CORETSEII0o[24] (in view view:work.CORETSE_0_CORETSE_0_0_PEMSTAT_26s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":2224:0:2224:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[25] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[24]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":2224:0:2224:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[8] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coreuartapb_0\coreuartapb_0_0\rtl\vlog\core_obfuscated\rx_async.v":754:0:754:5|Removing instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.CUARTlOlI.CUARTO01.CUARTIOll[2] because it is equivalent to instance CoreUARTapb_0_inst_0.CoreUARTapb_0_0.CUARTlOlI.CUARTO01.CUARTIOll[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram1_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram1_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram2_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[11] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[11]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[12] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[12]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[13] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[13]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[14] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[14]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[15] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[15]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[4] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[4]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[5] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[5]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[6]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[7] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[7]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[8] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[8]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[9] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[9]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[10] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[10]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[2]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp_1.gen_buff_loop[0].buff_entry_data_resp_1_ram0_[3] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram0_[3]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":16192:4:16192:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp_1.gen_buff_loop[0].buff_entry_error_resp_1_ram2_[0] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_fetch_unit_0.u_miv_rv32_ifu_iab_0.gen_buff_loop[0].buff_entry_error_resp.gen_buff_loop[0].buff_entry_error_resp_ram2_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":8739:2:8739:7|Register bit de_ex_pipe_operand0_mux_sel_ex[1] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":8739:2:8739:7|Register bit de_ex_pipe_operand1_mux_sel_ex[2] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":8832:2:8832:7|Register bit de_ex_pipe_bcu_operand0_mux_sel_ex[1] (in view view:work.miv_rv32_expipe_Z9(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":8739:2:8739:7|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_shifter_unit_places_sel_ex[2] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.de_ex_pipe_shifter_unit_operand_sel_ex[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":5963:6:5963:18|RAM gen_gpr\.u_gpr_array_0.mem_1[31:0] (in view: work.miv_rv32_gpr_ram_0s_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: FX107 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":5963:6:5963:18|RAM gen_gpr\.u_gpr_array_0.mem[31:0] (in view: work.miv_rv32_gpr_ram_0s_0(verilog)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12464:12:12464:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.rdAddrGrayReg_r[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.rdAddrReg_r[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12443:12:12443:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.wrAddrReg_w[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_req_fifo.genblk2.wrAddrGrayReg_w[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12443:12:12443:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.wrAddrReg_w[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.wrAddrGrayReg_w[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12464:12:12464:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.rdAddrGrayReg_r[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.genblk2.rdAddrReg_r[1]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":14288:2:14288:7|Register bit hipri_req_ptr[6] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":14288:2:14288:7|Register bit hipri_req_ptr[4] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: MO160 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":14288:2:14288:7|Register bit hipri_req_ptr[2] (in view view:work.miv_rv32_rr_pri_arb_3s_1s_1s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\msgmii_clkrst.v":298:0:298:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEo00II because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEI00II. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\msgmii_clkrst.v":233:0:233:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEl00II because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEOIiII.CORETSEi00II. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12426:12:12426:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram0_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram0_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":12426:12:12426:20|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram1_[1] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.gen_opsrv_debug.u_opsrv_debug_unit_0.debug_resp_fifo.fifoMem_fifoMem_ram1_[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\petfn_top.v":10871:0:10871:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[49] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEioolI.CORETSEiOI1.CORETSEloI1.CORETSEoIoI[48]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\microsemi\miv\miv_rv32\3.0.100\core_merged\miv_rv32_core_merged.v":5485:4:5485:9|Removing instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata2_match_data.gen_bit_reset.state_val[6] because it is equivalent to instance MIV_RV32_C0_0.MIV_RV32_C0_0.u_opsrv_0.u_core_0.u_expipe_0.u_csr_privarch_0.gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_execute.gen_bit_reset.state_val[0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":2224:0:2224:5|Removing instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[40] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEIillI.CORETSEoiolI.CORETSEoOilI.CORETSEoIlo.CORETSEioOo[28]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_4_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_3_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_4_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_3_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_2_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEl1li.CORETSEi1ol_00_1_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BN132 :"f:\dg0799_final\libero_project\libero_project\component\work\coretse_0\coretse_0_0\rtl\vlog\obfuscated\r10b8b.v":1950:0:1950:4|Removing sequential instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_2_dreg[2:0] because it is equivalent to instance CORETSE_0_inst_0.CORETSE_0_0.CORETSEooIlI.CORETSEi01lI.CORETSEI11lI.CORETSEoIiII.CORETSEiio0.CORETSEo1li.CORETSEi1ol_00_1_dreg[2:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":47:0:47:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":48:0:48:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":49:0:49:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":50:0:50:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":51:0:51:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":52:0:52:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":53:0:53:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":54:0:54:0|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: BW150 :|Clock COREJTAGDEBUG_UJ_JTAG_26s_0s_34s_85_0_0|un1_DUT_TCK_inferred_clock in set_clock_groups command cannot be found and will not be forward annotated
@W: BW156 :|Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool.
@W: MT246 :"f:\dg0799_final\libero_project\libero_project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":40:53:40:58|Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results)
@W: MT420 |Found inferred clock PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL|CDR_CLK_keep with period 10.00ns. Please declare a user-defined clock on net PF_IOD_CDR_C0_0.PF_LANECTRL_0.CDR_CLK.
@W: MT420 |Found inferred clock COREJTAGDEBUG_Z1|iUDRCK_inferred_clock with period 10.00ns. Please declare a user-defined clock on net core_jatg_debug_0_0.core_jatg_debug_0_0.iUDRCK_0.
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":25:0:25:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.RESET }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":26:0:26:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK_PAUSE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":27:0:27:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.SWITCH }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":29:0:29:0|Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.valid_flag[1] }]) (false path) was not applied to the design because no matching path was synchronous 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":30:0:30:0|Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.early_flag[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":31:0:31:0|Timing constraint (to [get_cells { PF_IOD_CDR_C0_0.CDR4_CNTL_TIP_0.late_flag[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":32:0:32:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":33:0:33:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":34:0:34:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.ARST_N }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":35:0:35:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":36:0:36:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":37:0:37:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.RX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":38:0:38:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_TX_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":39:0:39:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_P_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":40:0:40:0|Timing constraint (to [get_pins { PF_IOD_CDR_C0_0.PF_IOD_CDR_RX_N_0.I_IOD_0.TX_SYNC_RST }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":41:0:41:0|Timing constraint (from [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.HS_IO_CLK* }] through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CLK_OUT_R }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":42:0:42:0|Timing constraint (through [get_pins { PF_IOD_CDR_C0_0.PF_LANECTRL_0.I_LANECTRL.CDR_CLK }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":43:0:43:0|Timing constraint (to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.lock_sync[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":44:0:44:0|Timing constraint (to [get_cells { PF_IOD_CDR_CCC_C0_0.PF_COREDELAYCODE_TIP_0.diff_sync[1] }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
@W: MT447 :"f:/dg0799_final/libero_project/libero_project/designer/top/synthesis.fdc":45:0:45:0|Timing constraint (to [get_pins { PF_IOD_CDR_CCC_C0_0.PF_CCC_0.dll_inst_0.CODE_UPDATE }]) (false path) was not applied to the design because none of the paths specified by the constraint exist in the design 
