@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":805:7:805:17|Net resetn_rx_s is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":662:0:662:10|Net CORETSEI1li is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif_hst.v":2346:0:2346:11|Net CORETSEiIIOI is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_sys.v":1858:0:1858:11|Net CORETSEll0OI is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":290:0:290:10|Net CORETSEioil is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":305:0:305:10|Net CORETSEOiil is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":387:0:387:10|Net CORETSEol10 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":407:0:407:10|Net CORETSEil10 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":427:0:427:10|Net CORETSEO010 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":447:0:447:10|Net CORETSEI010 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":467:0:467:10|Net CORETSEl010 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsm_sysreg.v":487:0:487:10|Net CORETSEo010 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":2449:0:2449:9|Net CORETSEio1 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac_core.v":1247:0:1247:10|Net CORETSEooI1 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac.v":983:0:983:10|Net CORETSEoOI1 is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\si_sal.v":935:0:935:10|Net CORETSEIiil is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":2145:0:2145:11|Net CORETSEIiolI is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":2152:0:2152:11|Net CORETSEliolI is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE.v":253:0:253:10|Net CORETSEioil is not declared.
@W: CG1337 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE.v":268:0:268:10|Net CORETSEOiil is not declared.
@W: CS138 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":23965:0:23907:8|Macro definition for RAM_BIST_VIEW_BEHAV not found. Cannot undefine.
@W: CS138 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":23966:0:23907:8|Macro definition for RAM_BIST_VIEW not found. Cannot undefine.
@W: CS141 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":25840:14:25840:28|Unrecognized synthesis directive dc_script_begin. Verify the correct directive name.
@W: CS141 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":25843:14:25843:26|Unrecognized synthesis directive dc_script_end. Verify the correct directive name.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v":147:8:147:52|Removing wire UJTAG_BYPASS_TDO_0, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v":154:8:154:52|Removing wire UJTAG_BYPASS_TDO_1, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v":161:8:161:52|Removing wire UJTAG_BYPASS_TDO_2, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v":168:8:168:52|Removing wire UJTAG_BYPASS_TDO_3, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\COREJTAGDEBUG\3.1.100\core\corejtagdebug.v":218:28:218:37|Removing wire iURSTB_inv, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":244:12:244:20|Removing wire IA_PRDATA, as there is no assignment to it.
@W: CL208 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":134:0:134:5|All reachable assignments to bit 3 of control2[7:0] assign 0, register removed by optimization.
@W: CG1340 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Index into variable txfifo_dhold could be out of range ; a simulation mismatch is possible.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":195:12:195:22|Object resetn_rx_d is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":196:12:196:22|Removing wire resetn_rx_p, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":200:12:200:22|Removing wire resetn_rx_r, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":222:12:222:36|Object stxs_txready_at_ssel_temp is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":1130:0:1130:5|Pruning unused register msrxs_ssel. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning unused register stxs_oen. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":719:0:719:5|Pruning unused register spi_ssel_neg. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_bitcnt[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":416:0:416:5|Pruning unused register mtx_ssel. Make sure that there are no unused intermediate registers.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":343:0:343:5|Sharing sequential element cfg_enable_P1. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v":203:0:203:11|Removing wire CORETSElioOI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v":206:0:206:11|Removing wire CORETSEoioOI, as there is no assignment to it.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v":301:0:301:5|Pruning unused register CORETSEli1lI. Make sure that there are no unused intermediate registers.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v":1047:0:1047:10|Type of parameter CORETSEO10i on the instance CORETSEI0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v":1233:0:1233:10|Type of parameter CORETSEO10i on the instance CORETSEl0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":546:0:546:11|Object CORETSEiOoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":549:0:549:11|Object CORETSEOIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":552:0:552:11|Object CORETSEIIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":562:0:562:11|Object CORETSElIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":572:0:572:11|Object CORETSEoIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":588:0:588:11|Object CORETSEiIoOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":2068:0:2068:5|Pruning unused bits 1 to 0 of genblk2.CORETSEl01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1583:0:1583:5|Pruning unused bits 13 to 2 of CORETSEo01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1553:0:1553:5|Pruning unused bits 1 to 0 of CORETSEI01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":1484:0:1484:5|Pruning unused bits 1 to 0 of CORETSEO01OI[13:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxtfif_sys.v":2019:0:2019:5|Removing unused bit 38 of genblk2.CORETSEI11OI[39:0]. Either assign all bits or reduce the width of the signal.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v":1404:0:1404:10|Type of parameter CORETSEO10i on the instance CORETSEo0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":636:0:636:5|Pruning unused register CORETSEiiIOI. Make sure that there are no unused intermediate registers.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[36] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[37] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[38] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Optimizing register bit CORETSEoloi[39] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":2168:0:2168:5|Pruning register bits 39 to 36 of CORETSEoloi[39:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":1532:0:1532:5|Pruning unused register CORETSEl0IOI. Make sure that there are no unused intermediate registers.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v":1545:0:1545:10|Type of parameter CORETSEO10i on the instance CORETSEi0ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_sys.v":2075:0:2075:5|Pruning unused register CORETSEoI0OI. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_sys.v":1783:0:1783:5|Pruning unused register CORETSElI0OI[14:0]. Make sure that there are no unused intermediate registers.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif.v":1867:0:1867:10|Type of parameter CORETSEO10i on the instance CORETSEl1ii is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxfif_hst.v":909:0:909:11|Removing wire CORETSEo1OOI, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":423:0:423:10|Object CORETSEl0oI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":426:0:426:10|Removing wire CORETSEo0oI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":450:0:450:10|Removing wire CORETSEiOlI, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":510:0:510:10|Object CORETSEiOiI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":513:0:513:10|Object CORETSEOIiI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":532:0:532:10|Object CORETSEOliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":534:0:534:10|Object CORETSEIliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":537:0:537:10|Object CORETSElliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":539:0:539:10|Object CORETSEoliI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":977:0:977:10|Removing wire CORETSEOOll, as there is no assignment to it.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":4448:0:4448:5|Pruning unused register CORETSEioiI[15:0]. Make sure that there are no unused intermediate registers.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Optimizing register bit CORETSEooOl[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Optimizing register bit CORETSEooOl[6] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL279 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":4128:0:4128:5|Pruning register bits 6 to 5 of CORETSEooOl[6:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":348:0:348:9|Removing wire CORETSEI0I, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":655:0:655:9|Removing wire CORETSEOI1, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":658:0:658:9|Object CORETSEII1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":613:0:613:10|Object CORETSEOlI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":709:0:709:10|Object CORETSEIlI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":714:0:714:10|Object CORETSEllI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":716:0:716:10|Object CORETSEolI1 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":2022:0:2022:5|Pruning unused register CORETSEllo1. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":1990:0:1990:5|Pruning unused register CORETSEIlo1. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pehst.v":1958:0:1958:5|Pruning unused register CORETSEOlo1. Make sure that there are no unused intermediate registers.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac.v":681:0:681:10|Removing wire CORETSEllO1, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac.v":684:0:684:10|Removing wire CORETSEOio0, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pe_mcxmac.v":687:0:687:10|Removing wire CORETSEiIo0, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\sib_sync_2flp.v":77:0:77:10|Object CORETSEolO0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":113:0:113:10|Removing wire CORETSElllo, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":115:0:115:10|Removing wire CORETSEollo, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":118:0:118:10|Object CORETSEillo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":120:0:120:10|Object CORETSEO0lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":129:0:129:10|Object CORETSEi0lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":131:0:131:10|Object CORETSEO1lo is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":154:0:154:11|Removing wire CORETSEII1lI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":156:0:156:11|Removing wire CORETSElI1lI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":158:0:158:11|Removing wire CORETSEoI1lI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":160:0:160:11|Removing wire CORETSEiI1lI, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":162:0:162:11|Removing wire CORETSEOl1lI, as there is no assignment to it.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":154:0:154:11|*Output CORETSEII1lI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":156:0:156:11|*Output CORETSElI1lI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":158:0:158:11|*Output CORETSEoI1lI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":160:0:160:11|*Output CORETSEiI1lI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":162:0:162:11|*Output CORETSEOl1lI has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tx2048x40.v":93:0:93:10|Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\rx4096x36.v":93:0:93:10|Object CORETSElOil is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvtxi.v":364:0:364:5|Pruning unused register CORETSEO0oII[3:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petex_top.v":690:0:690:5|Pruning unused register CORETSEO1II. Make sure that there are no unused intermediate registers.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":219:0:219:10|Object CORETSEiOo0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":188:0:188:10|Object CORETSEiO0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":196:0:196:10|Object CORETSEOI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":199:0:199:10|Object CORETSEII0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":202:0:202:10|Object CORETSElI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":205:0:205:10|Object CORETSEoI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":213:0:213:10|Object CORETSEiI0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":216:0:216:10|Removing wire CORETSEOl0i, as there is no assignment to it.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":222:0:222:10|Object CORETSEIl0i is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":2085:0:2085:5|Pruning unused register CORETSEll0i. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":1890:0:1890:5|Pruning unused register CORETSEIili. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":1854:0:1854:5|Pruning unused register CORETSEOili. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pma.v":1818:0:1818:5|Pruning unused register CORETSEioli. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":4321:0:4321:5|Pruning unused register CORETSElIli. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":4260:0:4260:5|Pruning unused register CORETSEOIli. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":4101:0:4101:5|Pruning unused register CORETSEI1lI. Make sure that there are no unused intermediate registers.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":1303:0:1303:5|Removing unused bit 3 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perex_pcs.v":1303:0:1303:5|Removing unused bit 1 of CORETSEoIol[3:0]. Either assign all bits or reduce the width of the signal.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":3121:0:3121:5|Pruning unused register CORETSEiIIlI. Make sure that there are no unused intermediate registers.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":3041:0:3041:5|Removing unused bit 14 of CORETSElIIlI[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":2437:0:2437:5|Removing unused bit 14 of CORETSEl1OlI[15:0]. Either assign all bits or reduce the width of the signal.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":2361:0:2361:5|Sharing sequential element CORETSEI0OlI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petbm.v":2544:0:2544:5|Pruning unused register CORETSEIIio. Make sure that there are no unused intermediate registers.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":145:0:145:10|Object CORETSEIiOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":147:0:147:10|Object CORETSEliOI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":150:0:150:10|Removing wire CORETSEoiOI, as there is no assignment to it.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":319:0:319:5|Sharing sequential element CORETSEooOI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":422:0:422:5|Sharing sequential element CORETSEoOII. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_tbi.v":411:0:411:10|Removing wire CORETSEIio0, as there is no assignment to it.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_cnvrxi.v":496:0:496:5|Pruning unused register CORETSEIl1II[1:0]. Make sure that there are no unused intermediate registers.
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":825:0:825:0|Input CORETSEIO1lI on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":829:0:829:0|Input CORETSElO1lI on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":833:0:833:0|Input CORETSEoO1lI on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":837:0:837:0|Input CORETSEiO1lI on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":841:0:841:0|Input CORETSEOI1lI on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":865:0:865:0|Input CORETSEOl00 on instance CORETSEIillI is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":90:0:90:2|Removing wire TXD, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":92:0:92:3|Removing wire TXEN, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":94:0:94:3|Removing wire TXER, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":364:0:364:11|Removing wire CORETSEl0llI, as there is no assignment to it.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":90:0:90:2|*Output TXD has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":92:0:92:3|*Output TXEN has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE_top.v":94:0:94:3|*Output TXER has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE.v":247:0:247:9|Removing wire CORETSElo1, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\CoreTSE.v":250:0:250:9|Removing wire CORETSEoo1, as there is no assignment to it.
@W: CG1340 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":605:0:605:5|Index into variable CUARTIl0l could be out of range ; a simulation mismatch is possible.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Optimizing register bit CUARTI00l to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Tx_async.v":301:0:301:5|Pruning unused register CUARTI00l. Make sure that there are no unused intermediate registers.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\Rx_async.v":1613:0:1613:5|Sharing sequential element CUARTI1l. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":333:0:333:7|Object CUARTlI0 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1268:0:1268:5|Pruning unused register CUARTO10. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTOl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1159:0:1159:5|Pruning unused register CUARTIl0. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":1106:0:1106:5|Pruning unused register CUARTIOl[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":984:0:984:5|Pruning unused register CUARTll0[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTOI0. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":936:0:936:5|Pruning unused register CUARTlO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTOO0. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":888:0:888:5|Pruning unused register CUARTl1l. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUART.v":405:0:405:5|Pruning unused register CUARTIll. Make sure that there are no unused intermediate registers.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":283:0:283:8|Object CUARTI1OI is declared but not assigned. Either assign a value or remove the declaration.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":432:0:432:8|Type of parameter RAM_SB_IN_WIDTH on the instance u_opsrv_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":432:0:432:8|Type of parameter RAM_SB_OUT_WIDTH on the instance u_opsrv_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16466:38:16466:51|Object req_resp_fault is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16474:38:16474:57|Object lsu_emi_req_accepted is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16477:38:16477:53|Object emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16478:38:16478:58|Object next_emi_req_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16479:38:16479:62|Object emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16480:38:16480:67|Object next_emi_req_os_count_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16481:38:16481:49|Object inc_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16482:38:16482:49|Object dec_os_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16483:38:16483:56|Object emi_req_os_at_flush is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16484:38:16484:52|Object next_emi_req_os is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10641:2:10641:7|Pruning unused register div_divisor[62:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10641:2:10641:7|Pruning unused register dividend[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10641:2:10641:7|Pruning unused register res_pos_neg. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10641:2:10641:7|Pruning unused register quotient[31:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10633:2:10633:7|Pruning unused register div_ack. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10623:2:10623:7|Pruning unused register slow_mul_ack. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10615:2:10615:7|Pruning unused register mul_div_cnt[31:0]. Make sure that there are no unused intermediate registers.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":10661:2:10661:7|Pruning unused bits 64 to 32 of exu_result_reg_int[64:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3976:18:3976:51|Object machine_init_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3977:18:3977:53|Object machine_init_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3978:18:3978:49|Object machine_sw_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3979:18:3979:51|Object machine_sw_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3989:18:3989:61|Object machine_init_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3990:18:3990:63|Object machine_init_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3991:18:3991:59|Object machine_sw_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3992:18:3992:61|Object machine_sw_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3996:18:3996:43|Object tdata1_mcontrol_action_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3997:18:3997:61|Object machine_init_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3998:18:3998:63|Object machine_init_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3999:18:3999:59|Object machine_sw_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4000:18:4000:61|Object machine_sw_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4004:18:4004:56|Object machine_init_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4005:18:4005:58|Object machine_init_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4006:18:4006:54|Object machine_sw_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4007:18:4007:56|Object machine_sw_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3976:18:3976:51|Object machine_init_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3977:18:3977:53|Object machine_init_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3978:18:3978:49|Object machine_sw_wr_tdata1_dmode_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3979:18:3979:51|Object machine_sw_wr_tdata1_dmode_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3989:18:3989:61|Object machine_init_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3990:18:3990:63|Object machine_init_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3991:18:3991:59|Object machine_sw_wr_tdata1_mcontrol_select_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3992:18:3992:61|Object machine_sw_wr_tdata1_mcontrol_select_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3996:18:3996:43|Object tdata1_mcontrol_action_reg is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3997:18:3997:61|Object machine_init_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3998:18:3998:63|Object machine_init_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":3999:18:3999:59|Object machine_sw_wr_tdata1_mcontrol_action_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4000:18:4000:61|Object machine_sw_wr_tdata1_mcontrol_action_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4004:18:4004:56|Object machine_init_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4005:18:4005:58|Object machine_init_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4006:18:4006:54|Object machine_sw_wr_tdata1_mcontrol_m_wr_en is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4007:18:4007:56|Object machine_sw_wr_tdata1_mcontrol_m_wr_data is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5448:8:5448:18|Object wr_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":1815:32:1815:40|Object irq_m_swi is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":1992:32:1992:47|Object mcause_sw_rd_sel is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":1993:32:1993:47|Object mcause_sw_wr_sel is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":2096:50:2096:63|Object sw_rd_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":2101:50:2101:64|Object ext_msip_retime is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":2102:50:2102:64|Object ext_mtip_retime is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":2103:50:2103:64|Object ext_meip_retime is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":2121:50:2121:69|Object debugger_rd_en_valid is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":4093:6:4093:26|Removing instance gen_tdata1_2.gen_per_trig_tdata1[1].u_tdata1_mcontrol_hit because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5838:2:5838:7|Pruning unused register gpr_wr_sel_reg[4:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":5838:2:5838:7|Pruning unused register gpr_wr_valid_reg. Make sure that there are no unused intermediate registers.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":13773:2:13773:31|Removing instance u_opsrv_core_gpr_ded_reset_reg because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":10991:0:10991:8|Removing unused bit 23 of command_reg[31:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":10991:0:10991:8|Pruning unused bits 19 to 18 of command_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":10991:0:10991:8|Optimizing register bit abstractcs_busyerr to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":10991:0:10991:8|Pruning unused register abstractcs_busyerr. Make sure that there are no unused intermediate registers.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8807:12:8807:44|Removing instance miv_rv32_ram_singleport_lp_R119C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8734:27:8734:41|Removing instance \CFG2_BLKY2[26] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8645:12:8645:43|Removing instance miv_rv32_ram_singleport_lp_R86C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8564:12:8564:43|Removing instance miv_rv32_ram_singleport_lp_R53C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8534:27:8534:41|Removing instance \CFG2_BLKY2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8428:27:8428:41|Removing instance \CFG2_BLKX2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8318:12:8318:43|Removing instance miv_rv32_ram_singleport_lp_R71C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8262:12:8262:43|Removing instance miv_rv32_ram_singleport_lp_R87C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8259:27:8259:33|Removing instance CFG3_17 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8222:12:8222:43|Removing instance miv_rv32_ram_singleport_lp_R52C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8170:12:8170:44|Removing instance miv_rv32_ram_singleport_lp_R124C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8132:12:8132:43|Removing instance miv_rv32_ram_singleport_lp_R63C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8122:27:8122:41|Removing instance \CFG2_BLKX2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8073:12:8073:43|Removing instance miv_rv32_ram_singleport_lp_R95C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":8033:12:8033:43|Removing instance miv_rv32_ram_singleport_lp_R98C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7955:12:7955:44|Removing instance miv_rv32_ram_singleport_lp_R117C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7936:27:7936:41|Removing instance \CFG2_BLKX2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7891:12:7891:44|Removing instance miv_rv32_ram_singleport_lp_R101C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7771:27:7771:41|Removing instance \CFG2_BLKX2[19] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7761:27:7761:41|Removing instance \CFG2_BLKY2[20] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7720:12:7720:43|Removing instance miv_rv32_ram_singleport_lp_R62C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7681:12:7681:43|Removing instance miv_rv32_ram_singleport_lp_R89C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7577:12:7577:43|Removing instance miv_rv32_ram_singleport_lp_R50C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7537:12:7537:43|Removing instance miv_rv32_ram_singleport_lp_R41C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7411:27:7411:41|Removing instance \CFG2_BLKY2[24] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7302:12:7302:43|Removing instance miv_rv32_ram_singleport_lp_R96C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7298:27:7298:40|Removing instance \CFG2_BLKX2[8] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7172:12:7172:44|Removing instance miv_rv32_ram_singleport_lp_R103C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7133:12:7133:44|Removing instance miv_rv32_ram_singleport_lp_R100C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7074:12:7074:43|Removing instance miv_rv32_ram_singleport_lp_R54C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":7022:12:7022:44|Removing instance miv_rv32_ram_singleport_lp_R102C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6954:12:6954:43|Removing instance miv_rv32_ram_singleport_lp_R60C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6870:12:6870:44|Removing instance miv_rv32_ram_singleport_lp_R125C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6809:27:6809:41|Removing instance \CFG2_BLKX2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6759:12:6759:43|Removing instance miv_rv32_ram_singleport_lp_R73C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6709:12:6709:43|Removing instance miv_rv32_ram_singleport_lp_R97C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6670:12:6670:44|Removing instance miv_rv32_ram_singleport_lp_R116C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6607:12:6607:43|Removing instance miv_rv32_ram_singleport_lp_R64C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6561:27:6561:41|Removing instance \CFG2_BLKY2[15] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6399:12:6399:43|Removing instance miv_rv32_ram_singleport_lp_R72C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6361:12:6361:43|Removing instance miv_rv32_ram_singleport_lp_R33C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6340:27:6340:41|Removing instance \CFG2_BLKY2[11] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6281:12:6281:43|Removing instance miv_rv32_ram_singleport_lp_R99C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6241:12:6241:44|Removing instance miv_rv32_ram_singleport_lp_R108C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6151:27:6151:41|Removing instance \CFG2_BLKX2[16] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6090:12:6090:43|Removing instance miv_rv32_ram_singleport_lp_R43C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6048:12:6048:43|Removing instance miv_rv32_ram_singleport_lp_R55C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":6002:12:6002:43|Removing instance miv_rv32_ram_singleport_lp_R58C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5940:27:5940:41|Removing instance \CFG2_BLKX2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5934:27:5934:41|Removing instance \CFG2_BLKY2[12] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5869:12:5869:43|Removing instance miv_rv32_ram_singleport_lp_R32C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5825:12:5825:44|Removing instance miv_rv32_ram_singleport_lp_R104C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5779:12:5779:43|Removing instance miv_rv32_ram_singleport_lp_R81C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5702:27:5702:41|Removing instance \CFG2_BLKY2[30] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5599:12:5599:43|Removing instance miv_rv32_ram_singleport_lp_R70C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5529:12:5529:43|Removing instance miv_rv32_ram_singleport_lp_R42C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5462:12:5462:43|Removing instance miv_rv32_ram_singleport_lp_R65C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5416:12:5416:43|Removing instance miv_rv32_ram_singleport_lp_R68C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5266:12:5266:44|Removing instance miv_rv32_ram_singleport_lp_R127C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5257:27:5257:41|Removing instance \CFG2_BLKX2[29] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5212:12:5212:43|Removing instance miv_rv32_ram_singleport_lp_R74C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5117:12:5117:43|Removing instance miv_rv32_ram_singleport_lp_R56C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5114:27:5114:40|Removing instance \CFG2_BLKX2[9] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5107:28:5107:33|Removing instance CFG3_4 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5083:27:5083:41|Removing instance \CFG2_BLKY2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":5060:27:5060:41|Removing instance \CFG2_BLKY2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4982:12:4982:44|Removing instance miv_rv32_ram_singleport_lp_R111C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4936:12:4936:43|Removing instance miv_rv32_ram_singleport_lp_R40C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4858:12:4858:43|Removing instance miv_rv32_ram_singleport_lp_R34C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4855:27:4855:41|Removing instance \CFG2_BLKX2[13] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4847:27:4847:41|Removing instance \CFG2_BLKX2[18] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4831:27:4831:41|Removing instance \CFG2_BLKY2[17] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4709:12:4709:43|Removing instance miv_rv32_ram_singleport_lp_R66C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4654:12:4654:43|Removing instance miv_rv32_ram_singleport_lp_R57C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4610:27:4610:41|Removing instance \CFG2_BLKX2[10] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4505:12:4505:44|Removing instance miv_rv32_ram_singleport_lp_R105C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4462:12:4462:43|Removing instance miv_rv32_ram_singleport_lp_R44C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4367:28:4367:33|Removing instance CFG3_3 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4346:27:4346:41|Removing instance \CFG2_BLKX2[27] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4282:12:4282:43|Removing instance miv_rv32_ram_singleport_lp_R91C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4237:12:4237:43|Removing instance miv_rv32_ram_singleport_lp_R83C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4193:12:4193:44|Removing instance miv_rv32_ram_singleport_lp_R113C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4154:12:4154:44|Removing instance miv_rv32_ram_singleport_lp_R110C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4090:12:4090:44|Removing instance miv_rv32_ram_singleport_lp_R112C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4015:12:4015:43|Removing instance miv_rv32_ram_singleport_lp_R67C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":4009:27:4009:41|Removing instance \CFG2_BLKY2[25] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3968:12:3968:43|Removing instance miv_rv32_ram_singleport_lp_R75C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3930:12:3930:43|Removing instance miv_rv32_ram_singleport_lp_R59C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3927:27:3927:41|Removing instance \CFG2_BLKX2[14] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3888:12:3888:43|Removing instance miv_rv32_ram_singleport_lp_R78C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3837:12:3837:44|Removing instance miv_rv32_ram_singleport_lp_R126C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3797:27:3797:41|Removing instance \CFG2_BLKX2[31] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3738:12:3738:44|Removing instance miv_rv32_ram_singleport_lp_R109C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3676:12:3676:43|Removing instance miv_rv32_ram_singleport_lp_R82C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3657:27:3657:41|Removing instance \CFG2_BLKY2[21] because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3513:12:3513:43|Removing instance miv_rv32_ram_singleport_lp_R35C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3470:12:3470:43|Removing instance miv_rv32_ram_singleport_lp_R38C0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv\miv_rv32_ram_singleport_lp.v":3462:28:3462:34|Removing instance CFG3_20 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9208:2:9208:7|Pruning unused register tcm_dma_access_disable_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9208:2:9208:7|Pruning unused register tcm_dap_access_disable_reg. Make sure that there are no unused intermediate registers.
@W: CL265 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9510:2:9510:7|Removing unused bit 2 of resp_dest[2:0]. Either assign all bits or reduce the width of the signal.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9303:2:9303:7|Pruning unused bits 31 to 16 of cpu_d_req_addr_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL271 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9303:2:9303:7|Pruning unused bits 1 to 0 of cpu_d_req_addr_reg[31:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":315:13:315:33|Removing wire tcm_tas_udma_ctrl_irq, as there is no assignment to it.
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":319:13:319:29|Removing wire APB_MSTR_PRDATA_P, as there is no assignment to it.
@W: CS263 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0.v":285:34:285:52|Port-width mismatch for port MSYS_EI. The port definition is 2 bits, but the actual port connection bit width is 6. Adjust either the definition or the instantiation of this port.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_CCC_0\PF_CCC_0_0\PF_CCC_0_PF_CCC_0_0_PF_CCC.v":39:12:39:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v":50:12:50:18|Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:45:70:45|Input RX_P on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_LANECTRL_OVERLAY_0\PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v":70:54:70:54|Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_N_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v":64:23:64:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_RX_P_0\PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v":67:13:67:13|Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:34:49:34|Input INFF_SL on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:46:49:46|Input INFF_EN on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":49:59:49:59|Input OUTFF_SL on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:17:50:17|Input OUTFF_EN on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:26:50:26|Input AL_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:41:50:41|Input OEFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:55:50:55|Input OEFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":50:69:50:69|Input OEFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:21:51:21|Input INFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:35:51:35|Input INFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:49:51:49|Input INFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":51:65:51:65|Input OUTFF_LAT_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:19:52:19|Input OUTFF_SD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:34:52:34|Input OUTFF_AD_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":52:59:52:59|Input RX_N on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:20:54:20|Input RX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":54:36:54:36|Input TX_SYNC_RST on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":59:21:59:21|Input CDR_NEXT_CLK on instance I_IOD_98_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:23:94:23|Input RX_P on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG781 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_IOD_CDR_TX_0\PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v":94:32:94:32|Input RX_N on instance I_IOD_0 is undriven; assigning to 0.  Simulation mismatch possible. Either assign the input or remove the declaration. 
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_C0\PF_LANECTRL_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":47:27:47:36|Type of parameter INTERFACE_LEVEL on the instance dll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_CCC_0\PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v":87:27:87:36|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG360 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\PF_IOD_CDR_CCC_C0\PF_LANECTRL_CORE_READER_0\PF_LANECTRL_PAUSE_SYNC.v":21:6:21:19|Removing wire pause_sync_0_i, as there is no assignment to it.
@W: CL156 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":319:13:319:29|*Input APB_MSTR_PRDATA_P[3:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\MIV_RV32_C0\MIV_RV32_C0_0\miv_rv32.v":465:45:465:67|*Input tcm1_dap_access_disable to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL279 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9303:2:9303:7|Pruning register bits 3 to 1 of cpu_d_req_wr_byte_en_int[3:0]. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9075:48:9075:61|Input port bits 31 to 16 of cpu_i_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9075:48:9075:61|Input port bits 1 to 0 of cpu_i_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9088:48:9088:61|Input port bits 31 to 16 of cpu_d_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":9088:48:9088:61|Input port bits 1 to 0 of cpu_d_req_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7098:49:7098:71|Input port bits 11 to 0 of cfg_apb_mstr_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7099:49:7099:69|Input port bits 11 to 0 of cfg_apb_mstr_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7104:49:7104:72|Input port bits 11 to 0 of cfg_opsrv_cfg_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7105:49:7105:70|Input port bits 11 to 0 of cfg_opsrv_cfg_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7106:49:7106:67|Input port bits 11 to 0 of cfg_tcm0_start_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":7107:49:7107:65|Input port bits 11 to 0 of cfg_tcm0_end_addr[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":13201:49:13201:71|Input port bits 3 to 1 of cpu_regs_req_wr_byte_en[3:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\opsrv_merged\miv_rv32_opsrv_merged.v":13206:49:13206:68|Input port bits 31 to 2 of cpu_regs_req_wr_data[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":1738:60:1738:72|Input port bit 1 of excpt_trigger[1:0] is unused
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":6537:43:6537:44|Input port bits 23 to 12 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":6537:43:6537:44|Input port bits 10 to 8 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":6537:43:6537:44|Input port bits 6 to 4 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":6537:43:6537:44|Input port bits 2 to 0 of ie[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Pruning register bit 3 of gen_req_buff_loop[1].req_buff_resp_fault[1][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Pruning register bit 3 of gen_req_buff_loop[0].req_buff_resp_fault[0][3:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Optimizing register bit gen_req_buff_loop[0].req_buff_resp_fault[0][1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Optimizing register bit gen_req_buff_loop[1].req_buff_resp_fault[1][1] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Pruning register bit 1 of gen_req_buff_loop[0].req_buff_resp_fault[0][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Microsemi\MiV\MIV_RV32\3.0.100\core_merged\miv_rv32_core_merged.v":16782:4:16782:9|Pruning register bit 1 of gen_req_buff_loop[1].req_buff_resp_fault[1][2:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CoreUARTapb_0\CoreUARTapb_0_0\rtl\vlog\core_obfuscated\CoreUARTapb.v":126:0:126:4|Input port bits 1 to 0 of PADDR[4:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":333:0:333:5|Sharing sequential element CORETSEioOI. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL177 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petcr.v":436:0:436:5|Sharing sequential element CORETSEiOII. Add a syn_preserve attribute to the element to prevent sharing.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petbm.v":714:0:714:5|Optimizing register bit CORETSEIi1o[5] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petbm.v":714:0:714:5|Pruning register bit 5 of CORETSEIi1o[5:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":113:0:113:10|Input port bit 14 of CORETSEo0o0[15:0] is unused
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\msgmii_peanx_top.v":113:0:113:10|Input port bit 11 of CORETSEo0o0[15:0] is unused
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_eim.v":156:0:156:10|Input port bits 24 to 20 of CORETSEo1Oo[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_store.v":181:0:181:10|Input port bit 31 of CORETSEOllo[31:0] is unused
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sincnf.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sadd.v":54:0:54:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sinchd.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_sinc.v":44:0:44:10|Input port bits 30 to 12 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_ladd.v":54:0:54:10|Input port bits 30 to 24 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_linc.v":44:0:44:10|Input port bits 30 to 18 of CORETSEOllo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":51:0:51:8|Input port bit 22 of CORETSEoo[30:0] is unused
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":51:0:51:8|Input port bits 17 to 16 of CORETSEoo[30:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":62:0:62:10|Input port bits 31 to 30 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\pemstat_cntrl.v":62:0:62:10|Input port bits 23 to 21 of CORETSEoIoI[51:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":180:0:180:11|Input port bits 31 to 10 of CORETSEl00lI[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\tsmac_top.v":180:0:180:11|Input port bits 1 to 0 of CORETSEl00lI[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\permc_top.v":98:0:98:8|Input port bit 0 of CORETSEiI[1:0] is unused
@W: CL138 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":3490:0:3490:5|Removing register 'CORETSEOo' because it is only assigned 0 or its original value.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\perfn_top.v":147:0:147:8|Input port bits 1 to 0 of CORETSEil[7:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":219:0:219:10|Input port bits 1 to 0 of CORETSEil1I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":221:0:221:10|Input port bits 1 to 0 of CORETSEO01I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":223:0:223:10|Input port bits 1 to 0 of CORETSEI01I[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petfn_top.v":231:0:231:10|Input port bits 9 to 6 of CORETSEl01I[9:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\petmc_top.v":113:0:113:8|Input port bit 0 of CORETSEiI[1:0] is unused
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_sys.v":239:0:239:10|Input port bits 39 to 36 of CORETSEoIii[39:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL247 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\amcxrfif_fab.v":128:0:128:10|Input port bit 12 of CORETSEiIii[13:0] is unused
@W: CL156 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v":203:0:203:11|*Input CORETSElioOI[31:0] to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL156 :"F:\DG0799_final\Libero_Project\Libero_Project\component\work\CORETSE_0\CORETSE_0_0\rtl\vlog\obfuscated\mapbe_hst_cnv.v":206:0:206:11|*Input CORETSEoioOI to expression [instance] has undriven bits; assigning undriven bits to 0.  Simulation mismatch possible. Assign all bits of the input.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi.v":70:12:70:16|Input port bits 1 to 0 of PADDR[6:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL190 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Optimizing register bit stxs_bitsel[4] to a constant 0. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL260 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_chanctrl.v":823:0:823:5|Pruning register bit 4 of stxs_bitsel[4:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CORESPI\5.2.104\rtl\vlog\core\spi_rf.v":42:45:42:50|Input port bits 31 to 8 of wrdata[31:0] are unused. Assign logic for all port bits or change the input port size.
@W: CL246 :"F:\DG0799_final\Libero_Project\Libero_Project\component\Actel\DirectCore\CoreAPB3\4.2.100\rtl\vlog\core\coreapb3.v":75:18:75:22|Input port bits 27 to 16 of PADDR[31:0] are unused. Assign logic for all port bits or change the input port size.

