#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file F:\DG0799_final\Libero_Project\Libero_Project\synthesis\run_options.txt
#--  Written on Thu Feb 25 12:40:26 2021


#project files
add_file -verilog "../component/polarfire_syn_comps.v"
add_file -include "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/include.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_clockmux.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_chanctrl.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_fifo.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_rf.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi_control.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/spi.v"
add_file -verilog -lib CORESPI_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORESPI/5.2.104/rtl/vlog/core/corespi.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORESPI_0/CORESPI_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/rx4096x36.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_clkrst.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_cnvrxi.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_cnvrxo.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_cnvtxi.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_cnvtxo.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/petcr.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/peanx_sync.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_peanx_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/r10b8b.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/perex_pcs.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/perex_pma.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/petbm.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/t8b10b.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/petex_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_tbi.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/msgmii_core.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxfif_clkrst.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxfif_hst.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxrfif_fab.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxrfif_sys.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxtfif_fab.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxtfif_sys.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxtfif_wtm.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/amcxfif.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/decoder.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/tsm_sysreg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/mapbe_hst_cnv.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/mmcxwol.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_cntrl.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_eim.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_ladd.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_linc.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_sadd.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_sinchd.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_sincnf.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_sinc.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat_store.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemstat.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pecar.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pehst.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pemgt.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pecrc.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/perfn_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/permc_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/petfn_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/petmc_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pe_mcxmac_core.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/pe_mcxmac.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/sib_sync_2flp.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/sib_sync_pulse.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/si_sal.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/tsmac_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/tx2048x40.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/CoreTSE_top.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0_0/rtl/vlog/obfuscated/CoreTSE.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CORETSE_0/CORETSE_0.v"
add_file -verilog -lib COREAPB3_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_muxptob3.v"
add_file -verilog -lib COREAPB3_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3_iaddr_reg.v"
add_file -verilog -lib COREAPB3_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CoreAPB3/4.2.100/rtl/vlog/core/coreapb3.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreAPB3_0/CoreAPB3_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Clock_gen.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Rx_async.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/Tx_async.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/fifo_256x8_g5.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/CoreUART.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0_0/rtl/vlog/core_obfuscated/CoreUARTapb.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/CoreUARTapb_0/CoreUARTapb_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/Core_reset_pf/Core_reset_pf_0/core/corereset_pf.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/Core_reset_pf/Core_reset_pf.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_mnemonics_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_core_cfg_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_bist_shared_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_bist_seq_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/core_merged/miv_rv32_core_merged.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_opsrv_debug_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_opsrv_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/miv_rv32_opsrv_cfg_pkg.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/opsrv_merged/miv_rv32_opsrv_merged.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/opsrv/miv_rv32_ram_singleport_lp.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Microsemi/MiV/MIV_RV32/3.0.100/opsrv/miv_rv32_ram_singleport_lp_ecc.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/MIV_RV32_C0/MIV_RV32_C0_0/miv_rv32.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/MIV_RV32_C0/MIV_RV32_C0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_CCC_0/PF_CCC_0_0/PF_CCC_0_PF_CCC_0_0_PF_CCC.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_CCC_0/PF_CCC_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/CORECDR4_CNTL_TIP/2.0.100/rtl/vlog/core/corecdr4_cntl_tip.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_LANECTRL_OVERLAY_0/PF_IOD_CDR_C0_PF_IOD_CDR_LANECTRL_OVERLAY_0_PF_IOD.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_N_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_N_0_PF_IOD.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_RX_P_0/PF_IOD_CDR_C0_PF_IOD_CDR_RX_P_0_PF_IOD.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_TX_0/PF_IOD_CDR_C0_PF_IOD_CDR_TX_0_PF_IOD.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_LANECTRL_0/PF_IOD_CDR_C0_PF_LANECTRL_0_PF_LANECTRL.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_C0/PF_IOD_CDR_C0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/COREDELAYCODE_TIP/2.1.100/rtl/vlog/core/CoreDelayCode_TIP.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_CCC_0/PF_IOD_CDR_CCC_C0_PF_CCC_0_PF_CCC.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_CLK_DIV_0/PF_IOD_CDR_CCC_C0_PF_CLK_DIV_0_PF_CLK_DIV.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_LANECTRL_PAUSE_SYNC.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_LANECTRL_CORE_READER_0/PF_IOD_CDR_CCC_C0_PF_LANECTRL_CORE_READER_0_PF_LANECTRL.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/PF_IOD_CDR_CCC_C0/PF_IOD_CDR_CCC_C0.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/3.1.100/core/corejtagdebug_ujtag_wrapper.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/3.1.100/core/corejtagdebug_bufd.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/3.1.100/core/corejtagdebug_uj_jtag.v"
add_file -verilog -lib COREJTAGDEBUG_LIB "F:/DG0799_final/Libero_Project/Libero_Project/component/Actel/DirectCore/COREJTAGDEBUG/3.1.100/core/corejtagdebug.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/core_jatg_debug_0/core_jatg_debug_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/pf_init_monitor_0/pf_init_monitor_0_0/pf_init_monitor_0_pf_init_monitor_0_0_PF_INIT_MONITOR.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/pf_init_monitor_0/pf_init_monitor_0.v"
add_file -verilog "F:/DG0799_final/Libero_Project/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "F:/DG0799_final/Libero_Project/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
