Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Thu Feb 25 15:47:28 2021

Design top
Family PolarFire
Die MPF300TS
Package FCG1152
Temperature Range -40 - 100 C
Voltage Range 1.0185 - 1.0815 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions slow_lv_ht, slow_lv_lt, fast_hv_lt
Scenario for Timing Analysis timing_analysis

*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q N/A N/A
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 12.500 80.000 2.550 slow_lv_ht
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK N/A N/A
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 1.600 625.000
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 1.600 625.000
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 1.600 625.000
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 1.600 625.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 8.000 125.000 3.430 slow_lv_ht
PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q N/A N/A
REFCLK_P 8.000 125.000
REF_CLK_0 20.000 50.000
TCK 100.000 10.000 38.249 slow_lv_ht
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 8.000 125.000 2.137 slow_lv_ht
PHY_MDC_CLOCK 350.000 2.857

Worst Slack (ns) Operating Conditions
Input to Output slow_lv_ht

Clock Domain CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[0]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:D 3.537 7.009 0.000 3.605 slow_lv_ht
Path 2 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEIi1o[2]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[15]:D 3.517 6.976 0.000 3.591 slow_lv_ht
Path 3 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[2]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:D 3.521 6.993 0.000 3.589 slow_lv_ht
Path 4 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEIi1o[3]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[15]:D 3.475 6.933 0.000 3.548 slow_lv_ht
Path 5 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEIi1o[0]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[15]:D 3.393 6.851 0.000 3.466 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[0]:CLK
To: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:D
data required time N/C
data arrival time - 7.009
slack N/C
Data arrival time calculation
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q 0.000 0.000
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q Clock source + 0.000 0.000 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3592:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEI110 + 2.376 2.376 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3592:Y cell ADLIB:GB + 0.115 2.491 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_Y + 0.365 2.856 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.052 2.908 124 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[0]:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0_rgb_net_1 + 0.564 3.472 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo[0]:Q cell ADLIB:SLE + 0.166 3.638 3 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE_1:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEoOoo_Z[0] + 0.162 3.800 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE_1:Y cell ADLIB:CFG2 + 0.078 3.878 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE:B net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE_1_Z + 0.126 4.004 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE:Y cell ADLIB:CFG4 + 0.136 4.140 16 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSElioo:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/un5_CORETSEoo10_NE_Z + 0.611 4.751 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSElioo:Y cell ADLIB:CFG4 + 0.240 4.991 16 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_2[2]:C net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSElioo_Z_net_20 + 0.487 5.478 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_2[2]:Y cell ADLIB:CFG4 + 0.140 5.618 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_4[2]:B net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_2_Z[2] + 0.223 5.841 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_4[2]:Y cell ADLIB:CFG4 + 0.048 5.889 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo[2]:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_4_Z[2] + 0.387 6.276 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo[2]:Y cell ADLIB:CFG4 + 0.048 6.324 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEo0oo[2]:B net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEl0oo_Z[2] + 0.454 6.778 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEo0oo[2]:Y cell ADLIB:CFG4 + 0.204 6.982 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:D net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEo0oo_Z[2] + 0.027 7.009 r
data arrival time 7.009
Data required time calculation
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q N/C N/C
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q Clock source + 0.000 N/C r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3592:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEI110 + 1.921 N/C r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3592:Y cell ADLIB:GB + 0.105 N/C 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_Y + 0.331 N/C r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.047 N/C 124 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3592/U0_RGB1_RGB0_rgb_net_1 + 0.496 N/C r
clock reconvergence pessimism + 0.504 N/C
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiOi0/CORETSEi0oo[2]:D Library setup time ADLIB:SLE - 0.000 N/C
Operating Conditions slow_lv_ht

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q

No Path

Clock Domain PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0/INST_RAM1K20_IP:A_CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D 9.710 2.550 13.049 15.599 0.000 9.950 slow_lv_ht
Path 2 MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R26C0/INST_RAM1K20_IP:A_CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D 9.610 2.607 12.958 15.565 0.000 9.893 slow_lv_ht
Path 3 MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R25C0/INST_RAM1K20_IP:A_CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D 9.634 2.621 12.978 15.599 0.000 9.879 slow_lv_ht
Path 4 MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R27C0/INST_RAM1K20_IP:A_CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D 9.481 2.740 12.825 15.565 0.000 9.760 slow_lv_ht
Path 5 MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_operand1_mux_sel_ex[1]:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_branch_cond_ex[0]:EN 9.588 2.749 12.742 15.491 0.121 9.751 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0/INST_RAM1K20_IP:A_CLK
To: MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D
data required time 15.599
data arrival time - 13.049
slack 2.550
Data arrival time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 0.000 0.000
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.153 1.695 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.377 2.072 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.151 2.223 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.363 2.586 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 2.638 582 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0/INST_RAM1K20_IP:A_CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.701 3.339 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0/INST_RAM1K20_IP:B_DOUT[0] cell ADLIB:RAM1K20_IP + 1.872 5.211 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_31:A net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0_B_DOUT[0] + 0.934 6.145 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_31:Y cell ADLIB:CFG4 + 0.204 6.349 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1019:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_31_Y + 0.537 6.886 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1019:Y cell ADLIB:CFG4 + 0.066 6.952 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1080:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1019_Y + 0.354 7.306 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1080:Y cell ADLIB:CFG4 + 0.066 7.372 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[0]:A net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_1080_Y + 0.076 7.448 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/OR4_R_DATA[0]:Y cell ADLIB:CFG4 + 0.066 7.514 3 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_opsrv_interconnect_0/cpu_i_resp_rd_data[0]:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/tcm0_d_resp_rd_data_net[0] + 0.072 7.586 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_opsrv_interconnect_0/cpu_i_resp_rd_data[0]:Y cell ADLIB:CFG4 + 0.066 7.652 7 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNI6DB52[2]:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/cpu_i_resp_rd_data_net[0] + 0.425 8.077 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNI6DB52[2]:Y cell ADLIB:CFG4 + 0.048 8.125 5 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNIKE9A3[2]:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/emi_resp_head_uncompressed_full + 0.120 8.245 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNIKE9A3[2]:Y cell ADLIB:CFG4 + 0.048 8.293 15 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNI1J2E7[2]:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/N_725 + 0.430 8.723 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[2].buff_entry_hword_high_only_req_RNI1J2E7[2]:Y cell ADLIB:CFG4 + 0.140 8.863 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2__RNI83DIL[3]:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/m423_i_0 + 0.111 8.974 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/gen_buff_loop[0].buff_entry_data_resp.gen_buff_loop[0].buff_entry_data_resp_ram2__RNI83DIL[3]:Y cell ADLIB:CFG4 + 0.048 9.022 15 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3470_0_a2_0_1:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/de_ex_pipe_curr_instr_enc_ex_2[3] + 0.520 9.542 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3470_0_a2_0_1:Y cell ADLIB:CFG3 + 0.061 9.603 1 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3470_0_a2_0:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/rv32i_dec_mnemonic3470_0_a2_0_1 + 0.122 9.725 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3470_0_a2_0:Y cell ADLIB:CFG4 + 0.061 9.786 8 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3471_0_a2:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_689 + 0.487 10.273 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3471_0_a2:Y cell ADLIB:CFG4 + 0.047 10.320 3 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3474_0_a2_RNIG3H8A8:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/rv32i_dec_mnemonic3471 + 0.206 10.526 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3474_0_a2_RNIG3H8A8:Y cell ADLIB:CFG3 + 0.083 10.609 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8:A net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/rv32i_dec_mnemonic3474_0_a2_RNIG3H8A8 + 0.117 10.726 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/gen_decode_rv32i.rv32i_dec_mnemonic3463_0_a2_RNI1Q2FC8:Y cell ADLIB:CFG4 + 0.140 10.866 14 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_4_0_m2:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_298_i + 0.515 11.381 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_4_0_m2:Y cell ADLIB:CFG3 + 0.111 11.492 2 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_9_i_o2cf1:C net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_1427 + 0.083 11.575 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_9_i_o2cf1:Y cell ADLIB:CFG4 + 0.061 11.636 2 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_9_i_o2:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_9_i_o2cf1_Z + 0.318 11.954 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_9_i_o2:Y cell ADLIB:CFG2 + 0.066 12.020 3 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_2_2:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_1460 + 0.344 12.364 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_2_2:Y cell ADLIB:CFG4 + 0.046 12.410 1 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_2:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_2_2_Z + 0.056 12.466 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_2:Y cell ADLIB:CFG3 + 0.078 12.544 1 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_0_RNICKE8J5:B net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_456 + 0.304 12.848 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_0_RNICKE8J5:Y cell ADLIB:CFG4 + 0.045 12.893 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J:A net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/N_1273_i_1 + 0.053 12.946 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/u_idecode_0/de_ex_pipe_illegal_instr_ex_2_i_a2_6_3_RNIL1BM0J:Y cell ADLIB:CFG4 + 0.081 13.027 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/N_1273_i + 0.022 13.049 r
data arrival time 13.049
Data required time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 Clock Constraint 12.500 12.500
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 12.500 r
Clock generation + 1.254 13.754
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.144 13.898 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.132 14.030 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.343 14.373 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.138 14.511 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.329 14.840 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.047 14.887 582 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.461 15.348 r
clock reconvergence pessimism + 0.251 15.599
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/de_ex_pipe_illegal_instr_ex:D Library setup time ADLIB:SLE - 0.000 15.599
data required time 15.599
Operating Conditions slow_lv_ht

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 SPISDI CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0]:D 7.224 7.224 0.000 4.351 slow_lv_ht
Path 2 SPISDI CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_shiftreg[0]:D 6.851 6.851 0.000 3.985 slow_lv_ht
Path 3 SPISDI CORESPI_0_0/CORESPI_0_0/USPI/UCC/data_rx_q1:D 6.773 6.773 0.000 3.919 slow_lv_ht
Path 4 RX CoreUARTapb_0_inst_0/CoreUARTapb_0_0/CUARTlOlI/CUARTO01/CUARTI1Il[2]:D 6.216 6.216 0.000 3.361 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: SPISDI
To: CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0]:D
data required time N/C
data arrival time - 7.224
slack N/C
Data arrival time calculation
SPISDI 0.000 0.000 f
SPISDI_ibuf/U_IOPAD:PAD net SPISDI + 0.000 0.000 f
SPISDI_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.733 0.733 1 f
SPISDI_ibuf/U_IOIN:YIN net SPISDI_ibuf/YIN + 0.000 0.733 f
SPISDI_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.338 1.071 2 f
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_di_mux:A net SPISDI_c + 5.678 6.749 f
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_di_mux:Y cell ADLIB:CFG3 + 0.078 6.827 2 f
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0]:D net CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_di_mux_Z + 0.397 7.224 f
data arrival time 7.224
Data required time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 N/C N/C
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.144 N/C r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.132 N/C 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.343 N/C r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.138 N/C 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.328 N/C r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:Y cell ADLIB:RGB + 0.047 N/C 926 f
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0]:CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 + 0.487 N/C r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/msrxs_datain[0]:D Library setup time ADLIB:SLE - 0.000 N/C
Operating Conditions slow_lv_ht

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct:CLK SPISDO 9.426 12.608 12.608 slow_lv_ht
Path 2 CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_datareg[15]:CLK SPISDO 9.342 12.523 12.523 slow_lv_ht
Path 3 CORESPI_0_0/CORESPI_0_0/USPI/UCC/txfifo_datadelay[15]:CLK SPISDO 9.338 12.520 12.520 slow_lv_ht
Path 4 CORESPI_0_0/CORESPI_0_0/USPI/UCC/mtx_spi_data_out:CLK SPISDO 9.051 12.229 12.229 slow_lv_ht
Path 5 CORESPI_0_0/CORESPI_0_0/USPI/URF/control1[1]:CLK SPISDO 9.049 12.221 12.221 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct:CLK
To: SPISDO
data required time N/C
data arrival time - 12.608
slack N/C
Data arrival time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 0.000 0.000
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.153 1.695 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.377 2.072 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.151 2.223 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.364 2.587 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:Y cell ADLIB:RGB + 0.052 2.639 926 f
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct:CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 + 0.543 3.182 r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct:Q cell ADLIB:SLE + 0.179 3.361 3 r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_1_0:B net CORESPI_0_0/CORESPI_0_0/USPI/UCC/stxs_direct_Z + 0.249 3.610 r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_1_0:Y cell ADLIB:CFG3 + 0.105 3.715 1 r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u:B net CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u_1_0_Z + 0.341 4.056 r
CORESPI_0_0/CORESPI_0_0/USPI/UCC/spi_data_out_u:Y cell ADLIB:CFG4 + 0.132 4.188 1 f
SPISDO_obuf/U_IOTRI:D net SPISDO_c + 5.468 9.656 f
SPISDO_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.918 10.574 1 f
SPISDO_obuf/U_IOPAD:D net SPISDO_obuf/DOUT + 0.000 10.574 f
SPISDO_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.034 12.608 0 f
SPISDO net SPISDO + 0.000 12.608 f
data arrival time 12.608
Data required time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 N/C N/C
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
SPISDO N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:ALn 4.016 8.177 7.210 15.387 0.183 4.323 0.124 slow_lv_ht
Path 2 Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_resp_rd_ptr[0]:ALn 4.016 8.177 7.210 15.387 0.183 4.323 0.124 slow_lv_ht
Path 3 Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/buff_req_rd_ptr_Z[0]:ALn 4.016 8.177 7.210 15.387 0.183 4.323 0.124 slow_lv_ht
Path 4 Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_apb_mstr.u_apb_master_0/u_apb_mstr_req_arb/sel_reg[0]:ALn 4.006 8.178 7.200 15.378 0.183 4.322 0.133 slow_lv_ht
Path 5 Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_apb_mstr.u_apb_master_0/u_apb_mstr_req_arb/hipri_req_ptr[0]:ALn 4.006 8.178 7.200 15.378 0.183 4.322 0.133 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK
To: MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:ALn
data required time 15.387
data arrival time - 7.210
slack 8.177
Data arrival time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 0.000 0.000
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.153 1.695 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.377 2.072 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.151 2.223 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.364 2.587 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1:Y cell ADLIB:RGB + 0.052 2.639 926 f
Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB1_rgb_net_1 + 0.555 3.194 r
Core_reset_pf_0/Core_reset_pf_0/dff_15_rep:Q cell ADLIB:SLE + 0.175 3.369 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3591:A net Core_reset_pf_0.Core_reset_pf_0.dff_15_rep + 2.769 6.138 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3591:Y cell ADLIB:GB + 0.112 6.250 6 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3591/U0_RGB1_RGB4:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3591/U0_Y + 0.360 6.610 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3591/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 6.662 11 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:ALn net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3591/U0_RGB1_RGB4_rgb_net_1 + 0.548 7.210 r
data arrival time 7.210
Data required time calculation
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 Clock Constraint 12.500 12.500
PF_CCC_0_0/PF_CCC_0_0/pll_inst_0:OUT0 Clock source + 0.000 12.500 r
Clock generation + 1.254 13.754
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:A net PF_CCC_0_0/PF_CCC_0_0/pll_inst_0_clkint_0 + 0.144 13.898 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.132 14.030 1 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0_NET + 0.343 14.373 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0:Y cell ADLIB:GB + 0.138 14.511 8 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5:A net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_Y + 0.330 14.841 r
PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5:Y cell ADLIB:RGB + 0.047 14.888 339 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:CLK net PF_CCC_0_0/PF_CCC_0_0/clkint_0/U0_RGB1_RGB5_rgb_net_1 + 0.470 15.358 r
clock reconvergence pessimism + 0.212 15.570
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_fetch_unit_0/u_miv_rv32_ifu_iab_0/req_count[1]:ALn Library recovery time ADLIB:SLE - 0.183 15.387
data required time 15.387
Operating Conditions slow_lv_ht

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET TCK to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET REF_CLK_0 to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

SET PHY_MDC_CLOCK to PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0

No Path

Clock Domain PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:CDR_CLK

SET Register to Register

No Path

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX_P PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P 0.579 0.579 1.606 2.185 slow_lv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX_P
To: PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P
data required time N/C
data arrival time - 0.579
slack N/C
Data arrival time calculation
RX_P 0.000 0.000 f
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/U_IOPADP:PAD net RX_P + 0.000 0.000 f
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/U_IOPADP:Y cell ADLIB:IOPADP_IN + 0.579 0.579 2 f
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P net PF_IOD_CDR_C0_0/IB_DIFF_CDR_0_Y + 0.000 0.579 f
data arrival time 0.579
Data required time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK N/C N/C
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CDR_CLK Clock source + 0.000 N/C f
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:CDR_CLK net CDR_CLK + 0.000 N/C f
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P Library setup time ADLIB:IOD - 1.606 N/C
Operating Conditions slow_lv_lt

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0:HS_IO_CLK[0] TX_P 3.023 4.975 4.975 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0:HS_IO_CLK[0]
To: TX_P
data required time N/C
data arrival time - 4.975
slack N/C
Data arrival time calculation
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 0.000 0.000
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.426 1.426
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_3:A net PF_IOD_CDR_CCC_C0_0/PF_CCC_0_OUT0_0 + 0.114 1.540 r
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/hs_io_clk_3:Y cell ADLIB:HS_IO_CLK + 0.272 1.812 2 r
PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0:HS_IO_CLK[0] net Y + 0.140 1.952 r
PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0:TX cell ADLIB:IOD + 0.815 2.767 1 r
PF_IOD_CDR_C0_0/OB_DIFF_CDR_0/U_IOPADP:D net PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0_TX_0 + 0.000 2.767 r
PF_IOD_CDR_C0_0/OB_DIFF_CDR_0/U_IOPADP:PAD cell ADLIB:IOPADP_TRI + 2.208 4.975 0 r
TX_P net TX_P + 0.000 4.975 r
data arrival time 4.975
Data required time calculation
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 N/C N/C
PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.292 N/C
TX_P N/C r
Operating Conditions slow_lv_ht

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEOOi0/CORETSEooiII:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:D 4.432 3.430 8.317 11.747 0.000 4.570 slow_lv_ht
Path 2 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEl0ii/CORETSEOI1OI[2]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEl0ii/genblk5.CORETSEiIoi[1]:D 3.273 4.643 7.166 11.809 0.000 3.357 slow_lv_ht
Path 3 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEIOOl[1]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEi0iI:D 3.301 4.649 7.169 11.818 0.000 3.351 slow_lv_ht
Path 4 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEi0iI:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEi0iI:D 3.319 4.681 7.199 11.880 0.000 3.319 slow_lv_ht
Path 5 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEIoI1/CORETSEo11l[4]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEIoI1/CORETSEIO1l_Z[7]:D 3.225 4.689 7.121 11.810 0.000 3.311 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEOOi0/CORETSEooiII:CLK
To: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:D
data required time 11.747
data arrival time - 8.317
slack 3.430
Data arrival time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 0.000 0.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 0.000 r
Clock generation + 2.296 2.296
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:A net Y_DIV + 0.000 2.296 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:Y cell ADLIB:ICB_CLKINT + 0.135 2.431 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_NET + 0.347 2.778 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:Y cell ADLIB:GB + 0.154 2.932 4 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB2:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_Y + 0.358 3.290 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB2:Y cell ADLIB:RGB + 0.052 3.342 68 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEOOi0/CORETSEooiII:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB2_rgb_net_1 + 0.543 3.885 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEOOi0/CORETSEooiII:Q cell ADLIB:SLE + 0.179 4.064 8 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII_r[8]:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEli10[8] + 4.156 8.220 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII_r[8]:Y cell ADLIB:CFG2 + 0.066 8.286 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:D net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII + 0.031 8.317 r
data arrival time 8.317
Data required time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV Clock Constraint 8.000 8.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 8.000 r
Clock generation + 2.059 10.059
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:A net Y_DIV + 0.000 10.059 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:Y cell ADLIB:ICB_CLKINT + 0.117 10.176 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_GB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_NET + 0.316 10.492 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_GB0:Y cell ADLIB:GB + 0.140 10.632 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_gbs_1 + 0.335 10.967 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3:Y cell ADLIB:RGB + 0.047 11.014 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3_rgb_net_1 + 0.447 11.461 r
clock reconvergence pessimism + 0.286 11.747
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:D Library setup time ADLIB:SLE - 0.000 11.747
data required time 11.747
Operating Conditions slow_lv_ht

SET External Setup

No Path

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:CLK LINK_OK 6.498 10.361 10.361 slow_lv_ht
Path 2 PF_IOD_CDR_C0_0/PF_IOD_CDR_TX_0/I_IOD_0:TX_CLK TX_P 2.939 7.090 7.090 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:CLK
To: LINK_OK
data required time N/C
data arrival time - 10.361
slack N/C
Data arrival time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 0.000 0.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 0.000 r
Clock generation + 2.296 2.296
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:A net Y_DIV + 0.000 2.296 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:Y cell ADLIB:ICB_CLKINT + 0.135 2.431 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_GB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_NET + 0.347 2.778 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_GB0:Y cell ADLIB:GB + 0.154 2.932 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_gbs_1 + 0.371 3.303 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3:Y cell ADLIB:RGB + 0.052 3.355 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB3_rgb_net_1 + 0.508 3.863 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEiOiII[8]:Q cell ADLIB:SLE + 0.170 4.033 1 f
LINK_OK_obuf/U_IOTRI:D net LINK_OK_c + 3.376 7.409 f
LINK_OK_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.918 8.327 1 f
LINK_OK_obuf/U_IOPAD:D net LINK_OK_obuf/DOUT + 0.000 8.327 f
LINK_OK_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.034 10.361 0 f
LINK_OK net LINK_OK + 0.000 10.361 f
data arrival time 10.361
Data required time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV N/C N/C
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 N/C r
Clock generation + 2.059 N/C
LINK_OK N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEolOl:ALn 1.911 5.853 5.790 11.643 0.170 2.147 0.066 slow_lv_ht
Path 2 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEIOiI:ALn 1.911 5.853 5.790 11.643 0.170 2.147 0.066 slow_lv_ht
Path 3 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEoill:ALn 1.861 5.902 5.740 11.642 0.170 2.098 0.067 slow_lv_ht
Path 4 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEiill:ALn 1.861 5.902 5.740 11.642 0.170 2.098 0.067 slow_lv_ht
Path 5 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEI10l:ALn 1.861 5.902 5.740 11.642 0.170 2.098 0.067 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK
To: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEolOl:ALn
data required time 11.643
data arrival time - 5.790
slack 5.853
Data arrival time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV 0.000 0.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 0.000 r
Clock generation + 2.296 2.296
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:A net Y_DIV + 0.000 2.296 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:Y cell ADLIB:ICB_CLKINT + 0.135 2.431 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_NET + 0.347 2.778 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:Y cell ADLIB:GB + 0.154 2.932 4 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_Y + 0.369 3.301 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.052 3.353 548 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0_rgb_net_1 + 0.526 3.879 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01:Q cell ADLIB:SLE + 0.166 4.045 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEIO01:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEOO01_Z + 0.056 4.101 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEilI1/CORETSEIO01:Y cell ADLIB:CFG4 + 0.206 4.307 321 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEolOl:ALn net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEIO01_i + 1.483 5.790 r
data arrival time 5.790
Data required time calculation
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV Clock Constraint 8.000 8.000
PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD:Y_DIV Clock source + 0.000 8.000 r
Clock generation + 2.059 10.059
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:A net Y_DIV + 0.000 10.059 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_1:Y cell ADLIB:ICB_CLKINT + 0.117 10.176 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590_NET + 0.316 10.492 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3590:Y cell ADLIB:GB + 0.140 10.632 4 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_Y + 0.332 10.964 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.047 11.011 548 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEolOl:CLK net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3590/U0_RGB1_RGB0_rgb_net_1 + 0.460 11.471 r
clock reconvergence pessimism + 0.342 11.813
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEloI1/CORETSEolOl:ALn Library recovery time ADLIB:SLE - 0.170 11.643
data required time 11.643
Operating Conditions slow_lv_ht

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

SET PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R to PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV

No Path

Clock Domain PF_IOD_CDR_CCC_C0_0/PF_COREDELAYCODE_TIP_0/move_lane:Q

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_CCC_C0_0/PF_LANECTRL_CORE_READER_0/I_LANECTRL:DELAY_LINE_MOVE

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain REFCLK_P

Info: The maximum frequency of this clock domain is limited by the period of pin PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0:REF_CLK_0

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain REF_CLK_0

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin REF_CLK_0_ibuf/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Clock Domain TCK

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:D 18.514 38.249 18.514 56.763 0.000 23.502 slow_lv_ht
Path 2 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[12]:D 18.511 38.252 18.511 56.763 0.000 23.496 slow_lv_ht
Path 3 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[14]:D 18.509 38.254 18.509 56.763 0.000 23.492 slow_lv_ht
Path 4 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[1]:D 18.505 38.258 18.505 56.763 0.000 23.484 slow_lv_ht
Path 5 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[9]:D 18.503 38.260 18.503 56.763 0.000 23.480 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK
To: MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:D
data required time 56.763
data arrival time - 18.514
slack 38.249
Data arrival time calculation
TCK 0.000 0.000
TCK Clock source + 0.000 0.000 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK net TCK + 0.000 0.000 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:UTDI cell ADLIB:UJTAG_SEC + 8.220 8.220 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_UTDI:A net core_jatg_debug_0_0/core_jatg_debug_0_0/UTDIInt_UTDI + 1.761 9.981 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_UTDI:Y cell ADLIB:CFG1D + 0.204 10.185 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UTDI:A net core_jatg_debug_0_0/core_jatg_debug_0_0/UTDIInt_UTDI_2 + 0.260 10.445 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_UTDI:Y cell ADLIB:CFG1D + 0.204 10.649 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UTDI:A net core_jatg_debug_0_0/core_jatg_debug_0_0/UTDIInt_UTDI_3 + 0.157 10.806 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_UTDI:Y cell ADLIB:CFG1D + 0.204 11.010 8 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/dut_tms_int:B net core_jatg_debug_0_0/core_jatg_debug_0_0/UTDIInt + 0.471 11.481 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/dut_tms_int:Y cell ADLIB:CFG3 + 0.048 11.529 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[0].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/dut_tms_int_Z + 0.324 11.853 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[0].BUFD_BLK:Y cell ADLIB:CFG1 + 0.081 11.934 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[1].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[1] + 0.109 12.043 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[1].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 12.091 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[2].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[2] + 0.118 12.209 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[2].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 12.257 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[3].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[3] + 0.107 12.364 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[3].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 12.412 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[4].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[4] + 0.065 12.477 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[4].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 12.525 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[5].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[5] + 0.108 12.633 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[5].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 12.681 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[6].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[6] + 0.121 12.802 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[6].BUFD_BLK:Y cell ADLIB:CFG1 + 0.081 12.883 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[7].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[7] + 0.123 13.006 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[7].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.054 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[8].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[8] + 0.109 13.163 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[8].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.211 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[9].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[9] + 0.107 13.318 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[9].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.366 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[10].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[10] + 0.106 13.472 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[10].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.520 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[11].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[11] + 0.215 13.735 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[11].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.783 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[12].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[12] + 0.108 13.891 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[12].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 13.939 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[13].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[13] + 0.107 14.046 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[13].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.094 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[14].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[14] + 0.122 14.216 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[14].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.264 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[15].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[15] + 0.108 14.372 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[15].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.420 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[16].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[16] + 0.120 14.540 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[16].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.588 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[17].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[17] + 0.106 14.694 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[17].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.742 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[18].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[18] + 0.107 14.849 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[18].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 14.897 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[19].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[19] + 0.121 15.018 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[19].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 15.066 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[20].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[20] + 0.120 15.186 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[20].BUFD_BLK:Y cell ADLIB:CFG1 + 0.081 15.267 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[21].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[21] + 0.109 15.376 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[21].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 15.424 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[22].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[22] + 0.124 15.548 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[22].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 15.596 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[23].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[23] + 0.304 15.900 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[23].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 15.966 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[24].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[24] + 0.125 16.091 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[24].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 16.157 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[25].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[25] + 0.113 16.270 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[25].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 16.336 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[26].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[26] + 0.111 16.447 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[26].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 16.513 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[27].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[27] + 0.124 16.637 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[27].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 16.703 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[28].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[28] + 0.114 16.817 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[28].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 16.883 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[29].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[29] + 0.129 17.012 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[29].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 17.078 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[30].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[30] + 0.119 17.197 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[30].BUFD_BLK:Y cell ADLIB:CFG1 + 0.105 17.302 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[31].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[31] + 0.113 17.415 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[31].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 17.481 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[32].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[32] + 0.114 17.595 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[32].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 17.661 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[33].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/delay_sel[33] + 0.124 17.785 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/BUFD_TMS/bufd_gen[33].BUFD_BLK:Y cell ADLIB:CFG1 + 0.066 17.851 15 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[2]:C net core_jatg_debug_0_0_TGT_TMS_0 + 0.503 18.354 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState_RNO[2]:Y cell ADLIB:CFG4 + 0.140 18.494 1 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:D net MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/N_95_i + 0.020 18.514 r
data arrival time 18.514
Data required time calculation
TCK Clock Constraint 50.000 50.000
TCK Clock source + 0.000 50.000 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK net TCK + 0.000 50.000 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:UDRCK cell ADLIB:UJTAG_SEC + 1.698 51.698 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_1:A net iUDRCK + 0.143 51.841 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_1:Y cell ADLIB:ICB_CLKINT + 0.160 52.001 1 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3593:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_NET + 0.411 52.412 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3593:Y cell ADLIB:GB + 0.136 52.548 2 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_RGB1:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_Y + 0.326 52.874 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_RGB1:Y cell ADLIB:RGB + 0.047 52.921 9 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK_0:A net core_jatg_debug_0_0.core_jatg_debug_0_0.iUDRCK + 0.514 53.435 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK_0:Y cell ADLIB:CFG4 + 0.103 53.538 1 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB:A net core_jatg_debug_0_0/core_jatg_debug_0_0/un1_DUT_TCK + 2.261 55.799 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB:Y cell ADLIB:GB + 0.098 55.897 2 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y + 0.339 56.236 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.049 56.285 82 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:CLK net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0_rgb_net_1 + 0.478 56.763 r
clock reconvergence pessimism + 0.000 56.763
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/gen_current_state_register_active_high.gen_current_state_register_active_low.currTapState[2]:D Library setup time ADLIB:SLE - 0.000 56.763
data required time 56.763
Operating Conditions slow_lv_ht

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDMI_ne_0:ALn 12.527 44.301 12.527 56.828 0.183 11.398 -7.011 slow_lv_ht
Path 2 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDR_ne_0:ALn 12.526 44.302 12.526 56.828 0.183 11.396 -7.011 slow_lv_ht
Path 3 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftBP_ne_0:ALn 12.524 44.304 12.524 56.828 0.183 11.392 -7.011 slow_lv_ht
Path 4 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/ir_and_Instruction_register.gen_ir_and_Instruction_register_active_low.irReg[1]:ALn 12.278 44.578 12.278 56.856 0.170 10.844 -7.026 slow_lv_ht
Path 5 core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftIR_ne_0:ALn 12.278 44.579 12.278 56.857 0.170 10.842 -7.027 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK
To: MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDMI_ne_0:ALn
data required time 56.828
data arrival time - 12.527
slack 44.301
Data arrival time calculation
TCK 0.000 0.000
TCK Clock source + 0.000 0.000 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK net TCK + 0.000 0.000 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:URSTB cell ADLIB:UJTAG_SEC + 3.274 3.274 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_URSTB:A net core_jatg_debug_0_0/core_jatg_debug_0_0/iURSTB_URSTB + 1.527 4.801 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_URSTB:Y cell ADLIB:CFG1D + 0.185 4.986 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_URSTB:A net core_jatg_debug_0_0/core_jatg_debug_0_0/iURSTB_URSTB_2 + 0.264 5.250 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_2_URSTB:Y cell ADLIB:CFG1D + 0.185 5.435 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_URSTB:A net core_jatg_debug_0_0/core_jatg_debug_0_0/iURSTB_URSTB_3 + 0.152 5.587 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst_3_URSTB:Y cell ADLIB:CFG1D + 0.185 5.772 18 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[0].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/iURSTB + 0.111 5.883 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[0].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 5.931 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[1].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[1] + 0.120 6.051 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[1].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 6.099 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[2].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[2] + 0.109 6.208 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[2].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 6.256 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[3].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[3] + 0.106 6.362 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[3].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 6.410 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[4].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[4] + 0.305 6.715 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[4].BUFD_BLK:Y cell ADLIB:CFG1 + 0.140 6.855 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[5].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[5] + 0.121 6.976 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[5].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.024 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[6].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[6] + 0.106 7.130 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[6].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.178 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[7].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[7] + 0.108 7.286 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[7].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.334 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[8].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[8] + 0.124 7.458 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[8].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.506 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[9].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[9] + 0.122 7.628 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[9].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.676 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[10].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[10] + 0.109 7.785 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[10].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.833 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[11].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[11] + 0.106 7.939 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[11].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 7.987 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[12].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[12] + 0.119 8.106 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[12].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 8.154 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[13].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[13] + 0.109 8.263 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[13].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 8.311 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[14].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[14] + 0.065 8.376 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[14].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 8.424 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[15].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[15] + 0.109 8.533 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[15].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 8.581 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[16].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[16] + 0.291 8.872 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[16].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 8.920 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[17].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[17] + 0.120 9.040 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[17].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 9.088 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[18].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[18] + 0.052 9.140 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[18].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 9.188 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[19].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[19] + 0.065 9.253 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[19].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 9.301 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[20].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[20] + 0.109 9.410 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[20].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 9.458 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[21].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[21] + 0.106 9.564 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[21].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 9.612 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[22].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[22] + 0.608 10.220 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[22].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.268 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[23].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[23] + 0.121 10.389 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[23].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.437 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[24].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[24] + 0.121 10.558 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[24].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.606 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[25].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[25] + 0.055 10.661 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[25].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.709 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[26].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[26] + 0.065 10.774 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[26].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.822 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[27].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[27] + 0.108 10.930 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[27].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 10.978 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[28].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[28] + 0.111 11.089 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[28].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 11.137 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[29].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[29] + 0.118 11.255 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[29].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 11.303 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[30].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[30] + 0.109 11.412 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[30].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 11.460 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[31].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[31] + 0.107 11.567 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[31].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 11.615 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[32].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[32] + 0.120 11.735 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[32].BUFD_BLK:Y cell ADLIB:CFG1 + 0.048 11.783 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[33].BUFD_BLK:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/delay_sel[33] + 0.108 11.891 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk2.genblk2[0].BUFD_TRST/bufd_gen[33].BUFD_BLK:Y cell ADLIB:CFG1 + 0.081 11.972 109 r
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDMI_ne_0:ALn net core_jatg_debug_0_0.core_jatg_debug_0_0.genblk2.genblk2[0].BUFD_TRST.delay_sel[34] + 0.555 12.527 r
data arrival time 12.527
Data required time calculation
TCK Clock Constraint 50.000 50.000
TCK Clock source + 0.000 50.000 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:TCK net TCK + 0.000 50.000 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk1.genblk1.genblk1.UJTAG_inst:UDRCK cell ADLIB:UJTAG_SEC + 1.919 51.919 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_1:A net iUDRCK + 0.146 52.065 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_1:Y cell ADLIB:ICB_CLKINT + 0.180 52.245 1 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3593:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593_NET + 0.410 52.655 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/un3_CORETSEollOI_0_I_1_3593:Y cell ADLIB:GB + 0.129 52.784 2 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_RGB1:A net CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_Y + 0.334 53.118 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii_inst_1/un3_CORETSEollOI_0_I_1_3593/U0_RGB1:Y cell ADLIB:RGB + 0.049 53.167 9 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK_0:A net core_jatg_debug_0_0.core_jatg_debug_0_0.iUDRCK + 0.517 53.684 f
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.UJ_JTAG/un1_DUT_TCK_0:Y cell ADLIB:CFG4 + 0.097 53.781 1 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB:A net core_jatg_debug_0_0/core_jatg_debug_0_0/un1_DUT_TCK + 2.285 56.066 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB:Y cell ADLIB:GB + 0.105 56.171 2 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0:A net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_Y + 0.331 56.502 r
core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.047 56.549 82 f
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDMI_ne_0:CLK net core_jatg_debug_0_0/core_jatg_debug_0_0/genblk3.genblk1.TGT_TCK_GLB/U0_RGB1_RGB0_rgb_net_1 + 0.462 57.011 r
clock reconvergence pessimism + 0.000 57.011
MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_opsrv_debug.u_opsrv_debug_unit_0/MIV_opsrv_debug_transport_module_jtag_0/genblk3.gen_ir_and_Instruction_register_active_high.gen_ir_and_Instruction_register_active_low.shiftDMI_ne_0:ALn Library recovery time ADLIB:SLE - 0.183 56.828
data required time 56.828
Operating Conditions slow_lv_ht

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to TCK

No Path

Clock Domain PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[10]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:EN 0.433 2.569 1.594 4.163 0.112 1.578 slow_lv_ht
Path 2 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEOiI1/CORETSEoo_Z[28]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/CORETSElllOI[3]:EN 4.920 2.864 6.106 8.970 0.112 5.136 slow_lv_ht
Path 3 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEOiI1/CORETSEoo_Z[28]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/CORETSElllOI[4]:EN 4.937 2.881 6.123 9.004 0.112 5.119 slow_lv_ht
Path 4 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEOiI1/CORETSEoo_Z[28]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/CORETSElllOI[6]:EN 4.936 2.882 6.122 9.004 0.112 5.118 slow_lv_ht
Path 5 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEiOI1/CORETSEOiI1/CORETSEoo_Z[28]:CLK CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEooolI/CORETSEi0ii/CORETSElllOI[0]:EN 4.936 2.882 6.122 9.004 0.112 5.118 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[10]:CLK
To: PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:EN
data required time 4.163
data arrival time - 1.594
slack 2.569
Data arrival time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 0.000 0.000
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 0.000 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.562 0.562 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:Y cell ADLIB:RGB + 0.052 0.614 161 f
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[10]:CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2_rgb_net_1 + 0.547 1.161 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/SELA_LANE[10]:Q cell ADLIB:SLE + 0.175 1.336 4 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:EN net PF_IOD_CDR_C0_0/SELA_LANE_net_0[10] + 0.258 1.594 r
data arrival time 1.594
Data required time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R Clock Constraint 3.200 3.200
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 3.200 f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.456 3.656 f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:Y cell ADLIB:RGB + 0.049 3.705 161 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2_rgb_net_1 + 0.489 4.194 r
clock reconvergence pessimism + 0.081 4.275
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cdr_ready_reg[3]:EN Library setup time ADLIB:SLE - 0.112 4.163
data required time 4.163
Operating Conditions slow_lv_ht

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX_P PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P 0.579 0.579 1.470 0.982 slow_lv_lt
Path 2 RX_P PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_N_0/I_IOD_0:RX_N 0.579 0.579 1.077 0.506 slow_lv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX_P
To: PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P
data required time N/C
data arrival time - 0.579
slack N/C
Data arrival time calculation
RX_P 0.000 0.000 f
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/U_IOPADP:PAD net RX_P + 0.000 0.000 f
PF_IOD_CDR_C0_0/IB_DIFF_CDR_0/U_IOPADP:Y cell ADLIB:IOPADP_IN + 0.579 0.579 2 f
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P net PF_IOD_CDR_C0_0/IB_DIFF_CDR_0_Y + 0.000 0.579 f
data arrival time 0.579
Data required time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R N/C N/C
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 N/C f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB1:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.454 N/C f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB1:Y cell ADLIB:RGB + 0.050 N/C 902 r
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB1_rgb_net_1 + 0.563 N/C f
PF_IOD_CDR_C0_0/PF_IOD_CDR_RX_P_0/I_IOD_0:RX_P Library setup time ADLIB:IOD - 1.470 N/C
Operating Conditions slow_lv_lt

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiio0/CORETSEoiIi:CLK RD_BC_ERROR 11.308 12.492 12.492 slow_lv_ht
Path 2 PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R RX_CLK_R 4.209 4.209 4.209 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiio0/CORETSEoiIi:CLK
To: RD_BC_ERROR
data required time N/C
data arrival time - 12.492
slack N/C
Data arrival time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 0.000 0.000
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 0.000 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB0:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.562 0.562 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB0:Y cell ADLIB:RGB + 0.052 0.614 94 f
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiio0/CORETSEoiIi:CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB0_rgb_net_1 + 0.570 1.184 r
CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEi01lI.CORETSEI11lI/CORETSEoIiII/CORETSEiio0/CORETSEoiIi:Q cell ADLIB:SLE + 0.170 1.354 5 f
RD_BC_ERROR_obuf/U_IOTRI:D net RD_BC_ERROR_c + 8.187 9.541 f
RD_BC_ERROR_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.918 10.459 1 f
RD_BC_ERROR_obuf/U_IOPAD:D net RD_BC_ERROR_obuf/DOUT + 0.000 10.459 f
RD_BC_ERROR_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.033 12.492 0 f
RD_BC_ERROR net RD_BC_ERROR + 0.000 12.492 f
data arrival time 12.492
Data required time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R N/C N/C
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 N/C r
RD_BC_ERROR N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1]:ALn 0.779 2.137 1.943 4.080 0.183 2.658 0.101 slow_lv_ht
Path 2 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[0]:ALn 0.778 2.137 1.942 4.079 0.183 2.658 0.102 slow_lv_ht
Path 3 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[2]:ALn 0.777 2.138 1.941 4.079 0.183 2.655 0.102 slow_lv_ht
Path 4 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[3]:ALn 0.777 2.139 1.941 4.080 0.183 2.653 0.101 slow_lv_ht
Path 5 PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/early_flag[0]:ALn 0.787 2.154 1.951 4.105 0.170 2.615 0.089 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK
To: PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1]:ALn
data required time 4.080
data arrival time - 1.943
slack 2.137
Data arrival time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R 0.000 0.000
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 0.000 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.562 0.562 r
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:Y cell ADLIB:RGB + 0.052 0.614 161 f
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2_rgb_net_1 + 0.550 1.164 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n[0]:Q cell ADLIB:SLE + 0.175 1.339 54 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1]:ALn net PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/rst_n_Z[0] + 0.604 1.943 r
data arrival time 1.943
Data required time calculation
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R Clock Constraint 3.200 3.200
PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL:CLK_OUT_R Clock source + 0.000 3.200 f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:A net PF_IOD_CDR_C0_0/PF_LANECTRL_0_CLK_OUT_R + 0.456 3.656 f
PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2:Y cell ADLIB:RGB + 0.049 3.705 161 r
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1]:CLK net PF_IOD_CDR_C0_0/RCLKINT_0/U0_RGB2_rgb_net_1 + 0.490 4.195 r
clock reconvergence pessimism + 0.068 4.263
PF_IOD_CDR_C0_0/CDR4_CNTL_TIP_0/cnt[1]:ALn Library recovery time ADLIB:SLE - 0.183 4.080
data required time 4.080
Operating Conditions slow_lv_ht

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT0 to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT1 to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT2 to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CCC_0/pll_inst_0/OUT3 to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET PF_IOD_CDR_CCC_C0_0/PF_CLK_DIV_0/I_CD/Y_DIV to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

SET CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEIillI/CORETSEioolI/CORETSEOII1/CORETSEI110:Q to PF_IOD_CDR_C0_0/PF_LANECTRL_0/I_LANECTRL/CLK_OUT_R

No Path

Clock Domain PHY_MDC_CLOCK

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_CCC_0_0/PF_CCC_0_0/pll_inst_0/OUT0 to PHY_MDC_CLOCK

No Path

Path Set Pin to Pin

SET Input to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Operating Conditions
Path 1 RESET_N coma_mode 15.111 15.111 slow_lv_ht
Path 2 RESET_N REF_CLK_SEL 13.886 13.886 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RESET_N
To: coma_mode
data required time N/C
data arrival time - 15.111
slack N/C
Data arrival time calculation
RESET_N 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:PAD net RESET_N + 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.599 0.599 1 r
RESET_N_ibuf/U_IOIN:YIN net RESET_N_ibuf/YIN + 0.000 0.599 r
RESET_N_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.336 0.935 3 r
coma_mode_obuf_RNO:A net RESET_N_c + 8.812 9.747 r
coma_mode_obuf_RNO:Y cell ADLIB:CFG1 + 0.046 9.793 1 f
coma_mode_obuf/U_IOTRI:D net RESET_N_c_i + 1.319 11.112 f
coma_mode_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.969 12.081 1 f
coma_mode_obuf/U_IOPAD:D net coma_mode_obuf/DOUT + 0.000 12.081 f
coma_mode_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 3.030 15.111 0 f
coma_mode net coma_mode + 0.000 15.111 f
data arrival time 15.111
Data required time calculation
RESET_N N/C N/C r
coma_mode N/C f
data required time N/C
Operating Conditions slow_lv_ht

Path Set User Sets