logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q[16] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/URXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0 
logical_instance_name-CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q[16] Physical_names-[CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@CORESPI_0_0/CORESPI_0_0/USPI/UTXF/fifo_mem_q_fifo_mem_q_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-17 Port_B_Depth-32 Port_B_Width-17 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0 
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEl01lI/CORETSEIIil[39:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEl01lI/CORETSEIIil_CORETSEIIil_0_0/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEl01lI/CORETSEIIil_CORETSEIIil_0_2/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEl01lI/CORETSEIIil_CORETSEIIil_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEl01lI/CORETSEIIil_CORETSEIIil_0_3/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-2048 Port_A_Width-40 Port_B_Depth-2048 Port_B_Width-40 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0 
logical_instance_name-CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil[35:0] Physical_names-[CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_2/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_6/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_1/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_4/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_3/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_7/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_0/INST_RAM1K20_IP@@CORETSE_0_inst_0/CORETSE_0_0/CORETSEooIlI/CORETSEo01lI/CORETSEIIil_CORETSEIIil_0_5/INST_RAM1K20_IP@@] Cascade_type-Width Port_A_Depth-4096 Port_A_Width-36 Port_B_Depth-4096 Port_B_Width-36 RAM_type-0 RAM_Port_type-1 Memory_Source-3 ECC-0 
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0 Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R16C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R27C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R30C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R3C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R7C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R17C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R28C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R31C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R24C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R1C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R18C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R6C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R29C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R5C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R22C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R14C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R20C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R0C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R23C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R19C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R12C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R21C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R10C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R2C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R4C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R9C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R13C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R11C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R25C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R26C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R8C0/INST_RAM1K20_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/gen_tcm0.u_opsrv_TCM_0/tcm_ram_macro.u_ram_0/miv_rv32_ram_singleport_lp_R15C0/INST_RAM1K20_IP@@] Cascade_type-Depth Port_A_Depth-65536 Port_A_Width-32 Port_B_Depth-65536 Port_B_Width-32 RAM_type-0 RAM_Port_type-0 Memory_Source-0 ECC-0 
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_mem_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_mem_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_mem_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0 
logical_instance_name-MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_1[31:0] Physical_names-[MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_1_mem_1_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_1_mem_1_0_2/RAM64x12_PHYS_0/INST_RAM64x12_IP@@MIV_RV32_C0_0/MIV_RV32_C0_0/u_opsrv_0/u_core_0/u_expipe_0/gen_gpr_ram.u_gpr_0/gen_gpr.u_gpr_array_0/mem_1_mem_1_0_1/RAM64x12_PHYS_0/INST_RAM64x12_IP@@] Cascade_type-Width Port_A_Depth-32 Port_A_Width-32 Port_B_Depth-32 Port_B_Width-32 RAM_type-1 RAM_Port_type-0 Memory_Source-3 ECC-0 
