
#####  START OF DSP REPORT  #####

SNo     Instantiated     Instance_Name                                                                                                                                                                                                                      User_Attribute     MACC_Structure     MACC_Name                                                                                                                                                                                                                          Primitive_Type     DOTP     P_REG(EN/ARST/SRST)     A_REG(EN/ARST/SRST)     B_REG(EN/ARST/SRST)     C_REG(EN/ARST/SRST)     D_REG(EN/ARST/SRST)     SUB_REG(EN/ARST/SRST)     B2_REG(EN/ARST/SRST)
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1       YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_0.mx_0.g5_macc\.macc_0                                                                                                NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_0.mx_0.g5_macc\.macc_0                                                                                                MACC_PA            0        1(0/0/0)                1(0/0/0)                1(0/0/0)                1(0/0/1)                1(0/0/1)                0(0/0/0)                  0(0/0/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_0.mx_1.g5_macc\.macc_0                                                                                                NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_0.mx_1.g5_macc\.macc_0                                                                                                MACC_PA            0        1(0/0/0)                1(0/0/0)                1(0/0/0)                1(0/0/1)                1(0/0/1)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
2       YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_1.mx_0.g5_macc\.macc_0                                                                                                NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_1.mx_0.g5_macc\.macc_0                                                                                                MACC_PA            0        1(0/0/0)                1(0/0/0)                1(0/0/0)                1(0/0/1)                1(0/0/1)                0(0/0/0)                  0(0/0/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_1.mx_1.g5_macc\.macc_0                                                                                                NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.bfly_0.cmplx_0.genblk1\.cmplx18_0.half_1.mx_1.g5_macc\.macc_0                                                                                                MACC_PA            0        1(0/0/0)                1(0/0/0)                1(0/0/0)                1(0/0/1)                1(0/0/1)                0(0/0/0)                  0(0/0/0)            
                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       
3       YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                       NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                       MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                    MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                      NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.left_nibble_0.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0                      MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.1\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.2\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.3\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.4\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.5\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0            MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0         MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.mid_nibbles\.6\.a_nibble.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0           MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0        NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.left_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0        MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.1\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.2\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.3\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.4\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.5\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.taps\.6\.atap.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0     MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
        YES              PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0       NA                 NA                 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.rows\.1\.a_row.right_nibble\.right_nibble_0.many_tap_nibble\.many_tap_nibble_0.right_tap_0.MACC_PA_BC_ROM_wrap_0.MACC_PA_BC_ROM_0       MACC_PA_BC_ROM     0        1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                1(1/1/0)                0(0/0/0)                  1(1/1/0)            
=======================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================================

#####  END OF DSP REPORT  #####

