#Build: Synplify Pro (R) Q-2020.03M-SP1, Build 166R, Oct 19 2020 #install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro #OS: Windows 8 6.2 #Hostname: HYD-LT-I62935 # Wed Jan 13 10:53:51 2021 #Implementation: synthesis Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys HDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys VHDL Compiler, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode @N: : PF_COREFIR.vhd(70) | Top entity is set to PF_COREFIR. VHDL syntax check successful! @N:CD231 : std1164.vhd(888) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 172MB peak: 172MB) Process completed successfully. # Wed Jan 13 10:53:52 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Verilog Compiler, Version comp202003synp2, Build 170R, Built Oct 21 2020 10:52:30, @ @N: : | Running in 64-bit mode @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\polarfire_syn_comps.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\fifo_256x8_g5.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\FILTER_CONTROL_FSM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\PF_COREFFT_PF_COREFFT_0_uram_g5.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\twiddle32.v" (library COREFFT_LIB) @N:CG347 : twiddle32.v(35) | Read a parallel_case directive. @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\mac_lib.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0_0\PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1_0\PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2_0\PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3_0\PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4_0\PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_DSP_FLOW_DEMO_TOP\PF_DSP_FLOW_DEMO_TOP.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_ccc_0\PF_ccc_0_0\PF_ccc_0_PF_ccc_0_0_PF_CCC.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_ccc_0\PF_ccc_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\reset_sync\reset_sync.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 98MB) Process completed successfully. # Wed Jan 13 10:53:52 2021 ###########################################################] ###########################################################[ @N:CG1349 : | Running Verilog Compiler in System Verilog mode @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\generic\acg5.v" (library work) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\hypermods.v" (library __hyper__lib__) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\umr_capim.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_objects.v" (library snps_haps) @I::"C:\Microsemi\Libero_SoC_v12.6\SynplifyPro\lib\vlog\scemi_pipes.svh" (library snps_haps) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\polarfire_syn_comps.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\fifo_256x8_g5.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Clock_gen.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\FILTER_CONTROL_FSM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\PF_COREFFT_PF_COREFFT_0_uram_g5.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\twiddle32.v" (library COREFFT_LIB) @N:CG347 : twiddle32.v(35) | Read a parallel_case directive. @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\mac_lib.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\cmplx.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v" (library COREFFT_LIB) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0_0\PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_0\PF_TPSRAM_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1_0\PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_1\PF_TPSRAM_1.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2_0\PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_2\PF_TPSRAM_2.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3_0\PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_3\PF_TPSRAM_3.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4_0\PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_TPSRAM_4\PF_TPSRAM_4.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_DSP_FLOW_DEMO_TOP\PF_DSP_FLOW_DEMO_TOP.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_ccc_0\PF_ccc_0_0\PF_ccc_0_PF_ccc_0_0_PF_CCC.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_ccc_0\PF_ccc_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\reset_sync\reset_sync.v" (library work) @I::"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\top\top.v" (library work) Verilog syntax check successful! @N:CG364 : acg5.v(489) | Synthesizing module CLKINT in library work. Running optimization stage 1 on CLKINT ....... @W:CG1283 : PF_ccc_0_PF_ccc_0_0_PF_CCC.v(39) | Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(8364) | Synthesizing module PLL in library work. Running optimization stage 1 on PLL ....... @N:CG364 : acg5.v(504) | Synthesizing module VCC in library work. Running optimization stage 1 on VCC ....... @N:CG364 : acg5.v(500) | Synthesizing module GND in library work. Running optimization stage 1 on GND ....... @N:CG364 : PF_ccc_0_PF_ccc_0_0_PF_CCC.v(5) | Synthesizing module PF_ccc_0_PF_ccc_0_0_PF_CCC in library work. Running optimization stage 1 on PF_ccc_0_PF_ccc_0_0_PF_CCC ....... @N:CG364 : PF_ccc_0.v(263) | Synthesizing module PF_ccc_0 in library work. Running optimization stage 1 on PF_ccc_0 ....... @N:CG364 : Clock_gen.v(38) | Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Clock_gen in library work. BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = PF_COREUART_0_PF_COREUART_0_0_Clock_gen_1s_0s @N:CG179 : Clock_gen.v(128) | Removing redundant assignment. @N:CG179 : Clock_gen.v(149) | Removing redundant assignment. @N:CG179 : Clock_gen.v(169) | Removing redundant assignment. @N:CG179 : Clock_gen.v(189) | Removing redundant assignment. @N:CG179 : Clock_gen.v(209) | Removing redundant assignment. @N:CG179 : Clock_gen.v(229) | Removing redundant assignment. @N:CG179 : Clock_gen.v(249) | Removing redundant assignment. Running optimization stage 1 on PF_COREUART_0_PF_COREUART_0_0_Clock_gen_1s_0s ....... @N:CG364 : Tx_async.v(31) | Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Tx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 TX_FIFO=32'b00000000000000000000000000000000 tx_idle=32'b00000000000000000000000000000000 tx_load=32'b00000000000000000000000000000001 start_bit=32'b00000000000000000000000000000010 tx_data_bits=32'b00000000000000000000000000000011 parity_bit=32'b00000000000000000000000000000100 tx_stop_bit=32'b00000000000000000000000000000101 delay_state=32'b00000000000000000000000000000110 Generated name = PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s @W:CG1340 : Tx_async.v(268) | Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @W:CG1340 : Tx_async.v(268) | Index into variable tx_byte could be out of range ; a simulation mismatch is possible. @N:CG179 : Tx_async.v(356) | Removing redundant assignment. Running optimization stage 1 on PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @W:CL190 : Tx_async.v(119) | Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:CL169 : Tx_async.v(119) | Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers. @N:CG364 : Rx_async.v(30) | Synthesizing module PF_COREUART_0_PF_COREUART_0_0_Rx_async in library work. SYNC_RESET=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 receive_states_rx_idle=32'b00000000000000000000000000000000 receive_states_rx_data_bits=32'b00000000000000000000000000000001 receive_states_rx_stop_bit=32'b00000000000000000000000000000010 receive_states_rx_wait_state=32'b00000000000000000000000000000011 Generated name = PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s @N:CG179 : Rx_async.v(254) | Removing redundant assignment. @N:CG179 : Rx_async.v(280) | Removing redundant assignment. Running optimization stage 1 on PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @W:CL177 : Rx_async.v(501) | Sharing sequential element clear_framing_error_en. Add a syn_preserve attribute to the element to prevent sharing. @N:CG364 : CoreUART.v(31) | Synthesizing module PF_COREUART_0_PF_COREUART_0_0_COREUART in library work. TX_FIFO=32'b00000000000000000000000000000000 RX_FIFO=32'b00000000000000000000000000000000 RX_LEGACY_MODE=32'b00000000000000000000000000000000 FAMILY=32'b00000000000000000000000000011010 BAUD_VAL_FRCTN_EN=32'b00000000000000000000000000000001 SYNC_RESET=32'b00000000000000000000000000000000 Generated name = PF_COREUART_0_PF_COREUART_0_0_COREUART_0s_0s_0s_26s_1s_0s @N:CG179 : CoreUART.v(390) | Removing redundant assignment. @W:CG133 : CoreUART.v(136) | Object data_ready is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on PF_COREUART_0_PF_COREUART_0_0_COREUART_0s_0s_0s_26s_1s_0s ....... @W:CL169 : CoreUART.v(376) | Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(341) | Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(341) | Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(326) | Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(293) | Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(278) | Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(278) | Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(263) | Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(263) | Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers. @W:CL169 : CoreUART.v(159) | Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers. @N:CG364 : PF_COREUART_0.v(26) | Synthesizing module PF_COREUART_0 in library work. Running optimization stage 1 on PF_COREUART_0 ....... @N:CG364 : FILTER_CONTROL_FSM.v(35) | Synthesizing module FILTERCONTROL_FSM in library work. Running optimization stage 1 on FILTERCONTROL_FSM ....... @N:CG364 : acg5.v(578) | Synthesizing module RAM1K20 in library work. Running optimization stage 1 on RAM1K20 ....... @N:CG364 : PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM.v(5) | Synthesizing module PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM in library work. Running optimization stage 1 on PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM ....... @N:CG364 : PF_TPSRAM_0.v(59) | Synthesizing module PF_TPSRAM_0 in library work. Running optimization stage 1 on PF_TPSRAM_0 ....... @N:CG775 : COREFFT_TOP.v(28) | Component PF_COREFFT_PF_COREFFT_0_COREFFT not found in library "work" or "__hyper__lib__", but found in library COREFFT_LIB @N:CG364 : COREFFT_TOP.v(28) | Synthesizing module PF_COREFFT_PF_COREFFT_0_COREFFT in library COREFFT_LIB. FPGA_FAMILY=32'b00000000000000000000000000011010 URAM_MAXDEPTH=32'b00000000000000000000001000000000 CFG_ARCH=32'b00000000000000000000000000000001 DATA_BITS=32'b00000000000000000000000000010010 TWID_BITS=32'b00000000000000000000000000010010 FFT_SIZE=32'b00000000000000000000000100000000 SCALE_ON=32'b00000000000000000000000000000001 SCALE_SCH=32'b00000000000000000000000011111111 ORDER=32'b00000000000000000000000000000000 INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 SCALE_EXP_ON=32'b00000000000000000000000000000000 NO_RAM=32'b00000000000000000000000000000000 LOG2PTS=32'b00000000000000000000000000001000 LOGLOG2PTS=32'b00000000000000000000000000000011 FLOGLOG2PTS=32'b00000000000000000000000000000100 STREAM_DATAO_BITS=32'b00000000000000000000000000010010 IN_BITS=32'b00000000000000000000000000010000 OUTP_BITS=32'b00000000000000000000000000010000 Generated name = PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0 @N:CG364 : kit.v(445) | Synthesizing module fft_inpl_slowClock in library COREFFT_LIB. Running optimization stage 1 on fft_inpl_slowClock ....... @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_bit_reg_2s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_2s ....... @N:CG364 : kit.v(29) | Synthesizing module fft_inpl_kitEdge in library COREFFT_LIB. FRONT_EDGE=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitEdge_0s Running optimization stage 1 on fft_inpl_kitEdge_0s ....... @N:CG364 : kit.v(126) | Synthesizing module fft_inpl_counter_w in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000001010 TC=32'b00000000000000000000000010001001 Generated name = fft_inpl_counter_w_10_137s Running optimization stage 1 on fft_inpl_counter_w_10_137s ....... @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000101 TC=32'b00000000000000000000000000000111 Generated name = fft_inpl_counter_5_7 Running optimization stage 1 on fft_inpl_counter_5_7 ....... @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000011 Generated name = fft_inpl_kitDelay_bit_reg_3s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_3s ....... @N:CG364 : fftSm.v(361) | Synthesizing module fft_inpl_rdFFTtimer in library COREFFT_LIB. HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_rdFFTtimer_128s_8_3_10s_1s Running optimization stage 1 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000001010 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_10_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_10_2s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000101 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_5_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_5_2s ....... @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_bit_reg_1s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_1s ....... @N:CG364 : kit.v(99) | Synthesizing module fft_inpl_kitCountS in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000111 DCVALUE=32'b00000000000000000000000001111111 BUILD_DC=32'b00000000000000000000000000000000 Generated name = fft_inpl_kitCountS_7_127s_0s Running optimization stage 1 on fft_inpl_kitCountS_7_127s_0s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000111 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_7_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_7_2s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000001 DELAY=32'b00000000000000000000000000001010 Generated name = fft_inpl_kitDelay_reg_1s_10s Running optimization stage 1 on fft_inpl_kitDelay_reg_1s_10s ....... @N:CG364 : kit.v(70) | Synthesizing module fft_inpl_counter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000001000 TC=32'b00000000000000000000000011111111 Generated name = fft_inpl_counter_8_255s Running optimization stage 1 on fft_inpl_counter_8_255s ....... @N:CG364 : fftSm.v(481) | Synthesizing module fft_inpl_inBuf_ldA in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 Generated name = fft_inpl_inBuf_ldA_256s_8 @W:CG360 : fftSm.v(502) | Removing wire load_over, as there is no assignment to it. Running optimization stage 1 on fft_inpl_inBuf_ldA_256s_8 ....... @N:CG364 : fftSm.v(623) | Synthesizing module fft_inpl_inBuf_fftA_pipe in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_inBuf_fftA_pipe_8_3 Running optimization stage 1 on fft_inpl_inBuf_fftA_pipe_8_3 ....... @W:CL265 : fftSm.v(675) | Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal. @N:CG364 : fftSm.v(695) | Synthesizing module fft_inpl_twid_rA in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_rA_8_3 Running optimization stage 1 on fft_inpl_twid_rA_8_3 ....... @N:CG364 : kit.v(186) | Synthesizing module fft_inpl_kitDelay_bit_reg in library COREFFT_LIB. DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_bit_reg_4s Running optimization stage 1 on fft_inpl_kitDelay_bit_reg_4s ....... @N:CG364 : kit.v(405) | Synthesizing module fft_inpl_kitSync_ngrst in library COREFFT_LIB. PULSE_WIDTH=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitSync_ngrst_1s @W:CG133 : kit.v(412) | Object tick2 is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on fft_inpl_kitSync_ngrst_1s ....... @N:CG364 : kit.v(161) | Synthesizing module fft_inpl_bcounter in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000000111 Generated name = fft_inpl_bcounter_7 Running optimization stage 1 on fft_inpl_bcounter_7 ....... @N:CG364 : fftSm.v(739) | Synthesizing module fft_inpl_twid_wA_gen in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 Generated name = fft_inpl_twid_wA_gen_8_3 Running optimization stage 1 on fft_inpl_twid_wA_gen_8_3 ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000011 DELAY=32'b00000000000000000000000000000010 Generated name = fft_inpl_kitDelay_reg_3_2s Running optimization stage 1 on fft_inpl_kitDelay_reg_3_2s ....... @N:CG364 : fftSm.v(532) | Synthesizing module fft_inpl_outBufA in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 LOGPTS=32'b00000000000000000000000000001000 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_outBufA_256s_8_1s Running optimization stage 1 on fft_inpl_outBufA_256s_8_1s ....... @N:CG364 : fftSm.v(29) | Synthesizing module fft_inpl_sm_top in library COREFFT_LIB. PTS=32'b00000000000000000000000100000000 HALFPTS=32'b00000000000000000000000010000000 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_sm_top_256s_128s_8_3_10s_1s Running optimization stage 1 on fft_inpl_sm_top_256s_128s_8_3_10s_1s ....... @W:CL168 : fftSm.v(234) | Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @W:CL168 : fftSm.v(118) | Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive. @N:CG364 : fftDp.v(249) | Synthesizing module PF_COREFFT_PF_COREFFT_0_inPlace in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000001000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 Generated name = PF_COREFFT_PF_COREFFT_0_inPlace_8_32s_1s_512s_26s @N:CG364 : fftDp.v(163) | Synthesizing module PF_COREFFT_PF_COREFFT_0_inBuffer in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000001000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 Generated name = PF_COREFFT_PF_COREFFT_0_inBuffer_8_32s_1s_512s_26s @N:CG364 : fftDp.v(36) | Synthesizing module PF_COREFFT_PF_COREFFT_0_wrapRam in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 FPGA_FAMILY=32'b00000000000000000000000000011010 URAM_MAXDEPTH=32'b00000000000000000000001000000000 RAM_DEPTH=32'b00000000000000000000000010000000 SMARTGEN=32'b00000000000000000000000000000001 Generated name = PF_COREFFT_PF_COREFFT_0_wrapRam_8_32s_26s_512s_128s_1s @N:CG364 : acg5.v(133) | Synthesizing module OR2 in library work. Running optimization stage 1 on OR2 ....... @N:CG364 : acg5.v(102) | Synthesizing module CFG2 in library work. Running optimization stage 1 on CFG2 ....... @N:CG364 : acg5.v(508) | Synthesizing module RAM64x12 in library work. Running optimization stage 1 on RAM64x12 ....... @N:CG364 : PF_COREFFT_PF_COREFFT_0_uram_g5.v(5) | Synthesizing module PF_COREFFT_PF_COREFFT_0_uram_g5 in library COREFFT_LIB. Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_uram_g5 ....... Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_wrapRam_8_32s_26s_512s_128s_1s ....... Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_inBuffer_8_32s_1s_512s_26s ....... @W:CG133 : fftDp.v(267) | Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(268) | Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : fftDp.v(270) | Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_inPlace_8_32s_1s_512s_26s ....... @N:CG364 : kit.v(460) | Synthesizing module fft_inpl_switch in library COREFFT_LIB. DWIDTH=32'b00000000000000000000000000100000 Generated name = fft_inpl_switch_32s Running optimization stage 1 on fft_inpl_switch_32s ....... @N:CG364 : kit.v(326) | Synthesizing module fft_inpl_kitRndUp in library COREFFT_LIB. WIDTH_OUT=32'b00000000000000000000000000010000 RND_MODE=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitRndUp_16s_1s Running optimization stage 1 on fft_inpl_kitRndUp_16s_1s ....... @N:CG364 : cmplx.v(442) | Synthesizing module fft_inpl_cmplx_rnd in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 RND=32'b00000000000000000000000000000001 P_WIDTH=32'b00000000000000000000000000110000 Generated name = fft_inpl_cmplx_rnd_16s_0s_26s_1s_48s @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB. INWIDTH=32'b00000000000000000000000000010000 OUTWIDTH=32'b00000000000000000000000000010010 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_16s_18s_0s Running optimization stage 1 on fft_inpl_signExt_16s_18s_0s ....... @N:CG364 : mac_lib.v(36) | Synthesizing module fft_inpl_mac18x18mx in library COREFFT_LIB. WIDTH_A=32'b00000000000000000000000000010000 WIDTH_B=32'b00000000000000000000000000010000 BYPASS_REG_A=32'b00000000000000000000000000000000 BYPASS_REG_B=32'b00000000000000000000000000000000 BYPASS_REG_P=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 BY_REGA=2'b00 BY_REGB=2'b00 BY_REGP=2'b00 P_WIDTH=32'b00000000000000000000000000110000 Generated name = fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s @N:CG364 : acg5.v(674) | Synthesizing module MACC_PA in library work. Running optimization stage 1 on MACC_PA ....... Running optimization stage 1 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s ....... @N:CG364 : kit.v(364) | Synthesizing module fft_inpl_signExt in library COREFFT_LIB. INWIDTH=32'b00000000000000000000000000110000 OUTWIDTH=32'b00000000000000000000000000100001 UNSIGNED=32'b00000000000000000000000000000000 Generated name = fft_inpl_signExt_48s_33s_0s Running optimization stage 1 on fft_inpl_signExt_48s_33s_0s ....... @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000001 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 P_WIDTH=32'b00000000000000000000000000110000 SUB=1'b1 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_1s_0s_26s_48s_1_0s @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000001 Generated name = fft_inpl_kitDelay_reg_16s_1s Running optimization stage 1 on fft_inpl_kitDelay_reg_16s_1s ....... Running optimization stage 1 on fft_inpl_half_cmplx_18_16s_1s_0s_26s_48s_1_0s ....... @N:CG364 : cmplx.v(354) | Synthesizing module fft_inpl_half_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 MINUS=32'b00000000000000000000000000000000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 P_WIDTH=32'b00000000000000000000000000110000 SUB=1'b0 DBG=32'b00000000000000000000000000000000 Generated name = fft_inpl_half_cmplx_18_16s_0s_0s_26s_48s_0_0s Running optimization stage 1 on fft_inpl_half_cmplx_18_16s_0s_0s_26s_48s_0_0s ....... @N:CG364 : cmplx.v(414) | Synthesizing module fft_inpl_cmplx_18 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 NOPIPE=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 P_WIDTH=32'b00000000000000000000000000110000 Generated name = fft_inpl_cmplx_18_16s_0s_26s_48s Running optimization stage 1 on fft_inpl_cmplx_18_16s_0s_26s_48s ....... Running optimization stage 1 on fft_inpl_cmplx_rnd_16s_0s_26s_1s_48s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000010000 DELAY=32'b00000000000000000000000000000100 Generated name = fft_inpl_kitDelay_reg_16s_4s Running optimization stage 1 on fft_inpl_kitDelay_reg_16s_4s ....... @N:CG364 : kit.v(226) | Synthesizing module fft_inpl_kitDelay_reg in library COREFFT_LIB. BITWIDTH=32'b00000000000000000000000000000010 DELAY=32'b00000000000000000000000000000101 Generated name = fft_inpl_kitDelay_reg_2s_5s Running optimization stage 1 on fft_inpl_kitDelay_reg_2s_5s ....... @N:CG364 : kit.v(499) | Synthesizing module fft_inpl_bfly2 in library COREFFT_LIB. WIDTH=32'b00000000000000000000000000010000 TWIDTH=32'b00000000000000000000000000010000 DWIDTH=32'b00000000000000000000000000100000 TDWIDTH=32'b00000000000000000000000000100000 MPIPE=32'b00000000000000000000000000000011 FPGA_FAMILY=32'b00000000000000000000000000011010 Generated name = fft_inpl_bfly2_16s_16s_32s_32s_3s_26s Running optimization stage 1 on fft_inpl_bfly2_16s_16s_32s_32s_3s_26s ....... @N:CG364 : twiddle32.v(27) | Synthesizing module PF_COREFFT_PF_COREFFT_0_twiddle in library COREFFT_LIB. TDWIDTH=32'b00000000000000000000000000100000 LOGPTS=32'b00000000000000000000000000001000 Generated name = PF_COREFFT_PF_COREFFT_0_twiddle_32s_8 Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_twiddle_32s_8 ....... @N:CG364 : fftDp.v(369) | Synthesizing module PF_COREFFT_PF_COREFFT_0_twidLUT in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 TDWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000001000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 Generated name = PF_COREFFT_PF_COREFFT_0_twidLUT_8_32s_512s_26s Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_twidLUT_8_32s_512s_26s ....... @N:CG364 : kit.v(570) | Synthesizing module fft_inpl_autoScale in library COREFFT_LIB. SCALE_MODE=32'b00000000000000000000000000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 LOGLOGPTS=32'b00000000000000000000000000000100 MEMBUF=32'b00000000000000000000000000000001 Generated name = fft_inpl_autoScale_0s_0s_4_1s @W:CG133 : kit.v(590) | Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration. @W:CG133 : kit.v(590) | Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration. Running optimization stage 1 on fft_inpl_autoScale_0s_0s_4_1s ....... @N:CG364 : COREFFT.v(28) | Synthesizing module PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC in library COREFFT_LIB. INVERSE=32'b00000000000000000000000000000000 SCALE=32'b00000000000000000000000000000000 POINTS=32'b00000000000000000000000100000000 WIDTH=32'b00000000000000000000000000010000 MEMBUF=32'b00000000000000000000000000000001 URAM_MAXDEPTH=32'b00000000000000000000001000000000 SCALE_EXP_ON=32'b00000000000000000000000000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 LOGPTS=32'b00000000000000000000000000001000 LOGLOGPTS=32'b00000000000000000000000000000011 FLOGLOGPTS=32'b00000000000000000000000000000100 DWIDTH=32'b00000000000000000000000000100000 TWIDTH=32'b00000000000000000000000000010000 TDWIDTH=32'b00000000000000000000000000100000 HALFPTS=32'b00000000000000000000000010000000 MPIPE=32'b00000000000000000000000000000011 RW_DLY=32'b00000000000000000000000000001010 Generated name = PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0 @N:CG364 : fftDp.v(329) | Synthesizing module PF_COREFFT_PF_COREFFT_0_outBuff in library COREFFT_LIB. LOGPTS=32'b00000000000000000000000000001000 DWIDTH=32'b00000000000000000000000000100000 URAM_MAXDEPTH=32'b00000000000000000000001000000000 FPGA_FAMILY=32'b00000000000000000000000000011010 Generated name = PF_COREFFT_PF_COREFFT_0_outBuff_8_32s_512s_26s Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_outBuff_8_32s_512s_26s ....... @W:CG360 : COREFFT.v(86) | Removing wire outPQ, as there is no assignment to it. @W:CG360 : COREFFT.v(87) | Removing wire ctrl_outp, as there is no assignment to it. Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0 ....... Running optimization stage 1 on PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0 ....... @W:CL318 : COREFFT_TOP.v(86) | *Output RFS has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @W:CL318 : COREFFT_TOP.v(86) | *Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 'Z'. Simulation mismatch possible. Assign all bits of the output. @N:CG364 : PF_COREFFT.v(46) | Synthesizing module PF_COREFFT in library work. Running optimization stage 1 on PF_COREFFT ....... @N:CG364 : PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM.v(5) | Synthesizing module PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM in library work. Running optimization stage 1 on PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM ....... @N:CG364 : PF_TPSRAM_3.v(59) | Synthesizing module PF_TPSRAM_3 in library work. Running optimization stage 1 on PF_TPSRAM_3 ....... @N:CG364 : PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM.v(5) | Synthesizing module PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM in library work. Running optimization stage 1 on PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM ....... @N:CG364 : PF_TPSRAM_4.v(59) | Synthesizing module PF_TPSRAM_4 in library work. Running optimization stage 1 on PF_TPSRAM_4 ....... @N:CG364 : PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM.v(5) | Synthesizing module PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM in library work. Running optimization stage 1 on PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM ....... @N:CG364 : PF_TPSRAM_1.v(59) | Synthesizing module PF_TPSRAM_1 in library work. Running optimization stage 1 on PF_TPSRAM_1 ....... @N:CG364 : PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM.v(5) | Synthesizing module PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM in library work. Running optimization stage 1 on PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM ....... @N:CG364 : PF_TPSRAM_2.v(59) | Synthesizing module PF_TPSRAM_2 in library work. Running optimization stage 1 on PF_TPSRAM_2 ....... @N:CG364 : UART_IF.v(35) | Synthesizing module UART_IF in library work. @W:CG296 : UART_IF.v(135) | Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list. @W:CG290 : UART_IF.v(139) | Referenced variable RAM_REN is not in sensitivity list. @W:CG290 : UART_IF.v(142) | Referenced variable FIR_OUT_RDATA is not in sensitivity list. @W:CG290 : UART_IF.v(149) | Referenced variable FFT_RE_RDATA is not in sensitivity list. @W:CG290 : UART_IF.v(156) | Referenced variable FFT_IM_RDATA is not in sensitivity list. Running optimization stage 1 on UART_IF ....... @N:CG364 : PF_DSP_FLOW_DEMO_TOP.v(9) | Synthesizing module PF_DSP_FLOW_DEMO_TOP in library work. @N:CG794 : PF_DSP_FLOW_DEMO_TOP.v(179) | Using module PF_COREFIR from library work Running optimization stage 1 on PF_DSP_FLOW_DEMO_TOP ....... @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(40) | Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(1714) | Synthesizing module INIT in library work. Running optimization stage 1 on INIT ....... @W:CG1283 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(50) | Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type @N:CG364 : polarfire_syn_comps.v(216) | Synthesizing module BANKEN in library work. Running optimization stage 1 on BANKEN ....... @N:CG364 : PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v(5) | Synthesizing module PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR in library work. Running optimization stage 1 on PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR ....... @N:CG364 : PF_init_monitor_0.v(82) | Synthesizing module PF_init_monitor_0 in library work. Running optimization stage 1 on PF_init_monitor_0 ....... @N:CG364 : corereset_pf.v(21) | Synthesizing module reset_sync_reset_sync_0_CORERESET_PF in library work. Running optimization stage 1 on reset_sync_reset_sync_0_CORERESET_PF ....... @N:CG364 : reset_sync.v(21) | Synthesizing module reset_sync in library work. Running optimization stage 1 on reset_sync ....... @N:CG364 : top.v(9) | Synthesizing module top in library work. Running optimization stage 1 on top ....... Running optimization stage 2 on top ....... Running optimization stage 2 on reset_sync ....... Running optimization stage 2 on reset_sync_reset_sync_0_CORERESET_PF ....... @N:CL135 : corereset_pf.v(58) | Found sequential shift dff with address depth of 16 words and data bit width of 1. Running optimization stage 2 on PF_init_monitor_0 ....... Running optimization stage 2 on PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR ....... Running optimization stage 2 on BANKEN ....... Running optimization stage 2 on INIT ....... Running optimization stage 2 on PF_DSP_FLOW_DEMO_TOP ....... Running optimization stage 2 on UART_IF ....... @N:CL201 : UART_IF.v(186) | Trying to extract state machine for register rfsm. Extracted state machine for register rfsm State machine has 15 reachable states with original encodings of: 0000 0001 0010 0011 0100 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Running optimization stage 2 on PF_TPSRAM_2 ....... Running optimization stage 2 on PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM ....... Running optimization stage 2 on PF_TPSRAM_1 ....... Running optimization stage 2 on PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM ....... Running optimization stage 2 on PF_TPSRAM_4 ....... Running optimization stage 2 on PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM ....... Running optimization stage 2 on PF_TPSRAM_3 ....... Running optimization stage 2 on PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM ....... Running optimization stage 2 on PF_COREFFT ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_outBuff_8_32s_512s_26s ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0 ....... Running optimization stage 2 on fft_inpl_autoScale_0s_0s_4_1s ....... @A:CL153 : kit.v(590) | *Unassigned bits of scale_exp_r[3:0] are referenced and tied to 0 -- simulation mismatch possible. @N:CL159 : kit.v(584) | Input fftRd_done_tick is unused. Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_twidLUT_8_32s_512s_26s ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_twiddle_32s_8 ....... Running optimization stage 2 on fft_inpl_bfly2_16s_16s_32s_32s_3s_26s ....... @W:CL260 : kit.v(560) | Pruning register bit 16 of outQ[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level. Running optimization stage 2 on fft_inpl_kitDelay_reg_2s_5s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_16s_4s ....... Running optimization stage 2 on fft_inpl_cmplx_18_16s_0s_26s_48s ....... Running optimization stage 2 on fft_inpl_half_cmplx_18_16s_0s_0s_26s_48s_0_0s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_16s_1s ....... Running optimization stage 2 on fft_inpl_half_cmplx_18_16s_1s_0s_26s_48s_1_0s ....... Running optimization stage 2 on fft_inpl_signExt_48s_33s_0s ....... @W:CL246 : kit.v(369) | Input port bits 46 to 32 of inp[47:0] are unused. Assign logic for all port bits or change the input port size. Running optimization stage 2 on MACC_PA ....... Running optimization stage 2 on fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s ....... Running optimization stage 2 on fft_inpl_signExt_16s_18s_0s ....... Running optimization stage 2 on fft_inpl_cmplx_rnd_16s_0s_26s_1s_48s ....... Running optimization stage 2 on fft_inpl_kitRndUp_16s_1s ....... Running optimization stage 2 on fft_inpl_switch_32s ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_uram_g5 ....... Running optimization stage 2 on RAM64x12 ....... Running optimization stage 2 on CFG2 ....... Running optimization stage 2 on OR2 ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_wrapRam_8_32s_26s_512s_128s_1s ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_inBuffer_8_32s_1s_512s_26s ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_inPlace_8_32s_1s_512s_26s ....... @N:CL159 : fftDp.v(258) | Input load is unused. Running optimization stage 2 on fft_inpl_sm_top_256s_128s_8_3_10s_1s ....... Running optimization stage 2 on fft_inpl_outBufA_256s_8_1s ....... @N:CL159 : fftSm.v(549) | Input rTimerTC_tick is unused. Running optimization stage 2 on fft_inpl_kitDelay_reg_3_2s ....... Running optimization stage 2 on fft_inpl_twid_wA_gen_8_3 ....... Running optimization stage 2 on fft_inpl_bcounter_7 ....... Running optimization stage 2 on fft_inpl_kitSync_ngrst_1s ....... Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_4s ....... Running optimization stage 2 on fft_inpl_twid_rA_8_3 ....... Running optimization stage 2 on fft_inpl_inBuf_fftA_pipe_8_3 ....... Running optimization stage 2 on fft_inpl_inBuf_ldA_256s_8 ....... @N:CL159 : fftSm.v(493) | Input clkEn is unused. Running optimization stage 2 on fft_inpl_counter_8_255s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_1s_10s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_7_2s ....... Running optimization stage 2 on fft_inpl_kitCountS_7_127s_0s ....... Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_1s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_5_2s ....... Running optimization stage 2 on fft_inpl_kitDelay_reg_10_2s ....... Running optimization stage 2 on fft_inpl_rdFFTtimer_128s_8_3_10s_1s ....... Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_3s ....... Running optimization stage 2 on fft_inpl_counter_5_7 ....... Running optimization stage 2 on fft_inpl_counter_w_10_137s ....... Running optimization stage 2 on fft_inpl_kitEdge_0s ....... Running optimization stage 2 on fft_inpl_kitDelay_bit_reg_2s ....... Running optimization stage 2 on fft_inpl_slowClock ....... Running optimization stage 2 on PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0 ....... @N:CL159 : COREFFT_TOP.v(85) | Input CLKEN is unused. @N:CL159 : COREFFT_TOP.v(85) | Input RST is unused. @N:CL159 : COREFFT_TOP.v(85) | Input START is unused. @N:CL159 : COREFFT_TOP.v(85) | Input INVERSE_STRM is unused. @N:CL159 : COREFFT_TOP.v(85) | Input REFRESH is unused. Running optimization stage 2 on PF_TPSRAM_0 ....... Running optimization stage 2 on PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM ....... Running optimization stage 2 on RAM1K20 ....... Running optimization stage 2 on FILTERCONTROL_FSM ....... @N:CL201 : FILTER_CONTROL_FSM.v(98) | Trying to extract state machine for register fsm. Extracted state machine for register fsm State machine has 5 reachable states with original encodings of: 000 001 010 011 100 Running optimization stage 2 on PF_COREUART_0 ....... Running optimization stage 2 on PF_COREUART_0_PF_COREUART_0_0_COREUART_0s_0s_0s_26s_1s_0s ....... Running optimization stage 2 on PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s ....... @N:CL201 : Rx_async.v(286) | Trying to extract state machine for register rx_state. Extracted state machine for register rx_state State machine has 4 reachable states with original encodings of: 00 01 10 11 Running optimization stage 2 on PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s ....... @N:CL201 : Tx_async.v(119) | Trying to extract state machine for register xmit_state. Extracted state machine for register xmit_state State machine has 6 reachable states with original encodings of: 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 00000000000000000000000000000100 00000000000000000000000000000101 @N:CL159 : Tx_async.v(44) | Input tx_dout_reg is unused. @N:CL159 : Tx_async.v(45) | Input fifo_empty is unused. @N:CL159 : Tx_async.v(46) | Input fifo_full is unused. Running optimization stage 2 on PF_COREUART_0_PF_COREUART_0_0_Clock_gen_1s_0s ....... Running optimization stage 2 on PF_ccc_0 ....... Running optimization stage 2 on PF_ccc_0_PF_ccc_0_0_PF_CCC ....... Running optimization stage 2 on GND ....... Running optimization stage 2 on VCC ....... Running optimization stage 2 on PLL ....... Running optimization stage 2 on CLKINT ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer0.rt.csv At c_ver Exit (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 108MB peak: 111MB) Process completed successfully. # Wed Jan 13 10:54:03 2021 ###########################################################] ###########################################################[ @N: : PF_COREFIR.vhd(70) | Top entity is set to PF_COREFIR. VHDL syntax check successful! @N:CD231 : std1164.vhd(888) | Using onehot encoding for type mvl9plus. For example, enumeration 'U' is mapped to "1000000000". @N:CD630 : PF_COREFIR.vhd(70) | Synthesizing work.pf_corefir.rtl. @W:CD276 : COREFIR.vhd(77) | Map for port coef_on_slot of component pf_corefir_pf_corefir_0_corefir_pf not found @W:CD730 : PF_COREFIR.vhd(168) | Component declaration has 15 ports but entity declares 16 ports @W:CD326 : PF_COREFIR.vhd(168) | Port coef_on_slot of entity corefir_pf_lib.pf_corefir_pf_corefir_0_corefir_pf is unconnected. If a port needs to remain unconnected, use the keyword open. @N:CD630 : COREFIR.vhd(32) | Synthesizing corefir_pf_lib.pf_corefir_pf_corefir_0_corefir_pf.rtl. @W:CD638 : COREFIR.vhd(130) | Signal readyi is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_fir_g5.vhd(33) | Synthesizing corefir_pf_lib.pf_corefir_pf_corefir_0_enum_fir_g5.rtl. @N:CD630 : enum_fir_adv_g5.vhd(54) | Synthesizing corefir_pf_lib.enum_fir_adv_g5.rtl. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_0 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_2 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_3 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_4 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_5 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_6 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_7 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_8 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_9 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_10 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_11 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_12 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_13 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_14 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_15 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_16 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_17 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_18 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_19 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(228) | Signal row_taps_array_dbg_20 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(229) | Signal cin_w_dbg_1 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(229) | Signal cin_w_dbg_2 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(232) | Signal p_w_1 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(234) | Signal ddly_symm_0 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(235) | Signal ddly_forw_test is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(236) | Signal ddly_symm_test is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(241) | Signal coef_on_tick_minus is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(242) | Signal coefi_valid_tick_minus is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_fir_adv_g5.vhd(244) | Signal coefi_dly is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_fir_adv_g5.vhd(475) | Synthesizing corefir_pf_lib.enum_g5_latency_adv.rtl. @N:CD630 : enum_kit.vhd(297) | Synthesizing corefir_pf_lib.enum_kitcounts.rtl. Post processing for corefir_pf_lib.enum_kitcounts.rtl Running optimization stage 1 on enum_kitCountS ....... @N:CD630 : enum_kit.vhd(42) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg.rtl Running optimization stage 1 on enum_kitDelay_bit_reg ....... @N:CD630 : enum_kit.vhd(386) | Synthesizing corefir_pf_lib.enum_kitedge.rtl. Post processing for corefir_pf_lib.enum_kitedge.rtl Running optimization stage 1 on enum_kitEdge ....... @N:CD630 : enum_kit.vhd(42) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg.rtl Running optimization stage 1 on enum_kitDelay_bit_reg ....... Post processing for corefir_pf_lib.enum_g5_latency_adv.rtl Running optimization stage 1 on enum_g5_latency_adv ....... @N:CD630 : adv_dly_line.vhd(35) | Synthesizing corefir_pf_lib.enum_dly_line_18x192.rtl. @W:CD638 : adv_dly_line.vhd(78) | Signal rstnn is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_kit.vhd(91) | Synthesizing corefir_pf_lib.enum_kitdelay_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_reg.rtl Running optimization stage 1 on enum_kitDelay_reg ....... @N:CD630 : adv_dly_line.vhd(147) | Synthesizing corefir_pf_lib.enum_uram_shift_reg_18x192.rtl. @N:CD630 : adv_dly_line.vhd(271) | Synthesizing corefir_pf_lib.uram_wrap.rtl. @W:CD638 : adv_dly_line.vhd(378) | Signal din12 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : adv_dly_line.vhd(379) | Signal dout12 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : adv_dly_line.vhd(382) | Signal ra64 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : adv_dly_line.vhd(383) | Signal wa64 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : adv_dly_line.vhd(386) | Signal ra192 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : adv_dly_line.vhd(387) | Signal wa192 is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : adv_dly_line.vhd(1337) | Synthesizing corefir_pf_lib.g5_uram18x128.def_arch. Post processing for corefir_pf_lib.g5_uram18x128.def_arch Running optimization stage 1 on g5_uram18x128 ....... Post processing for corefir_pf_lib.uram_wrap.rtl Running optimization stage 1 on uram_wrap ....... @N:CD630 : enum_kit.vhd(297) | Synthesizing corefir_pf_lib.enum_kitcounts.rtl. Post processing for corefir_pf_lib.enum_kitcounts.rtl Running optimization stage 1 on enum_kitCountS ....... Post processing for corefir_pf_lib.enum_uram_shift_reg_18x192.rtl Running optimization stage 1 on enum_uram_shift_reg_18x192 ....... Post processing for corefir_pf_lib.enum_dly_line_18x192.rtl Running optimization stage 1 on enum_dly_line_18x192 ....... @N:CD630 : enum_row_g5.vhd(39) | Synthesizing corefir_pf_lib.enum_row_g5.rtl. @N:CD630 : enum_kit.vhd(91) | Synthesizing corefir_pf_lib.enum_kitdelay_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_reg.rtl Running optimization stage 1 on enum_kitDelay_reg ....... @N:CD630 : enum_kit.vhd(153) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg_attr.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg_attr.rtl Running optimization stage 1 on enum_kitDelay_bit_reg_attr ....... @N:CD630 : enum_kit.vhd(204) | Synthesizing corefir_pf_lib.enum_kitdelay_reg_attr.rtl. Post processing for corefir_pf_lib.enum_kitdelay_reg_attr.rtl Running optimization stage 1 on enum_kitDelay_reg_attr ....... @N:CD630 : enum_kit.vhd(153) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg_attr.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg_attr.rtl Running optimization stage 1 on enum_kitDelay_bit_reg_attr ....... @N:CD630 : enum_nibble_g5.vhd(37) | Synthesizing corefir_pf_lib.enum_tap_nibble.rtl. @N:CD630 : enum_undernibble_g5.vhd(367) | Synthesizing corefir_pf_lib.enum_tap_undernibble_3.rtl. @W:CD638 : enum_undernibble_g5.vhd(481) | Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_undernibble_g5.vhd(482) | Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_tap_g5.vhd(34) | Synthesizing corefir_pf_lib.enum_tap_g5.rtl. @W:CD638 : enum_tap_g5.vhd(127) | Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_tap_g5.vhd(132) | Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_macc_lib_g5.vhd(117) | Synthesizing corefir_pf_lib.macc_pa_bc_rom_wrap.rtl. Running optimization stage 1 on MACC_PA_BC_ROM ....... Post processing for corefir_pf_lib.macc_pa_bc_rom_wrap.rtl Running optimization stage 1 on MACC_PA_BC_ROM_wrap ....... @N:CD630 : enum_kit.vhd(434) | Synthesizing corefir_pf_lib.debug_init.rtl. @W:CD286 : enum_kit.vhd(434) | Creating black box for empty architecture debug_INIT Post processing for corefir_pf_lib.debug_init.rtl Running optimization stage 1 on debug_INIT ....... Post processing for corefir_pf_lib.enum_tap_g5.rtl Running optimization stage 1 on enum_tap_g5 ....... @N:CD630 : enum_kit.vhd(434) | Synthesizing corefir_pf_lib.debug_init.rtl. @W:CD286 : enum_kit.vhd(434) | Creating black box for empty architecture debug_INIT Post processing for corefir_pf_lib.debug_init.rtl Running optimization stage 1 on debug_INIT ....... Post processing for corefir_pf_lib.enum_tap_undernibble_3.rtl Running optimization stage 1 on enum_tap_undernibble_3 ....... @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 0 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 1 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 2 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 3 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 4 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 5 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 6 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 7 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 8 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 9 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 10 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 11 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 12 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 13 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 14 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 15 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 16 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 17 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 14 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 15 of signal coef_w_8 is floating -- simulation mismatch possible. Post processing for corefir_pf_lib.enum_tap_nibble.rtl Running optimization stage 1 on enum_tap_nibble ....... @N:CD630 : enum_nibble_g5.vhd(37) | Synthesizing corefir_pf_lib.enum_tap_nibble.rtl. @N:CD630 : enum_undernibble_g5.vhd(367) | Synthesizing corefir_pf_lib.enum_tap_undernibble_3.rtl. @W:CD638 : enum_undernibble_g5.vhd(481) | Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_undernibble_g5.vhd(482) | Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_tap_g5.vhd(34) | Synthesizing corefir_pf_lib.enum_tap_g5.rtl. @W:CD638 : enum_tap_g5.vhd(127) | Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_tap_g5.vhd(129) | Signal symm_data18 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_tap_g5.vhd(132) | Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration. Post processing for corefir_pf_lib.enum_tap_g5.rtl Running optimization stage 1 on enum_tap_g5 ....... @W:CL245 : enum_tap_g5.vhd(181) | Bit 0 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 1 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 2 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 3 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 4 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 5 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 6 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 7 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 8 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 9 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 10 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 11 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 12 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 13 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 14 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 15 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 16 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. @W:CL245 : enum_tap_g5.vhd(181) | Bit 17 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level. Post processing for corefir_pf_lib.enum_tap_undernibble_3.rtl Running optimization stage 1 on enum_tap_undernibble_3 ....... @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 0 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 1 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 2 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 3 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 4 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 5 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 6 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 7 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 8 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 9 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 10 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 11 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 12 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 13 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 14 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 15 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 16 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 17 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 14 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 15 of signal coef_w_8 is floating -- simulation mismatch possible. Post processing for corefir_pf_lib.enum_tap_nibble.rtl Running optimization stage 1 on enum_tap_nibble ....... @N:CD630 : enum_nibble_g5.vhd(37) | Synthesizing corefir_pf_lib.enum_tap_nibble.rtl. @N:CD630 : enum_undernibble_g5.vhd(367) | Synthesizing corefir_pf_lib.enum_tap_undernibble_3.rtl. @W:CD638 : enum_undernibble_g5.vhd(481) | Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_undernibble_g5.vhd(482) | Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration. @N:CD630 : enum_tap_g5.vhd(34) | Synthesizing corefir_pf_lib.enum_tap_g5.rtl. @W:CD638 : enum_tap_g5.vhd(127) | Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration. @W:CD638 : enum_tap_g5.vhd(132) | Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration. Post processing for corefir_pf_lib.enum_tap_g5.rtl Running optimization stage 1 on enum_tap_g5 ....... Post processing for corefir_pf_lib.enum_tap_undernibble_3.rtl Running optimization stage 1 on enum_tap_undernibble_3 ....... @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 0 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 1 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 2 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 3 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 4 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 5 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 6 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 7 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 8 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 9 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 10 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 11 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 12 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 13 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 14 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 15 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 16 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(481) | Bit 17 of signal data_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible. @W:CL252 : enum_undernibble_g5.vhd(482) | Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible. Only the first 100 messages of id 'CL252' are reported. To see all messages use 'report_messages -log C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\synthesis\synlog\top_compiler.srr -id CL252' in the Tcl shell. To see all messages in future runs, use the command 'message_override -limit {CL252} -count unlimited' in the Tcl shell. Post processing for corefir_pf_lib.enum_tap_nibble.rtl Running optimization stage 1 on enum_tap_nibble ....... @N:CD630 : enum_kit.vhd(434) | Synthesizing corefir_pf_lib.debug_init.rtl. @W:CD286 : enum_kit.vhd(434) | Creating black box for empty architecture debug_INIT Post processing for corefir_pf_lib.debug_init.rtl Running optimization stage 1 on debug_INIT ....... Post processing for corefir_pf_lib.enum_row_g5.rtl Running optimization stage 1 on enum_row_g5 ....... @N:CD630 : enum_pad_g5.vhd(46) | Synthesizing corefir_pf_lib.enum_pad_g5.rtl. @N:CD630 : enum_kit.vhd(91) | Synthesizing corefir_pf_lib.enum_kitdelay_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_reg.rtl Running optimization stage 1 on enum_kitDelay_reg ....... @N:CD630 : enum_kit.vhd(42) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg.rtl Running optimization stage 1 on enum_kitDelay_bit_reg ....... Post processing for corefir_pf_lib.enum_pad_g5.rtl Running optimization stage 1 on enum_pad_g5 ....... @N:CD630 : enum_kit.vhd(42) | Synthesizing corefir_pf_lib.enum_kitdelay_bit_reg.rtl. Post processing for corefir_pf_lib.enum_kitdelay_bit_reg.rtl Running optimization stage 1 on enum_kitDelay_bit_reg ....... Post processing for corefir_pf_lib.enum_fir_adv_g5.rtl Running optimization stage 1 on enum_fir_adv_g5 ....... Post processing for corefir_pf_lib.pf_corefir_pf_corefir_0_enum_fir_g5.rtl Running optimization stage 1 on PF_COREFIR_PF_COREFIR_0_enum_fir_g5 ....... Post processing for corefir_pf_lib.pf_corefir_pf_corefir_0_corefir_pf.rtl Running optimization stage 1 on PF_COREFIR_PF_COREFIR_0_COREFIR_PF ....... Post processing for work.pf_corefir.rtl Running optimization stage 1 on PF_COREFIR ....... Running optimization stage 2 on enum_kitDelay_bit_reg_5 ....... Running optimization stage 2 on enum_kitDelay_bit_reg_2 ....... Running optimization stage 2 on enum_kitDelay_reg_16_7 ....... @N:CL135 : enum_kit.vhd(116) | Found sequential shift delayLine with address depth of 7 words and data bit width of 16. Running optimization stage 2 on enum_pad_g5_3_2_2_1_1_0_16_0_16 ....... @N:CL159 : enum_pad_g5.vhd(68) | Input coef_sel is unused. Running optimization stage 2 on debug_INIT_1024 ....... Running optimization stage 2 on enum_tap_g5_work_pf_corefir_rtl_2layer1 ....... @N:CL159 : enum_tap_g5.vhd(62) | Input coef_sel is unused. Running optimization stage 2 on enum_tap_undernibble_3_work_pf_corefir_rtl_2layer1 ....... Running optimization stage 2 on enum_tap_nibble_work_pf_corefir_rtl_0layer1 ....... Running optimization stage 2 on enum_tap_g5_work_pf_corefir_rtl_1layer1 ....... @N:CL159 : enum_tap_g5.vhd(57) | Input symm_datai is unused. @N:CL159 : enum_tap_g5.vhd(62) | Input coef_sel is unused. Running optimization stage 2 on enum_tap_undernibble_3_work_pf_corefir_rtl_1layer1 ....... Running optimization stage 2 on enum_tap_nibble_work_pf_corefir_rtl_1layer1 ....... Running optimization stage 2 on debug_INIT_128 ....... Running optimization stage 2 on debug_INIT_16 ....... Running optimization stage 2 on MACC_PA_BC_ROM ....... Running optimization stage 2 on MACC_PA_BC_ROM_wrap_work_pf_corefir_rtl_0layer1 ....... @N:CL159 : enum_macc_lib_g5.vhd(136) | Input nGrst_B2 is unused. Running optimization stage 2 on enum_tap_g5_work_pf_corefir_rtl_0layer1 ....... @N:CL159 : enum_tap_g5.vhd(62) | Input coef_sel is unused. Running optimization stage 2 on enum_tap_undernibble_3_work_pf_corefir_rtl_0layer1 ....... Running optimization stage 2 on enum_tap_nibble_work_pf_corefir_rtl_2layer1 ....... Running optimization stage 2 on enum_kitDelay_bit_reg_attr_3 ....... Running optimization stage 2 on enum_kitDelay_reg_attr_16_1 ....... Running optimization stage 2 on enum_kitDelay_bit_reg_attr_2 ....... Running optimization stage 2 on enum_kitDelay_reg_48_2 ....... Running optimization stage 2 on enum_row_g5_work_pf_corefir_rtl_0layer1 ....... Running optimization stage 2 on enum_kitCountS_7_122_1 ....... Running optimization stage 2 on g5_uram18x128 ....... Running optimization stage 2 on uram_wrap_123_16_7 ....... Running optimization stage 2 on enum_uram_shift_reg_18x192_16_123 ....... Running optimization stage 2 on enum_kitDelay_reg_16_1 ....... Running optimization stage 2 on enum_dly_line_18x192_16_124_1_512 ....... Running optimization stage 2 on enum_kitDelay_bit_reg_3 ....... Running optimization stage 2 on enum_kitEdge_1 ....... Running optimization stage 2 on enum_kitDelay_bit_reg_7 ....... Running optimization stage 2 on enum_kitCountS_7_64_1 ....... Running optimization stage 2 on enum_g5_latency_adv_64_1_3_2_2_2_64 ....... Running optimization stage 2 on enum_fir_adv_g5_work_pf_corefir_rtl_0layer1 ....... Running optimization stage 2 on PF_COREFIR_PF_COREFIR_0_enum_fir_g5_1_127_1_1_1_0_16_0_16_512_0_3_2_2_1_1_1_4_2 ....... Running optimization stage 2 on PF_COREFIR_PF_COREFIR_0_COREFIR_PF_work_pf_corefir_rtl_0layer1 ....... @N:CL159 : COREFIR.vhd(73) | Input COEF_REF is unused. @N:CL159 : COREFIR.vhd(76) | Input RCLK is unused. Running optimization stage 2 on PF_COREFIR ....... For a summary of runtime and memory usage per design unit, please see file: ========================================================== Linked File: layer1.rt.csv At c_vhdl Exit (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 191MB peak: 192MB) Process completed successfully. # Wed Jan 13 10:54:09 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode @W:Z198 : enum_fir_g5.vhd(171) | Unbound component debug_INIT_1024 of instance debug_init_0 @W:Z198 : enum_fir_adv_g5.vhd(255) | Unbound component debug_INIT_1024 of instance debug_init_0 @W:Z198 : enum_row_g5.vhd(185) | Unbound component debug_INIT_1024 of instance debug_init_0 @W:Z198 : enum_nibble_g5.vhd(260) | Unbound component debug_INIT_128 of instance debug_init_0 @W:Z198 : enum_undernibble_g5.vhd(493) | Unbound component debug_INIT_128 of instance debug_init_0 @W:Z198 : enum_tap_g5.vhd(151) | Unbound component debug_INIT_16 of instance debug_init_0 @W:Z198 : enum_macc_lib_g5.vhd(239) | Unbound component MACC_PA_BC_ROM of instance MACC_PA_BC_ROM_0 @W:Z198 : enum_tap_g5.vhd(151) | Unbound component debug_INIT_16 of instance debug_init_0 @W:Z198 : enum_nibble_g5.vhd(260) | Unbound component debug_INIT_128 of instance debug_init_0 @W:Z198 : enum_undernibble_g5.vhd(493) | Unbound component debug_INIT_128 of instance debug_init_0 @W:Z198 : enum_tap_g5.vhd(151) | Unbound component debug_INIT_16 of instance debug_init_0 @W:Z198 : enum_nibble_g5.vhd(260) | Unbound component debug_INIT_128 of instance debug_init_0 @W:Z198 : enum_undernibble_g5.vhd(493) | Unbound component debug_INIT_128 of instance debug_init_0 ======================================================================================= For a summary of linker messages for components that did not bind, please see log file: Linked File: top_comp.linkerlog ======================================================================================= At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 118MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jan 13 10:54:10 2021 ###########################################################] For a summary of runtime and memory usage for all design units, please see file: ========================================================== Linked File: top_comp.rt.csv @END At c_hdl Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:18s; Memory used current: 24MB peak: 25MB) Process took 0h:00m:18s realtime, 0h:00m:18s cputime Process completed successfully. # Wed Jan 13 10:54:10 2021 ###########################################################] ###########################################################[ Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Synopsys Netlist Linker, Version comp202003synp2, Build 166R, Built Oct 19 2020 10:50:56, @ @N: : | Running in 64-bit mode At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 123MB peak: 123MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime Process completed successfully. # Wed Jan 13 10:54:11 2021 ###########################################################] Premap Report # Wed Jan 13 10:54:12 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Pre-mapping, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) Reading constraint file: C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\designer\top\synthesis.fdc Linked File: top_scck.rpt See clock summary report "C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\synthesis\top_scck.rpt" @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 159MB peak: 159MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 159MB peak: 159MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 159MB peak: 159MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 159MB peak: 161MB) @N:FX1171 : filter_control_fsm.v(98) | Found instance PF_DSP_FLOW_DEMO_TOP_0.FILTERCONTROL_FSM_0.FFT_I_VALID with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : filter_control_fsm.v(98) | Found instance PF_DSP_FLOW_DEMO_TOP_0.FILTERCONTROL_FSM_0.COEF_RD_ENABLE with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : filter_control_fsm.v(98) | Found instance PF_DSP_FLOW_DEMO_TOP_0.FILTERCONTROL_FSM_0.FILTER_COMPLETE with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : filter_control_fsm.v(98) | Found instance PF_DSP_FLOW_DEMO_TOP_0.FILTERCONTROL_FSM_0.COEF_ON with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : filter_control_fsm.v(98) | Found instance PF_DSP_FLOW_DEMO_TOP_0.FILTERCONTROL_FSM_0.FIR_WR_ENABLE with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:BN132 : fftsm.v(675) | Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. @N:FX1171 : kit.v(599) | Found instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.autoScale_0.bflyMonitor with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : kit.v(599) | Found instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.autoScale_0.ldMonitor with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.rx_en with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.RAM_REN with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.WDATA[15:0] with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.OEN with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.SEL with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.WEN with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @N:FX1171 : uart_if.v(186) | Found instance PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.COEF_WEN with reset/set having higher priority than enable. Selected technology supports register with enable having higher priority than reset/set. Adding glue logic to resolve priority. @W:FX1172 : enum_kit.vhd(65) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.dvalid_pipe_3.delayLine[0:4] is being ignored due to limitations in architecture. @W:FX1172 : enum_kit.vhd(65) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.enum_pad_g5_0.reload_pad.dvalid_pipe_2.delayLine[0:1] is being ignored due to limitations in architecture. @W:FX1183 : enum_kit.vhd(116) | User-specified initial value set for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.enum_pad_g5_0.reload_coef_pad.symm_data_pipe_0.delayLine[15:0] cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @W:FX1172 : enum_kit.vhd(116) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.many_tap_nibble.many_tap_nibble_0.left_tap_0.reload_shift_reg.shiftreg_section_0.delayLine_0[15:0] is being ignored due to limitations in architecture. @W:BN114 : enum_tap_g5.vhd(151) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances. @W:BN114 : enum_tap_g5.vhd(151) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances. @W:BN114 : enum_undernibble_g5.vhd(493) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:FX1172 : enum_kit.vhd(232) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.symm_data_pad.symm_data_pipe_0.delayLine_0[15:0] is being ignored due to limitations in architecture. @W:FX1172 : enum_kit.vhd(178) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.valid_pipe_0.delayLine[0:2] is being ignored due to limitations in architecture. @W:BN114 : enum_nibble_g5.vhd(260) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:BN114 : enum_tap_g5.vhd(151) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances. @W:BN114 : enum_undernibble_g5.vhd(493) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:BN114 : enum_nibble_g5.vhd(260) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:BN114 : enum_undernibble_g5.vhd(493) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:BN114 : enum_nibble_g5.vhd(260) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances. @W:FX1172 : enum_kit.vhd(178) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.valid_pipe_0.delayLine[0:1] is being ignored due to limitations in architecture. @W:FX1172 : enum_kit.vhd(116) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.inter_advanced.end_dly_0.delayLine_1[47:0] is being ignored due to limitations in architecture. @W:FX1172 : enum_kit.vhd(116) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.inter_advanced.end_dly_0.delayLine_0[47:0] is being ignored due to limitations in architecture. @W:BN114 : enum_row_g5.vhd(185) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_row_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances. @W:FX1172 : enum_kit.vhd(65) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.latency_0.async2sync_0.delayLine[0:2] is being ignored due to limitations in architecture. @W:FX1172 : enum_kit.vhd(65) | User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.latency_0.shift_reg_1.delayLine[0:6] is being ignored due to limitations in architecture. @W:BN114 : enum_fir_adv_g5.vhd(255) | Removing instance debug_init_0 (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances. @W:BN114 : enum_fir_g5.vhd(171) | Removing instance debug_init_0 (in view: corefir_pf_lib.PF_COREFIR_PF_COREFIR_0_enum_fir_g5_1_127_1_1_1_0_16_0_16_512_0_3_2_2_1_1_1_4_2(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances. @W:BN114 : pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v(51) | Removing instance vcc_inst (in view: work.PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR(verilog)) of black box view:work.VCC(verilog) because it does not drive other instances. @W:BN114 : pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v(52) | Removing instance gnd_inst (in view: work.PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR(verilog)) of black box view:work.GND(verilog) because it does not drive other instances. @W:FX1183 : corereset_pf.v(58) | User-specified initial value set for instance reset_sync_0.reset_sync_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. @N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) has its enable tied to GND. @N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) on net RFS (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) has its enable tied to GND. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_1(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_1(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_1(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_0(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_3(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_0(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_2(verilog) because it does not drive other instances. @N:BN115 : cmplx.v(407) | Removing instance signExt_p (in view: COREFFT_LIB.fft_inpl_half_cmplx_18_16s_1s_0s_26s_48s_1_0s(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_48s_33s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_3(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_4(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_3(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_0(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(130) | Removing instance signExt_a (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_2(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_6(verilog) because it does not drive other instances. @N:BN115 : mac_lib.v(132) | Removing instance signExt_b (in view: COREFFT_LIB.fft_inpl_mac18x18mx_16s_16s_0s_0s_0s_26s_0_0_0_48s_2(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_16s_18s_0s_1_5(verilog) because it does not drive other instances. @N:BN115 : cmplx.v(407) | Removing instance signExt_p (in view: COREFFT_LIB.fft_inpl_half_cmplx_18_16s_0s_0s_26s_48s_0_0s(verilog)) of type view:COREFFT_LIB.fft_inpl_signExt_48s_33s_0s_1(verilog) because it does not drive other instances. @N:BN362 : corefft.v(229) | Removing sequential instance buf_ready_r (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN115 : enum_row_g5.vhd(452) | Removing instance inter_advanced\.end_dly_0 (in view: corefir_pf_lib.enum_row_g5_work_pf_corefir_rtl_0layer1(rtl)) of type view:corefir_pf_lib.enum_kitDelay_reg_48_2(rtl) because it does not drive other instances. @N:BN362 : rx_async.v(501) | Removing sequential instance fifo_write (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffs(prim) because it does not drive other instances. @N:BN362 : rx_async.v(501) | Removing sequential instance clear_parity_en (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : fftsm.v(675) | Removing sequential instance swCross (in view: COREFFT_LIB.fft_inpl_inBuf_fftA_pipe_8_3_0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : fftsm.v(265) | Removing sequential instance fftRd_done_tick (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : corefft.v(229) | Removing sequential instance datao_valid_r (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : rx_async.v(206) | Removing sequential instance overflow (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : rx_async.v(447) | Removing sequential instance parity_err (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : rx_async.v(231) | Removing sequential instance framing_error (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN115 : fftsm.v(582) | Removing instance bit_dly_1 (in view: COREFFT_LIB.fft_inpl_outBufA_256s_8_1s(verilog)) of type view:COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[2\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : enum_fir_adv_g5.vhd(581) | Removing sequential instance datao_validi (in view: corefir_pf_lib.enum_g5_latency_adv_64_1_3_2_2_2_64(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[1\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : rx_async.v(286) | Removing sequential instance overflow_int (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : rx_async.v(286) | Removing sequential instance framing_error_int (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : kit.v(203) | Removing sequential instance genblk1\.delayLine\[0\] (in view: COREFFT_LIB.fft_inpl_kitDelay_bit_reg_3s_1(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN115 : enum_fir_adv_g5.vhd(565) | Removing instance syst_counter_0 (in view: corefir_pf_lib.enum_g5_latency_adv_64_1_3_2_2_2_64(rtl)) of type view:corefir_pf_lib.enum_kitCountS_7_64_1(rtl) because it does not drive other instances. @N:BN115 : enum_fir_adv_g5.vhd(553) | Removing instance shift_reg_1 (in view: corefir_pf_lib.enum_g5_latency_adv_64_1_3_2_2_2_64(rtl)) of type view:corefir_pf_lib.enum_kitDelay_bit_reg_7(rtl) because it does not drive other instances. @N:BN362 : enum_kit.vhd(65) | Removing sequential instance delayLine[0:6] (in view: corefir_pf_lib.enum_kitDelay_bit_reg_7(rtl)) of type view:PrimLib.dffre(prim) because it does not drive other instances. @N:BN362 : enum_fir_adv_g5.vhd(540) | Removing sequential instance init_rst (in view: corefir_pf_lib.enum_g5_latency_adv_64_1_3_2_2_2_64(rtl)) of type view:PrimLib.dffse(prim) because it does not drive other instances. @N:FX1184 : | Applying syn_allowed_resources blockrams=952 on top level netlist top Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 229MB peak: 229MB) Clock Summary ****************** Start Requested Requested Clock Clock Clock Level Clock Frequency Period Type Group Load --------------------------------------------------------------------------------------------------------------------------------------------------- 0 - REF_CLK_0 50.0 MHz 20.000 declared default_clkgroup 1 1 . PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 200.0 MHz 5.000 generated (from REF_CLK_0) default_clkgroup 2728 0 - System 100.0 MHz 10.000 system system_clkgroup 0 0 - fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 10.000 inferred Inferred_clkgroup_0 22 =================================================================================================================================================== Clock Load Summary *********************** Clock Source Clock Pin Non-clock Pin Non-clock Pin Clock Load Pin Seq Example Seq Example Comb Example -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- REF_CLK_0 1 REF_CLK_0(port) PF_ccc_0_0.PF_ccc_0_0.pll_inst_0.REF_CLK_0 - - PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 2728 PF_ccc_0_0.PF_ccc_0_0.pll_inst_0.OUT0(PLL) reset_sync_0.reset_sync_0.dff_0.C - PF_ccc_0_0.PF_ccc_0_0.clkint_0.I(BUFG) System 0 - - - - fft_inpl_slowClock|divider_inferred_clock[2] 22 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2:0].Q[2](dffr) PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0.W_CLK - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.slowClk.I[0](inv) ============================================================================================================================================================================================================================================================================================================================================================================================================================================================== @W:MT530 : kit.v(203) | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 22 sequential elements including PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\]. This clock has no specified timing constraint which may adversely impact design performance. @N:FX1143 : | Skipping assigning INTERNAL_VREF to iobanks, because the table of mapping from pin to iobank is not initialized. Finished Pre Mapping Phase. @N:BN225 : | Writing default property annotation file C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\synthesis\top.sap. Starting constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 213MB peak: 230MB) Encoding state machine xmit_state[5:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 Encoding state machine rx_state[3:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. Encoding state machine fsm[4:0] (in view: work.FILTERCONTROL_FSM(verilog)) original code -> new code 000 -> 00000 001 -> 00011 010 -> 00101 011 -> 01001 100 -> 10001 Encoding state machine rfsm[14:0] (in view: work.UART_IF(verilog)) original code -> new code 0000 -> 000000000000000 0001 -> 000000000000011 0010 -> 000000000000101 0011 -> 000000000001001 0100 -> 000000000010001 0110 -> 000000000100001 0111 -> 000000001000001 1000 -> 000000010000001 1001 -> 000000100000001 1010 -> 000001000000001 1011 -> 000010000000001 1100 -> 000100000000001 1101 -> 001000000000001 1110 -> 010000000000001 1111 -> 100000000000001 Finished constraint checker preprocessing (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 218MB peak: 230MB) Finished constraint checker (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 220MB peak: 230MB) Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 133MB peak: 230MB) Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Wed Jan 13 10:54:15 2021 ###########################################################] Map & Optimize Report # Wed Jan 13 10:54:15 2021 Copyright (C) 1994-2020 Synopsys, Inc. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited. Tool: Synplify Pro (R) Build: Q-2020.03M-SP1 Install: C:\Microsemi\Libero_SoC_v12.6\SynplifyPro OS: Windows 6.2 Hostname: HYD-LT-I62935 Implementation : synthesis Synopsys Generic Technology Mapper, Version map202003act, Build 160R, Built Oct 22 2020 12:05:41, @ Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 118MB peak: 118MB) @N:MF916 : | Option synthesis_strategy=base is enabled. @N:MF248 : | Running in 64-bit mode. @N:MF667 : | Clock conversion disabled. (Command "set_option -fix_gated_and_generated_clocks 0" in the project file.) Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 120MB peak: 129MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 122MB peak: 129MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 124MB peak: 129MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 170MB peak: 170MB) @W:MO160 : rx_async.v(421) | Register bit rx_parity_calc (in view view:work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:MO111 : corefft_top.v(86) | Tristate driver OVFLOW_FLAG (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) on net OVFLOW_FLAG (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) has its enable tied to GND. @N:MO111 : corefft_top.v(86) | Tristate driver RFS (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) on net RFS (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_Z1_layer0(verilog)) has its enable tied to GND. @W:BN132 : kit.v(244) | Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_1.genblk1.dly_d.genblk1.delayLine[0][15:0] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.bfly_0.cmplx_0.genblk1.cmplx18_0.half_0.genblk1.dly_d.genblk1.delayLine[0][15:0]. To keep the instance, apply constraint syn_preserve=1 on the instance. Available hyper_sources - for debug and ip models None Found Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 183MB peak: 189MB) @N:MO231 : clock_gen.v(101) | Found counter in view:work.PF_COREUART_0_PF_COREUART_0_0_Clock_gen_1s_0s(verilog) instance genblk1\.baud_cntr[12:0] Encoding state machine xmit_state[5:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) original code -> new code 00000000000000000000000000000000 -> 000001 00000000000000000000000000000001 -> 000010 00000000000000000000000000000010 -> 000100 00000000000000000000000000000011 -> 001000 00000000000000000000000000000100 -> 010000 00000000000000000000000000000101 -> 100000 @W:MO160 : tx_async.v(119) | Register bit xmit_state[4] (in view view:work.PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @N:BN362 : tx_async.v(339) | Removing sequential instance tx_parity (in view: work.PF_COREUART_0_PF_COREUART_0_0_Tx_async_0s_0s_0s_1s_2s_3s_4s_5s_6s(verilog)) because it does not drive other instances. Encoding state machine rx_state[3:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 @N:MO225 : rx_async.v(286) | There are no possible illegal states for state machine rx_state[3:0] (in view: work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)); safe FSM implementation is not required. @W:MO161 : rx_async.v(261) | Register bit last_bit[3] (in view view:work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 1. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : rx_async.v(261) | Register bit last_bit[2] (in view view:work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. @W:MO160 : rx_async.v(261) | Register bit last_bit[1] (in view view:work.PF_COREUART_0_PF_COREUART_0_0_Rx_async_0s_0s_0s_1s_2s_3s(verilog)) is always 0. To keep the instance, apply syn_preserve=1 on the instance. Encoding state machine fsm[4:0] (in view: work.FILTERCONTROL_FSM(verilog)) original code -> new code 000 -> 00000 001 -> 00011 010 -> 00101 011 -> 01001 100 -> 10001 @N:MO231 : filter_control_fsm.v(98) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance COEF_RADDR[6:0] @N:MO231 : filter_control_fsm.v(98) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FFT_WADDR[7:0] @N:MO231 : filter_control_fsm.v(98) | Found counter in view:work.FILTERCONTROL_FSM(verilog) instance FIR_WR_ADDR[9:0] @N:FX493 : | Applying initial value "0" on instance fsm_i[0]. @N:MO231 : kit.v(111) | Found counter in view:COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog) instance wTimer_0.Q[6:0] @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[1\][3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[1\][4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[1\][9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[0\][3] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rStage_dly2.genblk1\.delayLine\[0\][4] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][7] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][8] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:BN362 : kit.v(244) | Removing sequential instance rTimer_dly2.genblk1\.delayLine\[0\][9] (in view: COREFFT_LIB.fft_inpl_sm_top_256s_128s_8_3_10s_1s(verilog)) of type view:PrimLib.dffr(prim) because it does not drive other instances. @N:MO231 : kit.v(139) | Found counter in view:COREFFT_LIB.fft_inpl_counter_w_10_137s(verilog) instance Q[9:0] @N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_5_7(verilog) instance Q[4:0] @N:MO231 : kit.v(79) | Found counter in view:COREFFT_LIB.fft_inpl_counter_8_255s(verilog) instance Q[7:0] @N:MO231 : kit.v(168) | Found counter in view:COREFFT_LIB.fft_inpl_twid_wA_gen_8_3(verilog) instance slowTimer.Q[6:0] Encoding state machine rfsm[14:0] (in view: work.UART_IF(verilog)) original code -> new code 0000 -> 000000000000000 0001 -> 000000000000011 0010 -> 000000000000101 0011 -> 000000000001001 0100 -> 000000000010001 0110 -> 000000000100001 0111 -> 000000001000001 1000 -> 000000010000001 1001 -> 000000100000001 1010 -> 000001000000001 1011 -> 000010000000001 1100 -> 000100000000001 1101 -> 001000000000001 1110 -> 010000000000001 1111 -> 100000000000001 @N:MO231 : uart_if.v(186) | Found counter in view:work.UART_IF(verilog) instance R_ADDR[10:0] @N:MO231 : uart_if.v(186) | Found counter in view:work.UART_IF(verilog) instance COEF_WADDR[7:0] @N:MO231 : uart_if.v(186) | Found counter in view:work.UART_IF(verilog) instance DATA_WADDR[10:0] @N:FX493 : | Applying initial value "0" on instance rfsm_i[0]. @N:MF135 : enum_kit.vhd(116) | RAM enum_pad_g5_0.data_pipe_0.delayLine_seqshift[15:0] (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) is 8 words by 16 bits. @N:MF135 : enum_kit.vhd(116) | RAM enum_pad_g5_0.reload_coef_pad\.symm_data_pipe_0.delayLine_seqshift[15:0] (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) is 8 words by 16 bits. @W:FX107 : enum_kit.vhd(116) | RAM enum_pad_g5_0.data_pipe_0.delayLine_seqshift[15:0] (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @W:FX107 : enum_kit.vhd(116) | RAM enum_pad_g5_0.reload_coef_pad\.symm_data_pipe_0.delayLine_seqshift[15:0] (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) does not have a read/write conflict check. Possible simulation mismatch. To resolve a read/write conflict, either set syn_ramstyle = rw_check, or enable the "Read Write Check on RAM" Implementation Option. For more information, search for "read/write conflict check" in Online Help. @N:MO231 : enum_kit.vhd(314) | Found counter in view:corefir_pf_lib.enum_kitCountS_7_122_1(rtl) instance count[6:0] Starting factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 192MB peak: 192MB) @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[3] (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0(verilog)) because it does not drive other instances. @N:BN362 : fftsm.v(439) | Removing sequential instance sm_0.rdFFTtimer_0.rStage_r[4] (in view: COREFFT_LIB.PF_COREFFT_PF_COREFFT_0_COREFFT_INPLC_Z2_layer0(verilog)) because it does not drive other instances. Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 197MB peak: 197MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 199MB peak: 199MB) @N:BN362 : rx_async.v(377) | Removing sequential instance PF_COREUART_0_0.PF_COREUART_0_0.make_RX.rx_shift[8] (in view: work.top(verilog)) because it does not drive other instances. Starting Early Timing Optimization (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:04s; Memory used current: 200MB peak: 200MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 200MB peak: 201MB) @W:BN132 : fftsm.v(675) | Removing instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.offsetPQ_r1[6] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. @W:BN132 : fftsm.v(675) | Removing instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.offsetPQ_r1[6] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_rA_0.mask1_r[5]. To keep the instance, apply constraint syn_preserve=1 on the instance. Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 200MB peak: 201MB) @N:MO106 : twiddle32.v(35) | Found ROM PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0[31:0] (in view: work.top(verilog)) with 64 words by 32 bits. @N:MO106 : twiddle32.v(35) | Found ROM PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00[31:0] (in view: work.top(verilog)) with 64 words by 32 bits. @N:BN362 : twiddle32.v(35) | Removing sequential instance G_294 (in view: work.top(verilog)) because it does not drive other instances. @N:BN362 : twiddle32.v(35) | Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_dreg[31:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. @N:BN362 : twiddle32.v(35) | Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_dreg[31:0] (in view: work.top(verilog)) of type view:PrimLib.dff(prim) because it does not drive other instances. Finished preparing to map (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 201MB peak: 201MB) Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 204MB peak: 204MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:07s 0.64ns 1714 / 2563 2 0h:00m:07s 0.64ns 1646 / 2563 @N:FP130 : | Promoting Net dff_arst on CLKINT I_476 @N:FP130 : | Promoting Net PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider_i_0[2] on CLKINT I_477 Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Added 0 Buffers Added 0 Cells via replication Added 0 Sequential Cells via replication Added 0 Combinational Cells via replication Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:08s; CPU Time elapsed 0h:00m:08s; Memory used current: 208MB peak: 208MB) Finished restoring hierarchy (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 219MB peak: 219MB) @S |Clock Optimization Summary #### START OF CLOCK OPTIMIZATION REPORT #####[ Clock optimization not enabled 1 non-gated/non-generated clock tree(s) driving 1 clock pin(s) of sequential element(s) 2 gated/generated clock tree(s) driving 2710 clock pin(s) of sequential element(s) 0 instances converted, 2710 sequential instances remain driven by gated/generated clocks ======================================= Non-Gated/Non-Generated Clocks ======================================= Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance -------------------------------------------------------------------------------------------------------------- ClockId0003 REF_CLK_0 clock definition on port 1 PF_ccc_0_0.PF_ccc_0_0.pll_inst_0 ============================================================================================================== ============================================================================================================================================== Gated/Generated Clocks =============================================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ClockId0001 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2] SLE 22 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.preRstAfterInit No gated clock conversion method for cell cell:ACG4.SLE ClockId0002 PF_ccc_0_0.PF_ccc_0_0.pll_inst_0 PLL 2688 reset_sync_0.reset_sync_0.dff_2 No gated clock conversion method for cell cell:ACG4.SLE ===================================================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Start Writing Netlists (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 166MB peak: 220MB) Writing Analyst data base C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\synthesis\synwork\top_m.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 217MB peak: 223MB) Writing Verilog Simulation files @N:BW103 : | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. @N:BW107 : | Synopsys Constraint File capacitance units using default value of 1pF @W:BW156 : | Option "-name" of set_clock_groups cannot be forward-annotated; there is no equivalent option in your place-and-route tool. Finished Writing Verilog Simulation files (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 216MB peak: 223MB) Start final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 218MB peak: 223MB) @W:MT246 : pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v(40) | Blackbox INIT is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @N:MT615 : | Found clock REF_CLK_0 with period 20.00ns @N:MT615 : | Found clock PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 with period 5.00ns @W:MT420 : | Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] with period 10.00ns. Please declare a user-defined clock on net PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.slowClock_0.divider[2]. ##### START OF TIMING REPORT #####[ # Timing report written on Wed Jan 13 10:54:29 2021 # Top view: top Requested Frequency: 50.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\designer\top\synthesis.fdc @N:MT320 : | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. @N:MT322 : | Clock constraints include only register-to-register paths associated with each individual clock. Performance Summary ******************* Worst slack in design: 0.998 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 200.0 MHz 249.9 MHz 5.000 4.002 0.998 generated (from REF_CLK_0) default_clkgroup REF_CLK_0 50.0 MHz NA 20.000 NA NA declared default_clkgroup fft_inpl_slowClock|divider_inferred_clock[2] 100.0 MHz 221.9 MHz 10.000 4.506 5.494 inferred Inferred_clkgroup_0 ===================================================================================================================================================================== Estimated period and frequency reported as NA means no slack depends directly on the clock waveform Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 | 5.000 0.998 | No paths - | No paths - | No paths - fft_inpl_slowClock|divider_inferred_clock[2] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 | No paths - | No paths - | No paths - | Diff grp - fft_inpl_slowClock|divider_inferred_clock[2] fft_inpl_slowClock|divider_inferred_clock[2] | No paths - | 10.000 5.494 | No paths - | No paths - ================================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[10] PF_FIR_OUT_BUF_R_DATA[8] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[11] PF_FIR_OUT_BUF_R_DATA[9] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[12] PF_FIR_OUT_BUF_R_DATA[10] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[13] PF_FIR_OUT_BUF_R_DATA[11] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[14] PF_FIR_OUT_BUF_R_DATA[12] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[15] PF_FIR_OUT_BUF_R_DATA[13] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[16] PF_FIR_OUT_BUF_R_DATA[14] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[17] PF_FIR_OUT_BUF_R_DATA[15] 3.023 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[0] PF_FIR_OUT_BUF_R_DATA[0] 3.023 1.042 PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM1K20 A_DOUT[1] PF_FIR_OUT_BUF_R_DATA[1] 3.023 1.042 ===================================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[0] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[0] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[1] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[1] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[2] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[2] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[3] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[3] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[4] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[4] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[5] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[5] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[6] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[6] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[7] PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 SLE D DATA_OUT_11[7] 5.000 0.998 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.enum_pad_g5_0.data_pipe_0.delayLine_seqshift_delayLine_seqshift_0_0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM64x12 W_DATA[0] PF_FIR_IN_BUF_R_DATA[0] 4.924 1.294 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5\.enum_fir_g5.adv_enum\.adv_enum_0.enum_pad_g5_0.reload_coef_pad\.symm_data_pipe_0.delayLine_seqshift_delayLine_seqshift_0_0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 RAM64x12 W_DATA[0] PF_COEF_BUF_R_DATA[0] 4.924 1.294 ============================================================================================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.000 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.000 - Propagation time: 4.002 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 0.998 Number of logic level(s): 3 Starting point: PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 / A_DOUT[10] Ending point: PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[0] / D The start point is clocked by PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin A_CLK The end point is clocked by PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 [rising] (rise=0.000 fall=2.500 period=5.000) on pin CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_DSP_FLOW_DEMO_TOP_0.PF_FIR_OUT_BUF.PF_TPSRAM_2_0.PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 RAM1K20 A_DOUT[10] Out 3.023 3.023 r - PF_FIR_OUT_BUF_R_DATA[8] Net - - 0.118 - 1 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11_0_1[0] CFG3 B In - 3.141 r - PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11_0_1[0] CFG3 Y Out 0.083 3.224 r - DATA_OUT_11_0_1[0] Net - - 0.118 - 1 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11_0_2[0] CFG4 D In - 3.342 r - PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11_0_2[0] CFG4 Y Out 0.232 3.574 f - DATA_OUT_11_0_2[0] Net - - 0.118 - 1 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11[0] CFG4 D In - 3.692 f - PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT_11[0] CFG4 Y Out 0.192 3.884 f - DATA_OUT_11[0] Net - - 0.118 - 1 PF_DSP_FLOW_DEMO_TOP_0.UART_IF_0.DATA_OUT[0] SLE D In - 4.002 f - ==================================================================================================================================================================== Total path delay (propagation time + setup) of 4.002 is 3.530(88.2%) logic and 0.472(11.8%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ==================================== Detailed Report for Clock: fft_inpl_slowClock|divider_inferred_clock[2] ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[1] 0.201 5.494 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[2] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[2] 0.201 5.504 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[0] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[0] 0.218 6.107 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[4] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[4] 0.218 6.830 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[3] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[3] 0.218 6.842 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[5] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[5] 0.218 7.471 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[6] fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wA_w[6] 0.218 8.131 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.pulse fft_inpl_slowClock|divider_inferred_clock[2] SLE Q pulse 0.218 8.314 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.twid_wEn fft_inpl_slowClock|divider_inferred_clock[2] SLE Q twid_wEn_w 0.201 8.368 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.tick1 fft_inpl_slowClock|divider_inferred_clock[2] SLE Q tick1 0.218 9.458 =============================================================================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[1] twidData_w[12] 9.924 5.494 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[1] twidData_w[12] 9.924 5.494 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[6] twidData_w[28] 9.946 5.530 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[6] twidData_w[28] 9.946 5.530 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[7] twidData_w[7] 9.924 5.543 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[1] twidData_w[23] 9.924 5.543 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[7] twidData_w[7] 9.924 5.543 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[1] twidData_w[23] 9.924 5.543 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[5] twidData_w[5] 9.924 5.577 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1 fft_inpl_slowClock|divider_inferred_clock[2] RAM64x12 W_DATA[10] twidData_w[21] 9.924 5.577 ============================================================================================================================================================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.000 - Setup time: 0.076 + Clock delay at ending point: 0.000 (ideal) = Required time: 9.924 - Propagation time: 4.431 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 5.494 Number of logic level(s): 6 Starting point: PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] / Q Ending point: PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1 / W_DATA[1] The start point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] (rise=0.000 fall=5.000 period=10.000) on pin CLK The end point is clocked by fft_inpl_slowClock|divider_inferred_clock[2] [falling] (rise=0.000 fall=5.000 period=10.000) on pin W_CLK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.slowTimer.Q[1] SLE Q Out 0.201 0.201 f - twid_wA_w[1] Net - - 0.980 - 76 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_31_0_.m12 CFG2 B In - 1.181 f - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_31_0_.m12 CFG2 Y Out 0.084 1.265 r - m12 Net - - 0.773 - 22 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m148 CFG3 C In - 2.037 r - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m148 CFG3 Y Out 0.148 2.185 r - m148 Net - - 0.594 - 6 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m157_1 CFG3 C In - 2.780 r - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m157_1 CFG3 Y Out 0.132 2.912 f - m157_0 Net - - 0.124 - 2 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m277 CFG4 D In - 3.036 f - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_0_31_0_.m277 CFG4 Y Out 0.192 3.228 f - m277 Net - - 0.118 - 1 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_31_0_.m154 CFG4 D In - 3.345 f - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_00_31_0_.m154 CFG4 Y Out 0.192 3.537 f - T_1_0_Data0_12 Net - - 0.124 - 2 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_0_Or2_12 CFG3 C In - 3.661 f - PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.lut_0.T_1_0_Or2_12 CFG3 Y Out 0.145 3.807 f - twidData_w[12] Net - - 0.624 - 2 PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.twidLUT_1.twidLUT_0.PolarFire_uram\.uram_0.PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1 RAM64x12 W_DATA[1] In - 4.431 f - ============================================================================================================================================================================================================================= Total path delay (propagation time + setup) of 4.506 is 1.169(25.9%) logic and 3.337(74.1%) route. Path delay compensated for clock skew. Clock skew is added to clock-to-out value, and is subtracted from setup time value ##### END OF TIMING REPORT #####] Timing exceptions that could not be applied Finished final timing analysis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 219MB peak: 223MB) Finished timing report (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 219MB peak: 223MB) --------------------------------------- Resource Usage Report for top Mapping to part: mpf300tfcg1152-1 Cell usage: BANKEN 1 use CLKINT 3 uses INIT 1 use OR2 240 uses PLL 1 use CFG1 19 uses CFG2 243 uses CFG3 655 uses CFG4 321 uses Carry cells: ARI1 241 uses - used for arithmetic functions ARI1 51 uses - used for Wide-Mux implementation Total ARI1 292 uses Sequential Cells: SLE 2526 uses SLE_INIT 6 uses - used for Seqshift to URAM mapping Total SLE 2532 uses DSP Blocks: 68 of 924 (7%) MACC_PA: 4 Mults MACC_PA_BC_ROM: 64 Mults I/O ports: 4 I/O primitives: 4 INBUF 3 uses OUTBUF 1 use Global Clock Buffers: 3 RAM/ROM usage summary Total Block RAMs (RAM1K20) : 5 of 952 (0%) Block RAMs (RAM64x12) : 46 Block RAMs (RAM64x12) : 4 - RAMs inferred for SeqShift Total Block RAMs (RAM64x12) : 50 of 2772 (1%) Total LUTs: 1530 Extra resources required for RAM and MACC_PA interface logic during P&R: RAM64X12 Interface Logic : SLEs = 600; LUTs = 600; RAM1K20 Interface Logic : SLEs = 180; LUTs = 180; MACC_PA Interface Logic : SLEs = 144; LUTs = 144; MACC_PA_BC_ROM Interface Logic : SLEs = 2304; LUTs = 2304; Total number of SLEs after P&R: 2532 + 600 + 180 + 2448 = 5760; Total number of LUTs after P&R: 1530 + 600 + 180 + 2448 = 4758; Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 79MB peak: 223MB) Process took 0h:00m:14s realtime, 0h:00m:14s cputime # Wed Jan 13 10:54:30 2021 ###########################################################]