| Project Settings |
|---|
| Project Name | top_syn | Device Name | synthesis: Microchip PolarFire : MPF300T |
| Implementation Name | synthesis | Top Module | top |
| Retiming | 0 | Resource Sharing | 1 |
| Fanout Guide | 10000 | Disable I/O Insertion | 0 |
| Disable Sequential Optimizations | 0 | FSM Compiler | 1 |
| Run Status |
|---|
| Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
| (compiler) | Complete |
172 |
233 |
0 |
- |
00m:19s |
- |
1/13/2021
10:54:10 AM |
| (premap) | Complete |
54 |
28 |
0 |
0m:03s |
0m:03s |
230MB |
1/13/2021
10:54:15 AM |
| (fpga_mapper) | Complete |
50 |
13 |
0 |
0m:14s |
0m:14s |
223MB |
1/13/2021
10:54:30 AM |
| Multi-srs Generator |
Complete | | | | | | | 1/13/2021
10:54:11 AM |
| Area Summary |
|---|
| |
| Carry Cells | 292 |
Sequential Cells | 2532 |
| DSP Blocks
(dsp_used) | 68 |
I/O Cells | 4 |
| Global Clock Buffers | 3 |
RAM1K20
(v_ram) | 5 |
| RAM64x12
(v_ram) | 50 |
LUTs
(total_luts) | 1530 |
| Timing Summary |
|---|
|
| Clock Name | Req Freq | Est Freq | Slack |
|---|
| PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 | 200.0 MHz | 249.9 MHz | 0.998 |
| REF_CLK_0 | 50.0 MHz | NA | NA |
| fft_inpl_slowClock|divider_inferred_clock[2] | 100.0 MHz | 221.9 MHz | 5.494 |
| Optimizations Summary |
|---|
| Combined Clock Conversion | 1 / 2 |
| |
|