@W: BN132 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":65:4:65:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.dvalid_pipe_3.delayLine[0:4] is being ignored due to limitations in architecture. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":65:4:65:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.enum_pad_g5_0.reload_pad.dvalid_pipe_2.delayLine[0:1] is being ignored due to limitations in architecture. 
@W: FX1183 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":116:4:116:5|User-specified initial value set for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.enum_pad_g5_0.reload_coef_pad.symm_data_pipe_0.delayLine[15:0] cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":116:4:116:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.many_tap_nibble.many_tap_nibble_0.left_tap_0.reload_shift_reg.shiftreg_section_0.delayLine_0[15:0] is being ignored due to limitations in architecture. 
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":232:4:232:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.symm_data_pad.symm_data_pipe_0.delayLine_0[15:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":178:4:178:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.left_nibble_0.valid_pipe_0.delayLine[0:2] is being ignored due to limitations in architecture. 
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_g5_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_16(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_1layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_undernibble_3_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_tap_nibble_work_pf_corefir_rtl_2layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_128(rtl) because it does not drive other instances.
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":178:4:178:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.valid_pipe_0.delayLine[0:1] is being ignored due to limitations in architecture. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":116:4:116:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.inter_advanced.end_dly_0.delayLine_1[47:0] is being ignored due to limitations in architecture. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":116:4:116:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.rows.1.a_row.inter_advanced.end_dly_0.delayLine_0[47:0] is being ignored due to limitations in architecture. 
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_row_g5.vhd":185:2:185:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_row_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances.
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":65:4:65:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.latency_0.async2sync_0.delayLine[0:2] is being ignored due to limitations in architecture. 
@W: FX1172 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_kit.vhd":65:4:65:5|User-specified initial value defined for instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFIR_0.PF_COREFIR_0.enum_g5.enum_fir_g5.adv_enum.adv_enum_0.latency_0.shift_reg_1.delayLine[0:6] is being ignored due to limitations in architecture. 
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_fir_adv_g5.vhd":255:2:255:13|Removing instance debug_init_0 (in view: corefir_pf_lib.enum_fir_adv_g5_work_pf_corefir_rtl_0layer1(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\work\pf_corefir\pf_corefir_0\rtl\vhdl\core\enum_pf\enum_fir_g5.vhd":171:2:171:13|Removing instance debug_init_0 (in view: corefir_pf_lib.PF_COREFIR_PF_COREFIR_0_enum_fir_g5_1_127_1_1_1_0_16_0_16_512_0_3_2_2_1_1_1_4_2(rtl)) of black box view:corefir_pf_lib.debug_INIT_1024(rtl) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":51:8:51:15|Removing instance vcc_inst (in view: work.PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR(verilog)) of black box view:work.VCC(verilog) because it does not drive other instances.
@W: BN114 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\work\pf_init_monitor_0\pf_init_monitor_0_0\pf_init_monitor_0_pf_init_monitor_0_0_pf_init_monitor.v":52:8:52:15|Removing instance gnd_inst (in view: work.PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR(verilog)) of black box view:work.GND(verilog) because it does not drive other instances.
@W: FX1183 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance reset_sync_0.reset_sync_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: MT530 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\kit.v":203:6:203:11|Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 22 sequential elements including PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\]. This clock has no specified timing constraint which may adversely impact design performance. 
