@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_ccc_0\PF_ccc_0_0\PF_ccc_0_PF_ccc_0_0_PF_CCC.v":39:12:39:21|Type of parameter VCOFREQUENCY on the instance pll_inst_0 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1340 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CG1340 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":268:0:268:5|Index into variable tx_byte could be out of range ; a simulation mismatch is possible.
@W: CL190 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Optimizing register bit fifo_read_en0 to a constant 1. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Tx_async.v":119:0:119:5|Pruning unused register fifo_read_en0. Make sure that there are no unused intermediate registers.
@W: CL177 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\Rx_async.v":501:0:501:5|Sharing sequential element clear_framing_error_en. Add a syn_preserve attribute to the element to prevent sharing.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":136:8:136:17|Object data_ready is declared but not assigned. Either assign a value or remove the declaration.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":376:0:376:5|Pruning unused register overflow_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":341:0:341:5|Pruning unused register rx_dout_reg_empty_q. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":326:0:326:5|Pruning unused register rx_dout_reg[7:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":293:0:293:5|Pruning unused register rx_state[1:0]. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":278:0:278:5|Pruning unused register clear_framing_error_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":263:0:263:5|Pruning unused register clear_parity_reg0. Make sure that there are no unused intermediate registers.
@W: CL169 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREUART_0\PF_COREUART_0_0\rtl\vlog\core\CoreUART.v":159:0:159:5|Pruning unused register fifo_write_tx. Make sure that there are no unused intermediate registers.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":502:7:502:15|Removing wire load_over, as there is no assignment to it.
@W: CL265 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":675:2:675:7|Removing unused bit 6 of mask1_r[6:0]. Either assign all bits or reduce the width of the signal.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":412:13:412:17|Object tick2 is declared but not assigned. Either assign a value or remove the declaration.
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":234:61:234:72|Removing instance wStage_dly_2 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CL168 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\fftSm.v":118:38:118:50|Removing instance edge_detect_0 because it does not drive other instances. To preserve this instance, use the syn_noprune synthesis directive.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":267:19:267:27|Object wA_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":268:19:268:27|Object wA_load_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:6:270:15|Object wEn_bfly_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:18:270:26|Object wEn_odd_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\fftDp.v":270:29:270:38|Object wEn_even_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:22:590:32|Object scale_exp_r is declared but not assigned. Either assign a value or remove the declaration.
@W: CG133 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":590:35:590:49|Object scale_exp_count is declared but not assigned. Either assign a value or remove the declaration.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":86:20:86:24|Removing wire outPQ, as there is no assignment to it.
@W: CG360 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT.v":87:16:87:24|Removing wire ctrl_outp, as there is no assignment to it.
@W: CL318 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:34:86:36|*Output RFS has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CL318 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFFT\PF_COREFFT_0\rtl\in_place\vlog\core\COREFFT_TOP.v":86:39:86:49|*Output OVFLOW_FLAG has undriven bits; assigning undriven bits to 'Z'.  Simulation mismatch possible. Assign all bits of the output.
@W: CG296 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v":135:8:135:13|Incomplete sensitivity list; assuming completeness. Make sure all referenced variables in message CG290 are included in the sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v":139:16:139:22|Referenced variable RAM_REN is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v":142:10:142:22|Referenced variable FIR_OUT_RDATA is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v":149:10:149:21|Referenced variable FFT_RE_RDATA is not in sensitivity list.
@W: CG290 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\hdl\UART_IF.v":156:10:156:21|Referenced variable FFT_IM_RDATA is not in sensitivity list.
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter FABRIC_POR_N_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter PCIE_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter SRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter UIC_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":40:53:40:58|Type of parameter USRAM_INIT_DONE_SIMULATION_DELAY on the instance I_INIT is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CG1283 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_init_monitor_0\PF_init_monitor_0_0\PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v":50:12:50:18|Type of parameter BANK_EN_SIMULATION_DELAY on the instance I_BEN_6 is not in accordance with the type of parameter on corresponding module. Please update RTL with correct parameter type 
@W: CL260 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":560:2:560:7|Pruning register bit 16 of outQ[31:0]. If this is not the intended behavior, drive the input with valid values, or an input from the top level.
@W: CL246 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFFT\7.1.100\rtl\in_place\vlog\core\kit.v":369:22:369:24|Input port bits 46 to 32 of inp[47:0] are unused. Assign logic for all port bits or change the input port size.
@W: CD276 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFIR\PF_COREFIR_0\rtl\vhdl\core\enum_PF\COREFIR.vhd":77:4:77:15|Map for port coef_on_slot of component pf_corefir_pf_corefir_0_corefir_pf not found
@W: CD730 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFIR\PF_COREFIR.vhd":168:0:168:11|Component declaration has 15 ports but entity declares 16 ports
@W: CD326 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFIR\PF_COREFIR.vhd":168:0:168:11|Port coef_on_slot of entity corefir_pf_lib.pf_corefir_pf_corefir_0_corefir_pf is unconnected. If a port needs to remain unconnected, use the keyword open.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\work\PF_COREFIR\PF_COREFIR_0\rtl\vhdl\core\enum_PF\COREFIR.vhd":130:9:130:14|Signal readyi is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_0 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_3 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_4 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_5 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_6 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_7 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_9 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_10 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_11 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_12 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_13 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_14 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_15 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_16 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_17 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_18 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_19 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":228:9:228:26|Signal row_taps_array_dbg_20 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":229:9:229:17|Signal cin_w_dbg_1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":229:9:229:17|Signal cin_w_dbg_2 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":232:9:232:11|Signal p_w_1 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":234:9:234:17|Signal ddly_symm_0 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":235:9:235:22|Signal ddly_forw_test is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":236:9:236:22|Signal ddly_symm_test is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":241:9:241:26|Signal coef_on_tick_minus is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":242:9:242:30|Signal coefi_valid_tick_minus is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_fir_adv_g5.vhd":244:9:244:17|Signal coefi_dly is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":78:9:78:13|Signal rstnn is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":378:9:378:13|Signal din12 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":379:9:379:14|Signal dout12 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":382:9:382:12|Signal ra64 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":383:9:383:12|Signal wa64 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":386:9:386:13|Signal ra192 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\adv_dly_line.vhd":387:9:387:13|Signal wa192 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":127:9:127:14|Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":132:9:132:26|Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD286 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_kit.vhd":434:7:434:16|Creating black box for empty architecture debug_INIT 
@W: CD286 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_kit.vhd":434:7:434:16|Creating black box for empty architecture debug_INIT 
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 0 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 1 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 2 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 3 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 4 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 5 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 6 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 7 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 8 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 9 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 10 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 11 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 12 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 13 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 14 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 15 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 16 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 17 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 14 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 15 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":127:9:127:14|Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":129:9:129:19|Signal symm_data18 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":132:9:132:26|Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 0 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 1 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 2 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 3 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 4 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 5 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 6 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 7 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 8 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 9 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 10 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 11 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 12 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 13 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 14 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 15 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 16 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL245 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":181:2:181:22|Bit 17 of input d of instance MACC_PA_BC_ROM_wrap_0 is undriven. If this is not the intended behavior, drive the inputs with valid values, or inputs from the top level.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 0 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 1 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 2 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 3 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 4 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 5 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 6 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 7 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 8 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 9 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 10 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 11 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 12 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 13 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 14 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 15 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 16 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 17 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 14 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 15 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Signal data_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Signal coef_w_8 is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":127:9:127:14|Signal mcanda is undriven. Either assign the signal a value or remove the signal declaration.
@W: CD638 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_tap_g5.vhd":132:9:132:26|Signal dbg_top_init_array is undriven. Either assign the signal a value or remove the signal declaration.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 0 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 1 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 2 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 3 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 4 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 5 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 6 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 7 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 8 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 9 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 10 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 11 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 12 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 13 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 14 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 15 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 16 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":481:9:481:14|Bit 17 of signal data_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 0 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 1 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 2 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 3 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 4 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 5 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 6 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 7 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 8 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 9 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 10 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 11 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 12 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CL252 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_PF\enum_undernibble_g5.vhd":482:9:482:14|Bit 13 of signal coef_w_8 is floating -- simulation mismatch possible.
@W: CD286 :"C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\component\Actel\DirectCore\COREFIR_PF\2.3.100\rtl\vhdl\core\enum_kit.vhd":434:7:434:16|Creating black box for empty architecture debug_INIT 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\work\pf_corefir\pf_corefir_0\rtl\vhdl\core\enum_pf\enum_fir_g5.vhd":171:2:171:13|Unbound component debug_INIT_1024 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_fir_adv_g5.vhd":255:2:255:13|Unbound component debug_INIT_1024 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_row_g5.vhd":185:2:185:13|Unbound component debug_INIT_1024 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Unbound component debug_INIT_128 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Unbound component debug_INIT_128 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Unbound component debug_INIT_16 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_macc_lib_g5.vhd":239:2:239:17|Unbound component MACC_PA_BC_ROM of instance MACC_PA_BC_ROM_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Unbound component debug_INIT_16 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Unbound component debug_INIT_128 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Unbound component debug_INIT_128 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_tap_g5.vhd":151:2:151:13|Unbound component debug_INIT_16 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_nibble_g5.vhd":260:2:260:13|Unbound component debug_INIT_128 of instance debug_init_0 
@W: Z198 :"c:\pf_task_jan_2021\test\dg0762\dg0762_corefir\libero_project\component\actel\directcore\corefir_pf\2.3.100\rtl\vhdl\core\enum_pf\enum_undernibble_g5.vhd":493:2:493:13|Unbound component debug_INIT_128 of instance debug_init_0 

