#--  Synopsys, Inc.
#--  Version Q-2020.03M-SP1
#--  Project file C:\PF_task_jan_2021\test\DG0762\DG0762_CoreFIR\Libero_Project\synthesis\run_options.txt
#--  Written on Wed Jan 13 10:53:51 2021


#project files
add_file -verilog "../component/polarfire_syn_comps.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0_0/rtl/vlog/core/Rx_async.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0_0/rtl/vlog/core/Tx_async.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0_0/rtl/vlog/core/fifo_256x8_g5.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0_0/rtl/vlog/core/Clock_gen.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0_0/rtl/vlog/core/CoreUART.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREUART_0/PF_COREUART_0.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/hdl/FILTER_CONTROL_FSM.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT_0/rtl/in_place/vlog/core/PF_COREFFT_PF_COREFFT_0_uram_g5.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/kit.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT_0/rtl/in_place/vlog/core/fftDp.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT_0/twiddle32.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/mac_lib.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/cmplx.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFFT/7.1.100/rtl/in_place/vlog/core/fftSm.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT_0/rtl/in_place/vlog/core/COREFFT.v"
add_file -verilog -lib COREFFT_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT_0/rtl/in_place/vlog/core/COREFFT_TOP.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFFT/PF_COREFFT.v"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/corefir_rtl_pack.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/corefir_top_kit.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_rtl_pack.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_kit.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/adv_dly_line.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_fir_adv_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_pad_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_macc_lib_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_tap_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_undernibble_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_nibble_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_row_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/Actel/DirectCore/COREFIR_PF/2.3.100/rtl/vhdl/core/enum_PF/enum_fir_basic_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFIR/PF_COREFIR_0/rtl/vhdl/core/enum_PF/PF_COREFIR_PF_COREFIR_0_enum_params.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFIR/PF_COREFIR_0/rtl/vhdl/core/enum_PF/PF_COREFIR_PF_COREFIR_0_enumFIR_coefs.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFIR/PF_COREFIR_0/rtl/vhdl/core/enum_PF/enum_fir_g5.vhd"
add_file -vhdl -lib COREFIR_PF_LIB "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFIR/PF_COREFIR_0/rtl/vhdl/core/enum_PF/COREFIR.vhd"
add_file -vhdl -lib work "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_COREFIR/PF_COREFIR.vhd"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_0/PF_TPSRAM_0_0/PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_0/PF_TPSRAM_0.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_1/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_1/PF_TPSRAM_1.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_2/PF_TPSRAM_2_0/PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_2/PF_TPSRAM_2.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_3/PF_TPSRAM_3_0/PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_3/PF_TPSRAM_3.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_4/PF_TPSRAM_4_0/PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_TPSRAM_4/PF_TPSRAM_4.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/hdl/UART_IF.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_DSP_FLOW_DEMO_TOP/PF_DSP_FLOW_DEMO_TOP.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_ccc_0/PF_ccc_0_0/PF_ccc_0_PF_ccc_0_0_PF_CCC.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_ccc_0/PF_ccc_0.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_init_monitor_0/PF_init_monitor_0_0/PF_init_monitor_0_PF_init_monitor_0_0_PF_INIT_MONITOR.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/PF_init_monitor_0/PF_init_monitor_0.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/reset_sync/reset_sync_0/core/corereset_pf.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/reset_sync/reset_sync.v"
add_file -verilog "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/component/work/top/top.v"
add_file -fpga_constraint "C:/PF_task_jan_2021/test/DG0762/DG0762_CoreFIR/Libero_Project/designer/top/synthesis.fdc"


#implementation: "synthesis"
impl -add synthesis -type fpga

#
#implementation attributes

set_option -vlog_std sysv

#device options
set_option -technology PolarFire
set_option -part MPF300T
set_option -package FCG1152
set_option -speed_grade -1
set_option -part_companion ""

#compilation/mapping options
set_option -use_fsm_explorer 0
set_option -top_module "top"

# hdl_compiler_options
set_option -distributed_compile 0
set_option -hdl_strict_syntax 0

# mapper_without_write_options
set_option -frequency 100.000
set_option -srs_instrumentation 1

# mapper_options
set_option -write_verilog 0
set_option -write_vhdl 0

# actel_options
set_option -rw_check_on_ram 0

# Microchip G4
set_option -run_prop_extract 1
set_option -maxfan 10000
set_option -clock_globalthreshold 2
set_option -async_globalthreshold 800
set_option -globalthreshold 5000
set_option -low_power_ram_decomp 0
set_option -seqshift_to_uram 1
set_option -disable_io_insertion 0
set_option -opcond COMTC
set_option -retiming 0
set_option -report_path 4000
set_option -update_models_cp 0
set_option -preserve_registers 0
set_option -disable_ramindex 0
set_option -rep_clkint_driver 1
set_option -microsemi_enhanced_flow 1
set_option -ternary_adder_decomp 66
set_option -pack_uram_addr_reg 1

# Microchip PolarFire
set_option -automatic_compile_point 0
set_option -rom_map_logic 1
set_option -polarfire_ram_init 1
set_option -gclkint_threshold 1000
set_option -rgclkint_threshold 100
set_option -clkint_rgclkint_limit 1
set_option -low_power_gated_clock 0
set_option -gclk_resource_count 24
set_option -min_cdc_sync_flops 2
set_option -unsafe_cdc_netlist_property 0

# NFilter
set_option -no_sequential_opt 0

# sequential_optimization_options
set_option -symbolic_fsm_compiler 1

# Compiler Options
set_option -compiler_compatible 0
set_option -resource_sharing 1

# Compiler Options
set_option -auto_infer_blackbox 0

# Compiler Options
set_option -vhdl2008 1

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "./top.vm"
impl -active "synthesis"
