Timing Multi Corner Report Max Delay Analysis

SmartTime Version 12.900.20.24

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Wed Jan 13 11:00:54 2021

Design top
Family PolarFire
Die MPF300TS
Package FCG1152
Temperature Range -40 - 100 C
Voltage Range 1.0185 - 1.0815 V
Speed Grade -1
Design State Post-Layout
Data source Production
Multi Corner Report Operating Conditions slow_lv_ht, slow_lv_lt, fast_hv_lt
Scenario for Timing Analysis timing_analysis

*** IMPORTANT RECOMMENDATION *** If you haven't done so, it is highly recommended to add clock jitter information for each clock domain into Libero SoC through clock uncertainty SDC timing constraints. Please refer to the Libero SoC v12.5 release notes for more details.

Summary

Clock Domain Required Period (ns) Required Frequency (MHz) Worst Slack (ns) Operating Conditions
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/A N/A
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 5.000 200.000 1.466 slow_lv_ht
REF_CLK_0 20.000 50.000

Worst Slack (ns) Operating Conditions
Input to Output

Clock Domain PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] 3.766 6.483 0.068 3.716 slow_lv_ht
Path 2 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] 3.763 6.480 0.068 3.715 slow_lv_ht
Path 3 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] 3.717 6.434 0.068 3.667 slow_lv_ht
Path 4 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] 3.714 6.431 0.068 3.666 slow_lv_ht
Path 5 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[8] 3.651 6.368 0.061 3.616 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK
To: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5]
data required time N/C
data arrival time - 6.483
slack N/C
Data arrival time calculation
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q 0.000 0.000
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 0.000 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_Z[2] + 0.160 0.160 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y cell ADLIB:CFG1 + 0.045 0.205 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2] + 1.448 1.653 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:Y cell ADLIB:GB + 0.113 1.766 2 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y + 0.361 2.127 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.052 2.179 16 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:CLK net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0_rgb_net_1 + 0.538 2.717 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2]:Q cell ADLIB:SLE + 0.175 2.892 88 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m12:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twid_wA_w[2] + 0.809 3.701 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m12:Y cell ADLIB:CFG2 + 0.129 3.830 22 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m168_i:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m12 + 0.493 4.323 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m168_i:Y cell ADLIB:CFG3 + 0.061 4.384 1 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m17_1_0_wmux:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/N_169_i_0 + 0.151 4.535 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m17_1_0_wmux:Y cell ADLIB:CFG4A + 0.155 4.690 1 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m17_1_0_wmux_0:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m17_1_0_y0 + 0.073 4.763 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m17_1_0_wmux_0:Y cell ADLIB:CFG4A + 0.061 4.824 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m172:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m17_1_0_wmux_0_Y + 0.476 5.300 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m172:Y cell ADLIB:CFG3 + 0.081 5.381 2 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_16:C net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/m172 + 0.247 5.628 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_16:Y cell ADLIB:CFG3 + 0.129 5.757 2 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/CFG_11:B net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidData_w[16] + 0.598 6.355 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/CFG_11:IPB cell ADLIB:CFG4_IP_ABCD + 0.024 6.379 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/W_DATA_net[5] + 0.104 6.483 f
data arrival time 6.483
Data required time calculation
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q N/C N/C
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q Clock source + 0.000 N/C f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_Z[2] + 0.130 N/C f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y cell ADLIB:CFG1 + 0.037 N/C 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2] + 1.171 N/C r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]:Y cell ADLIB:GB + 0.103 N/C 2 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0:A net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y + 0.326 N/C r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.047 N/C 16 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_CLK net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0_rgb_net_1 + 0.633 N/C r
clock reconvergence pessimism + 0.388 N/C
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[5] Library setup time ADLIB:RAM64x12_IP - 0.068 N/C
Operating Conditions slow_lv_ht

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

SET PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 to PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q

No Path

Clock Domain PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0

SET Register to Register

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) Minimum Period (ns) Operating Conditions
Path 1 PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[0] 3.304 1.575 6.614 8.189 0.062 3.425 slow_lv_ht
Path 2 PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[3] 3.279 1.602 6.589 8.191 0.060 3.398 slow_lv_ht
Path 3 PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[2] 3.258 1.622 6.568 8.190 0.061 3.378 slow_lv_ht
Path 4 PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[4] 3.246 1.631 6.556 8.187 0.064 3.369 slow_lv_ht
Path 5 PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[1] 3.251 1.631 6.561 8.192 0.059 3.369 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK
To: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[0]
data required time 8.189
data arrival time - 6.614
slack 1.575
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:Y cell ADLIB:GB + 0.145 2.217 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y + 0.361 2.578 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4:Y cell ADLIB:RGB + 0.052 2.630 515 f
PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4_rgb_net_1 + 0.680 3.310 r
PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0/INST_RAM1K20_IP:A_DOUT[0] cell ADLIB:RAM1K20_IP + 1.992 5.302 1 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/CFG_1:B net PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF_R_DATA[0] + 1.172 6.474 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/CFG_1:IPB cell ADLIB:CFG4_IP_ABCD + 0.024 6.498 1 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[0] net PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/W_DATA_net[0] + 0.116 6.614 f
data arrival time 6.614
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 Clock Constraint 5.000 5.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 5.000 r
Clock generation + 1.254 6.254
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 6.398 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 6.529 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 6.874 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:Y cell ADLIB:GB + 0.132 7.006 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y + 0.325 7.331 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB0:Y cell ADLIB:RGB + 0.047 7.378 29 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB0_rgb_net_1 + 0.657 8.035 r
clock reconvergence pessimism + 0.216 8.251
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0/INST_RAM64x12_IP:W_DATA[0] Library setup time ADLIB:RAM64x12_IP - 0.062 8.189
data required time 8.189
Operating Conditions slow_lv_ht

SET External Setup

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Setup (ns) External Setup (ns) Operating Conditions
Path 1 RX PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D 1.839 1.839 0.000 0.085 fast_hv_lt

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RX
To: PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D
data required time N/C
data arrival time - 1.839
slack N/C
Data arrival time calculation
RX 0.000 0.000 f
RX_ibuf/U_IOPAD:PAD net RX + 0.000 0.000 f
RX_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.619 0.619 1 f
RX_ibuf/U_IOIN:YIN net RX_ibuf/YIN + 0.000 0.619 f
RX_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.131 0.750 1 f
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D net RX_c + 1.089 1.839 f
data arrival time 1.839
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 0.699 N/C
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.093 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.089 N/C 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.225 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.100 N/C 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.227 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6:Y cell ADLIB:RGB + 0.034 N/C 1704 f
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6_rgb_net_1 + 0.287 N/C r
PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2]:D Library setup time ADLIB:SLE - 0.000 N/C
Operating Conditions fast_hv_lt

SET Clock to Output

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Clock to Out (ns) Operating Conditions
Path 1 PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK TX 4.196 7.353 7.353 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK
To: TX
data required time N/C
data arrival time - 7.353
slack N/C
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.151 2.223 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.371 2.594 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6:Y cell ADLIB:RGB + 0.052 2.646 1704 f
PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6_rgb_net_1 + 0.511 3.157 r
PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx:Q cell ADLIB:SLE + 0.166 3.323 1 f
TX_obuf/U_IOTRI:D net TX_c + 1.079 4.402 f
TX_obuf/U_IOTRI:DOUT cell ADLIB:IOTRI_OB_EB + 0.918 5.320 1 f
TX_obuf/U_IOPAD:D net TX_obuf/DOUT + 0.000 5.320 f
TX_obuf/U_IOPAD:PAD cell ADLIB:IOPAD_TRI + 2.033 7.353 0 f
TX net TX + 0.000 7.353 f
data arrival time 7.353
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
TX N/C f
Operating Conditions slow_lv_ht

SET Register to Asynchronous

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) Minimum Period (ns) Skew (ns) Operating Conditions
Path 1 reset_sync_0/reset_sync_0/dff_15_rep:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N 3.337 1.466 6.533 7.999 0.207 3.534 -0.010 slow_lv_ht
Path 2 reset_sync_0/reset_sync_0/dff_15_rep:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N 3.301 1.505 6.497 8.002 0.207 3.495 -0.013 slow_lv_ht
Path 3 reset_sync_0/reset_sync_0/dff_15_rep:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:D_ARST_N 3.288 1.516 6.484 8.000 0.209 3.484 -0.013 slow_lv_ht
Path 4 reset_sync_0/reset_sync_0/dff_15_rep:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N 3.176 1.625 6.372 7.997 0.207 3.375 -0.008 slow_lv_ht
Path 5 reset_sync_0/reset_sync_0/dff_15_rep:CLK PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:D_ARST_N 3.162 1.637 6.358 7.995 0.209 3.363 -0.008 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: reset_sync_0/reset_sync_0/dff_15_rep:CLK
To: PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N
data required time 7.999
data arrival time - 6.533
slack 1.466
Data arrival time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 0.000 0.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 0.000 r
Clock generation + 1.384 1.384
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.158 1.542 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.151 1.693 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.379 2.072 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:Y cell ADLIB:GB + 0.145 2.217 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y + 0.371 2.588 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5:Y cell ADLIB:RGB + 0.052 2.640 697 f
reset_sync_0/reset_sync_0/dff_15_rep:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5_rgb_net_1 + 0.556 3.196 r
reset_sync_0/reset_sync_0/dff_15_rep:Q cell ADLIB:SLE + 0.175 3.371 127 r
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N net reset_sync_0/reset_sync_0/dff_15_rep_Z + 3.162 6.533 r
data arrival time 6.533
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 Clock Constraint 5.000 5.000
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 5.000 r
Clock generation + 1.254 6.254
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 6.398 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 6.529 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 6.874 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0:Y cell ADLIB:GB + 0.137 7.011 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB7:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 + 0.332 7.343 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB7:Y cell ADLIB:RGB + 0.047 7.390 1196 f
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB7_rgb_net_1 + 0.618 8.008 r
clock reconvergence pessimism + 0.198 8.206
PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0/INST_MACC_IP:AL_N Library recovery time ADLIB:MACC_IP - 0.207 7.999
data required time 7.999
Operating Conditions slow_lv_ht

SET External Recovery

From To Delay (ns) Slack (ns) Arrival (ns) Required (ns) Recovery (ns) External Recovery (ns) Operating Conditions
Path 1 RESET_N reset_sync_0/reset_sync_0/dff_13:ALn 5.479 5.479 0.170 2.789 slow_lv_ht
Path 2 RESET_N reset_sync_0/reset_sync_0/dff_12:ALn 5.479 5.479 0.170 2.789 slow_lv_ht
Path 3 RESET_N reset_sync_0/reset_sync_0/dff_11:ALn 5.479 5.479 0.170 2.788 slow_lv_ht
Path 4 RESET_N reset_sync_0/reset_sync_0/dff_14:ALn 5.209 5.209 0.170 2.508 slow_lv_ht
Path 5 RESET_N reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE:ALn 5.179 5.179 0.170 2.467 slow_lv_ht

Expanded Path 1

Pin Name Type Net Name Cell Name Op Delay (ns) Total (ns) Fanout Edge
From: RESET_N
To: reset_sync_0/reset_sync_0/dff_13:ALn
data required time N/C
data arrival time - 5.479
slack N/C
Data arrival time calculation
RESET_N 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:PAD net RESET_N + 0.000 0.000 r
RESET_N_ibuf/U_IOPAD:Y cell ADLIB:IOPAD_IN + 0.599 0.599 1 r
RESET_N_ibuf/U_IOIN:YIN net RESET_N_ibuf/YIN + 0.000 0.599 r
RESET_N_ibuf/U_IOIN:Y cell ADLIB:IOIN_IB_E + 0.336 0.935 1 r
reset_sync_0/reset_sync_0/un1_D:A net RESET_N_c + 2.467 3.402 r
reset_sync_0/reset_sync_0/un1_D:Y cell ADLIB:CFG4 + 0.204 3.606 18 r
reset_sync_0/reset_sync_0/dff_13:ALn net reset_sync_0/reset_sync_0/un1_INTERNAL_RST_i + 1.873 5.479 r
data arrival time 5.479
Data required time calculation
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0 N/C N/C
PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 Clock source + 0.000 N/C r
Clock generation + 1.254 N/C
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:A net PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 + 0.144 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0_1:Y cell ADLIB:ICB_CLKINT + 0.131 N/C 2 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0_NET + 0.345 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0:Y cell ADLIB:GB + 0.132 N/C 6 r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5:A net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y + 0.334 N/C r
PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5:Y cell ADLIB:RGB + 0.047 N/C 697 f
reset_sync_0/reset_sync_0/dff_13:CLK net PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5_rgb_net_1 + 0.473 N/C r
reset_sync_0/reset_sync_0/dff_13:ALn Library recovery time ADLIB:SLE - 0.170 N/C
Operating Conditions slow_lv_ht

SET Asynchronous to Register

No Path

SET PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q to PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0

No Path

Clock Domain REF_CLK_0

Info: The maximum frequency of this clock domain is limited by the minimum pulse widths of pin REF_CLK_0_ibuf/U_IOPAD:PAD

SET Register to Register

No Path

SET External Setup

No Path

SET Clock to Output

No Path

SET Register to Asynchronous

No Path

SET External Recovery

No Path

SET Asynchronous to Register

No Path

Path Set Pin to Pin

SET Input to Output

No Path

Path Set User Sets