Global Net Report

Microsemi Corporation - Microsemi Libero Software Release v12.6 (Version 12.900.20.24)

Date: Wed Jan 13 10:57:35 2021

Global Nets Information

From GB Location Net Name Fanout
1 PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0 (1164, 163) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 3260
2 reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_GB0 (1175, 162) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_gbs_1 1507
3 PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0 (1152, 162) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y 1365
4 reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0 (1163, 162) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_Y 1280
5 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0 (1164, 162) PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y 22

I/O to GB Connections

(none)

Fabric to GB Connections

From From Location To Net Name Net Type Fanout
1 reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE:Q (1152, 82) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_GB0 reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE_net ROUTED 2
2 reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE:Q (1152, 82) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0 reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE_net ROUTED 2
3 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2]:Y (1201, 78) PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_Z[2] ROUTED 1

CCC to GB Connections

From From Location To Net Name Net Type Fanout
1 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 (2460, 5) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 HARDWIRED 1
2 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0 (2460, 5) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0 PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_clkint_0 HARDWIRED 1

CCC Input Connections

Port Name Pin Number I/O Function From From Location To CCC Location Net Name Net Type Fanout
1 REF_CLK_0 E25 HSIO63PB6/CLKIN_S_12/CCC_SE_CLKIN_S_12/CCC_SE_PLL0_OUT0 REF_CLK_0_ibuf/U_IOPAD:Y (2256, 1) PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:REF_CLK_0 (2460, 5) REF_CLK_0_c HARDWIRED 2

Local Nets to RGB Connections

(none)

Global Nets to RGB Connections

From From Location Net Name Fanout RGB Location Local Fanout
1 PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0 (1164, 163) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_gbs_1 3260 1 (1741, 12) 102
2 (1741, 39) 1704
3 (1741, 66) 64
4 (1747, 12) 74
5 (1747, 39) 1196
6 (1747, 66) 120
2 reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_GB0 (1175, 162) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_gbs_1 1507 1 (1745, 40) 833
2 (1745, 67) 15
3 (1751, 40) 659
3 PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0 (1152, 162) PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_Y 1365 1 (576, 39) 515
2 (576, 66) 29
3 (582, 12) 11
4 (582, 39) 697
5 (582, 66) 112
6 (582, 93) 1
4 reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0 (1163, 162) reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_Y 1280 1 (581, 40) 499
2 (581, 67) 24
3 (587, 40) 653
4 (587, 67) 104
5 PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0 (1164, 162) PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_Y 22 1 (1740, 39) 16
2 (1740, 66) 6

Clock Signals Summary

The number of clock signals through H-Chip Global resources 3
The number of clock signals through Row Global resources 14
The number of clock signals through Sector Global resources 58
The number of clock signals through Cluster Global resources 676