# Microsemi NMAT TXT File

# Version: v12.6 12.900.20.24

# Design Name: top 

# Input Netlist Format: EDIF 

# Family: PolarFire , Die: MPF300TS , Package: FCG1152 , Speed grade: -1 

# Date generated: Wed Jan 13 10:59:39 2021 


#
# I/O constraints
#

set_io REF_CLK_0 E25
set_io RESET_N K22
set_io RX H18
set_io TX G17

#
# Core cell constraints
#

set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[10] 1563 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1797 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[23] 1696 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[21] 1556 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][14] 1800 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[5] 1694 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[27] 1783 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][12] 1700 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[9] 1605 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 293 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[8]\\ 798 54
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[0] 1551 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 629 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1674 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_valid_r 1780 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[24] 1718 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_8_RNO 1538 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2302 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[1] 1576 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2031 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[31] 1719 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[6] 793 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[10] 1563 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1662 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[14] 1788 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m80_i 1511 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[20] 1820 39
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_o4[0] 1451 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 959 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 548 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_4_inst 793 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine[1] 1626 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[9] 1605 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[10] 1738 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[21] 1769 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[10] 1622 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1853 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2007 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1781 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1578 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[13] 1699 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[0] 1629 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 296 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[9] 1596 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[18] 1557 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 245 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[3] 1645 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][1] 1634 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m103 1562 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1794 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][9] 1760 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[4] 1606 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][0] 1573 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[22] 1779 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][9] 1759 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/dvalid_pipe_0/delayLine[1] 1825 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 485 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m73 1511 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[10] 1732 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][4] 1594 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[11] 1813 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_4 1551 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1718 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/CFG2_BLKX0[0] 1719 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/tc_7_2_0 1652 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m166_i 1547 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 550 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[2] 1633 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 979 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[2] 1637 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[13] 1790 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[0] 829 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 269 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[31] 1699 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1433 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[17] 1647 24
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[1] 1154 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 636 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[8] 1707 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1648 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[1] 1671 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 455 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[7] 1700 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1702 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[2] 1580 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[17] 1810 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 545 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[23] 1771 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[28] 1727 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[2] 1723 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[5] 1643 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[13] 1769 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1097 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[5] 1550 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 831 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[6] 1615 37
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[6] 1370 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[2]\\ 792 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1277 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1445 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WEN_RNO 1601 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[9] 1681 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[1] 1200 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m283 1575 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[31] 1694 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[11] 1645 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][1] 1808 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][13] 1725 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1032 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1843 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[12] 1327 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[23] 1820 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[11] 1763 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[4] 1706 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[21] 1819 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[18] 1833 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[8] 1682 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[28] 1585 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_1_inst 833 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[6]_3 1618 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 349 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][14] 1796 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m117 1535 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit 1536 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[30] 1692 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1227 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[3] 1561 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1371 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 1155 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/valid_pipe_0/delayLine[2] 735 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[10] 1621 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 197 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1769 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/trueRst 1642 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[14] 1791 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1313 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][1] 1555 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1883 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[12] 1803 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][6] 1706 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[0] 788 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[8] 1712 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1362 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2133 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 1835 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][9] 1752 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[22] 1722 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1096 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[3] 799 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2225 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 645 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/edge_detect_0/inp_tick 1694 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[21] 1759 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 1154 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0_RNO 1139 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[28] 1843 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[26] 1734 27
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNI8CKB1[4] 1339 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 1250 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_8 1593 36
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0_1 2448 164
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2062 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[4] 1651 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1539 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1559 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[21] 1843 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1646 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[0] 1711 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1527 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1226 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1169 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][9] 1592 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[2] 1703 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1061 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][13] 1588 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1902 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 917 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_6 1556 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1708 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[1] 1603 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 713 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[7] 1719 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1709 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[23] 1837 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 280 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[9] 1632 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[16] 1820 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 2051 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[4] 1686 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[24] 1774 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m46_1_2 1511 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_202_i 1501 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[20] 1807 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[5] 1709 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][1] 1613 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[2] 1636 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/swCross 1582 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/un1_bflyOutValid 1694 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[2] 1691 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][6] 1705 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1276 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_8 1597 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[18] 1810 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2201 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1001 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[14] 1696 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1444 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.N_183_i 1580 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[0] 1705 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[26] 1805 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m82 1508 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m248_2_1 1503 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2165 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1626 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 196 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1513 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 2023 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2094 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smPong_2_sqmuxa_i 1623 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 220 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_9_i 1583 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][9] 1758 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 701 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 351 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm[1] 1163 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[8] 1687 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[4] 1576 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_0_inst 829 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/twid_wEn_1_sqmuxa_i 1538 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][8] 1675 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[5] 1643 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[3] 1726 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[6] 1668 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[8] 1662 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[7] 1554 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc_3_0_a2_1 1594 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[29] 1716 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1731 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1919 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1779 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 277 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m172 1546 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2297 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[5] 1128 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1673 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[18] 1805 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[5] 1573 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/dvalid_pipe_0/delayLine[0] 721 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[10] 1187 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m125 1530 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2270 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 393 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 209 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[12] 1809 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[23] 1703 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[1] 1694 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 1156 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[11] 1687 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r_RNO[2] 1592 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[6] 1698 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_4_RNO 239 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 198 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[28] 1778 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 843 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[0] 1670 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[0][0] 1663 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[26] 1739 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 1801 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 348 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1801 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[27] 1783 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1779 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[9] 1690 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[13] 1699 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2118 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[26] 1842 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[6] 1558 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[0] 1554 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[19] 1788 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1708 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[9] 1641 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1581 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1419 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1554 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][8] 1673 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[6] 1340 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rx_en_RNO 1470 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state[3] 1648 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_9 1586 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dvalid_pipe_3/delayLine[4] 797 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[22] 1720 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[3] 1609 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[29] 1725 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[25] 1731 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[10] 1556 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1349 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 1546 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 830 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[16] 1811 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2097 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[0] 1205 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ifoLoad 1641 40
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m38_i_i_o2_5 1379 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1693 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[25] 1737 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1534 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m12 1528 24
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[1] 1461 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[3] 1644 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1802 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[1] 1716 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 989 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[5] 1640 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[14] 1688 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[5] 1554 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[7] 1636 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 1258 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_3/genblk1.delayLine[0] 1608 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.N_60_i 1163 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[9] 1707 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[28] 1777 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 700 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 703 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[12] 1795 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m265 1511 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 640 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 670 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_shift.rx_bit_cnt_4[2] 1452 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r_RNO[1] 1591 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_RNIQSFH1[4] 1669 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[10] 1758 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/dvalid_pipe_0/delayLine[1] 949 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[0] 1612 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][3] 1799 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 1154 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1806 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[1] 1604 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1626 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 958 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1335 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 216 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[4] 1691 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1792 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 382 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/dvalid_pipe_0/delayLine[1] 1565 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[11] 1763 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m274_1_0 1571 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1913 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[29] 1721 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_2_6[0] 1583 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1348 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[26] 1842 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 1555 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[5] 1755 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1949 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1754 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][5] 1757 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][5] 1756 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_3 1555 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/N_87_i 1578 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1712 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[11] 1815 39
set_location reset_sync_0/reset_sync_0/dff_1 1160 4
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[3] 1562 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[3] 1544 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[5] 1644 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 439 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2314 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m256 1510 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[22] 1797 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][5] 1569 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[10] 1686 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1778 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1479 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/cvalid_pipe_0/delayLine[1] 1271 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1553 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[26] 1901 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/un1_rx_bit_cnt_1.CO1 1460 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WEN_RNO_0 1351 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1821 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[21] 1799 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1361 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1133 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[7] 1710 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1877 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[1] 1646 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1613 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][2] 1806 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2333 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA_0 1187 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1592 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[20] 1796 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[8] 1596 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBufValid_r 1631 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 260 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m8 1545 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[2] 1612 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 339 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1672 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[29] 1721 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[5] 1641 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_9 1568 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[2] 1721 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1923 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1768 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_5 1596 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1289 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[7] 1494 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 905 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m30 1499 27
set_location PF_init_monitor_0_0/PF_init_monitor_0_0/I_INIT 508 2
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[3] 1595 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1011 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m71 1523 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/tc_RNO 1675 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[4] 1655 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_DATA_OUT_0_sqmuxa_i_a3_RNIEVLL 1596 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1181 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/valid_pipe_0/delayLine[0] 684 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m284 1579 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[4] 1587 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 704 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2045 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 1157 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[25] 1836 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_7_RNO_0 1557 39
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[6] 1663 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[2] 792 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[2] 1590 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[17] 1765 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[17] 1795 36
set_location reset_sync_0/reset_sync_0/dff_3 1159 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2189 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m261 1510 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1409 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_7_RNO 219 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[24] 1875 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[24] 1903 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/dvalid_pipe_0/delayLine[1] 1905 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2153 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[3] 1717 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[19] 1789 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[17] 1767 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m125 1534 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m35 1499 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1817 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[20] 1801 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 1147 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1686 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid 1612 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1793 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/end_of_ngrst_0/d_flop2 1267 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[1] 1632 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m8_i 1535 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[1] 1632 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[6] 1597 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[18] 1755 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][5] 1704 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2214 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 459 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 264 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[4] 1699 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[29] 1814 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_3_RNI887V 217 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 574 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 401 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r[0] 1577 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[12] 1686 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1200 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 1843 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 797 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 385 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[15] 1753 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[6] 1691 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[5] 1610 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1637 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[31] 1777 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 721 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_5_RNO 1137 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_16 1536 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1132 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][14] 1701 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1360 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[6]\\ 793 51
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel_RNO[2] 1644 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[14] 1824 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[14] 1829 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[0] 1761 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/rAmsb_r2 1715 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2261 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2123 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 425 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_7 1582 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[15] 1786 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1901 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[6] 1580 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[4] 1791 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/dvalid_pipe_0/delayLine[2] 731 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1861 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[24] 1903 27
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count_RNO[0] 1449 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2128 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1551 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[4] 1663 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[27] 1860 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1734 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2321 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[31] 1695 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[6] 1727 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[29] 1867 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m167_1_1 1544 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 321 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1180 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1217 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 1247 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[11] 1762 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[15] 1805 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[7] 1636 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m277_1_0 1569 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][6] 1704 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1529 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[2] 1700 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1541 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[1] 1639 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][5] 1755 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m264_2_0 1523 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/valid_pipe_0/delayLine[1] 1268 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[11] 1827 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][0] 1691 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[22] 1772 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 1303 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][0] 1764 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/validOut 1792 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[7] 1584 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1896 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[8] 1689 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1842 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1757 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[0] 1655 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_0_inst 832 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m46 1510 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[16] 1792 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1000 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_valid_RNO 1623 42
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR_RNIJMT71[0] 1120 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[3] 1694 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[5] 1729 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1793 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1457 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 618 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1829 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 400 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][13] 1809 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[1] 1498 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r[1] 1591 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[4] 1654 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 1162 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[9] 1635 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[3] 1632 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[2] 1680 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1589 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[0]\\ 788 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m166 1534 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1528 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[17] 1809 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1205 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/tick1 1207 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2175 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[17] 1793 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[2] 1584 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[5] 1221 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[1] 1572 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[1] 1736 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[17] 1555 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[28] 1825 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1961 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[4] 1689 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 761 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1971 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 971 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1897 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[1] 1632 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1756 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[0] 1670 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[3] 1599 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m111 1547 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2260 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1469 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1830 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][8] 1671 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1535 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r_RNIMDE6[2] 1563 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1673 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 2021 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[24] 1831 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][5] 1660 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_25 1533 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_4_i 1580 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 1554 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[29] 1786 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_57_i 1547 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 2038 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 809 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 1534 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1588 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1685 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1889 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1275 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[10] 1715 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1637 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m242 1546 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m152 1568 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[27] 1821 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2127 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[29] 1724 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[7] 1681 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 438 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1780 55
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/FIR_OUT_REN_0_a2 1557 42
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm[3] 1243 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 439 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_1_RNO 1135 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[12] 1789 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/cvalid_pipe_0/delayLine[0] 1415 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[20] 1795 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2096 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1531 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 404 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[8] 1611 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][0] 1638 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[20] 1796 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[15] 1183 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[24] 1900 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m39 1510 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[19] 1710 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[21] 1792 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m168 1508 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m59_2_0_1 1546 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][6] 1572 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/SEL_RNO 1207 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rAwA_w_0_a2_0 1587 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 970 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 999 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[27] 1711 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][1] 1642 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[4] 1641 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m13_i 1522 21
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[3] 1661 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1815 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[7] 1332 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_4 1598 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/cvalid_pipe_0/delayLine[0] 1269 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1777 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[27] 1871 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1198 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_9 1532 36
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m35_i_0 1243 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[4] 1607 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2050 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m225 1499 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[4] 1634 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_1 1135 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 419 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/valid_pipe_0/delayLine[2] 983 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 808 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[12] 1700 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][7] 1625 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[2] 1728 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[27] 1593 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[4] 1691 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[14] 1794 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_0_sqmuxa_3_0_1 1642 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[0] 1458 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2] 1164 162
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[8] 1656 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m130_1_1 1498 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[13] 1767 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[4] 1696 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m242 1509 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1767 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick[1] 1586 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1960 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[11] 1718 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 494 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 417 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1850 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[2] 1553 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/startFFT_g4_dly_0/genblk1.delayLine[1] 1630 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[3][0] 1650 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[11] 1146 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 913 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/genblk1.RXRDY4 1466 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2237 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[2] 1125 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 256 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][12] 1651 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_4 1575 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1707 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_26 1510 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][1] 1641 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1865 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[3] 1570 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[5] 1580 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m167_1 1543 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[6] 1693 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_82_i 1507 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[20] 1831 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[19] 1807 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[6] 1625 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[18] 1795 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick2[0] 1536 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][0] 1655 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[0] 1755 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[7] 1554 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[19] 1558 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_17 1571 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[15] 1818 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[0] 1668 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[7] 1754 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[4] 1188 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_3_inst 810 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1636 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[3] 1655 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[1] 1606 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1073 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[3] 1677 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_ns_0_a2[5] 1655 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[5] 1759 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][5] 1644 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[3] 1649 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[3] 1738 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[23] 1695 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[9]\\ 826 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r_5[0] 1591 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 567 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m102_1_1 1545 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 1842 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[4] 1157 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[22] 1719 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine[3] 1208 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[5] 1577 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 775 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/cvalid_pipe_0/delayLine[0] 1268 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 699 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[11] 1812 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1625 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 904 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m2 1522 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[30] 1692 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][15] 1591 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[4] 1730 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[6] 1691 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m219 1509 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/valid_pipe_0/delayLine[1] 1237 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[31] 1695 24
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[1] 1337 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2283 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1770 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[15] 1795 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[4] 1617 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1845 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][9] 1691 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_7 218 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2046 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[4] 1594 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1710 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1701 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/rdCtl_reg_RNIFE5L 1625 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[3] 1199 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1616 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m89 1498 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1530 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 226 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[5] 1606 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1322 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 460 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[7] 1660 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2_RNIVPIT[0] 1116 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[10] 1685 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[3] 1799 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[22] 1778 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_cnt.xmit_bit_sel_3_i_0_o2[3] 1650 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[22] 1729 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[3] 1717 51
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[4] 1702 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2215 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2308 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/cvalid_pipe_0/delayLine[1] 1504 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[11] 1731 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m285 1577 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 772 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][0] 1611 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[7] 1736 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[7] 1624 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_5_RNO 224 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 195 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[29] 1588 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[11] 1822 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[3] 1648 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1780 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m157_1 1575 24
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNI5KDI[3] 1190 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][6] 1570 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_statece[1] 1439 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1005 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 915 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smPong_5 1627 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][9] 1757 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1908 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 342 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_4_RNO 1136 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[0] 1739 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m280 1558 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[6] 1738 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 591 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m45 1508 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 956 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][2] 1661 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_4_i 1602 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_4 239 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 668 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.bflyMode_r 1818 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1898 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[6] 1553 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_sel.tx_4_iv_i 1652 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[4] 830 55
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[6] 1721 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1312 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 230 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 698 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA_0_7 1176 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[3] 1567 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[7] 1673 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1767 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[5] 1565 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ENABLE_RNO 1210 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 262 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[15] 1698 34
set_location reset_sync_0/reset_sync_0/dff_15_rep 1160 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rx_en_RNO_1 1469 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WEN_0_sqmuxa_i_o3 1471 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[22] 1713 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1047 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1806 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m68 1523 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[1] 1677 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[13] 1816 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[8] 1682 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[1] 1573 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[2] 1581 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_bflyRiskOV_w_2 1722 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1288 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel[0] 1654 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/cvalid_pipe_0/delayLine[2] 675 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2[2] 1136 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1168 46
set_location reset_sync_0/reset_sync_0/dff_0 1158 4
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_i[0] 1499 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_9 1553 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][7] 1759 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1614 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[2][1] 1795 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_2/genblk1.delayLine[1] 1613 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[19] 1799 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[24] 1720 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][7] 1764 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][3] 1631 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m206_2_0 1545 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2063 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[0] 1597 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_0_sqmuxa_1_0_a2_0_a2_RNIHR0N 1251 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 708 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 850 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m34_2_1 1570 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 969 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_full_int_1_sqmuxa_i_1 1463 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[21] 1801 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[8] 1739 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1832 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 903 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 683 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[11] 1801 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[0] 1704 54
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte_1_sqmuxa 1454 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[15] 837 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_pad.dvalid_pipe_2/delayLine[0] 1265 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1095 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1816 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][15] 1689 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[14] 1828 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1131 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1640 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1215 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[1] 1552 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[3] 1184 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1620 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[28] 1782 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m194 1498 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[11] 1804 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[4] 1681 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[21] 1807 51
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_shift.rx_bit_cnt_4[0] 1458 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m200 1518 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/cvalid_pipe_0/delayLine[0] 1126 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 590 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m256_2_1_1_1 1509 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 374 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 257 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/dvalid_pipe_0/delayLine[1] 1236 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[7] 1681 25
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[2] 1366 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.bflyMode_r 1763 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1997 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[1] 1124 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1553 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1647 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/fftRd_done_r_3_0_a2 1613 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[3] 1638 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[0] 1605 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m188_i 1521 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 760 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2224 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/cvalid_pipe_0/delayLine[0] 1404 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_I_VALID 1293 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[11] 835 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_2_inst 792 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preOutBuf_wEn_2_sqmuxa_i_0 1620 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[4] 1577 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[5] 1645 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2044 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[7] 781 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1671 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1802 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_5_inst 807 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[4] 1689 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[2] 1708 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][11] 1628 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2332 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1922 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1714 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_27 1509 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[13] 1817 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1771 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1728 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[31] 1890 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 1834 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.N_200_i 1544 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_1_inst 782 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 298 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[11] 1813 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[5] 1535 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1996 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1733 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1913 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[6] 1564 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[0] 1529 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[0] 1725 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[1] 1581 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_7 1599 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1783 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 991 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1287 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[0] 1607 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m71 1517 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[18] 1821 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1635 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[27] 1705 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[7] 1706 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 666 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 628 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1854 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[0] 1674 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m206_1_0 1553 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[14] 1800 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m34_2 1569 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[30] 1892 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][7] 1705 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2336 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[8] 1534 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m41_1_0 1509 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 676 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2057 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2200 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_RNO[2] 1593 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m249 1508 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[2] 1708 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 399 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1694 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2164 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[4] 1725 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1443 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[6] 1548 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[23] 1693 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_RNO[4] 1586 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[19] 1835 27
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[8] 1736 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[1] 1736 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1959 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1094 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[6] 1585 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1664 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[9] 1642 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 988 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 244 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[18] 1808 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1191 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[1] 1365 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2135 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[6] 1553 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_ns_0[5] 1646 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][4] 1566 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[3] 1677 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[11] 1815 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/un1_rst_1 1624 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[24] 1721 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1071 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][2] 1648 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1024 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 454 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[24] 1718 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2021 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[0] 1670 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsmce[14] 1329 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 218 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[3] 1684 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][13] 1807 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2293 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m12_0_0_a2_0 1284 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 294 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[4] 1725 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m72 1509 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[27] 1865 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][8] 1647 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_0_RNI7VRM 1119 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 2047 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[6] 1352 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/N_82_i 1584 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][1] 1636 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 881 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[7] 1672 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m109 1508 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[31] 1813 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m160 1557 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[15] 1791 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_6_RNO 222 54
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[5] 1686 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA_0_7_RNIGF4F 1188 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[0] 1652 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[2] 1737 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[8] 1735 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_RNO[1] 1200 78
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m15 1521 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1948 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0_o2[14] 1328 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[6] 1530 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_11 1507 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1703 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1841 28
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m35_i_0_o2 1289 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][14] 1671 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[13]\\ 838 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preOutBuf_wEn 1623 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1259 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2043 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][7] 1755 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[1] 1729 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/un1_startLoad 1633 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1815 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2337 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[2] 1670 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2328 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[5] 1640 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_rdy_2_sqmuxa_i 1624 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 1256 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[2] 1724 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[10] 1630 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 304 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_r 1591 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_3_0_a2_1 1567 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[29] 1874 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_3_0_a2_2 1592 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wEn_r 1637 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][5] 1693 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 365 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/cvalid_pipe_0/delayLine[1] 1124 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2[1] 230 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][3] 1547 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[8] 1683 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1612 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[8] 1601 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[27] 1889 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[16] 1663 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[16] 1793 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 712 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[28] 1782 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_4_inst 824 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 683 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[6] 1735 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/cvalid_pipe_0/delayLine[1] 1501 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[14]\\ 825 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 283 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNI3LN51[3] 1146 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[8] 1667 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1649 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1613 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1347 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[3] 1716 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[13] 1788 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 457 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[27] 1782 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 484 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1759 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[10] 1684 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[12] 1835 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[10] 1684 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[11] 1814 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[6] 1637 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2199 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[30] 1713 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[3] 1589 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[13] 1819 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m23_i 1523 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2163 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m248_2_1_1 1502 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state[5] 1646 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[5] 1640 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[1] 831 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1762 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1769 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 413 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[19] 1818 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_shift.rx_bit_cnt_4[3] 1453 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][5] 1715 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1468 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[9] 1528 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_RNO[3] 1588 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2090 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m16_1_1 1446 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_3 1134 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2056 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[1] 1641 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick2[1] 1557 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[30] 1754 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][0] 1646 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[8] 1559 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][9] 1754 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[5] 1724 54
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[1] 1569 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/async2sync_0/delayLine[2] 1261 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 902 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/SEL 1208 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[15] 1802 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[3] 1593 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1648 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1145 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[2] 1574 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[25] 1773 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[4]_3 1617 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_4 1604 39
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[3] 1724 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[28] 1791 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wEn_Q_r 1650 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[2] 1639 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[27] 1891 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_8_i 1585 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2_RNO[0] 228 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1660 34
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[2] 1155 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[4] 1220 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[3] 1603 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[3] 1692 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1529 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 1115 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 1553 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_2_sqmuxa_1_i_a2_4 1585 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1493 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[5] 1680 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[1] 1675 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[24] 1738 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m147 1567 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 521 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_0[0] 1497 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.N_89_i 1497 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 716 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[21] 1816 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 437 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1618 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[5] 832 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2007 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m6_i 1520 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1719 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[31] 1781 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1766 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/cvalid_pipe_0/delayLine[2] 291 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1346 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/BLK_EN_inst 806 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1970 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][15] 1787 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1647 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[28] 1722 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 275 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[0] 1736 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_rdy_0_sqmuxa_1 1619 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][12] 1585 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[5] 1713 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[29] 1874 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[2] 1627 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[0] 795 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[29] 1814 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1769 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2139 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[5] 1658 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[0] 1542 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1612 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[0] 1672 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1921 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1552 28
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[6] 1129 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][13] 1767 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1620 34
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[3] 1156 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2259 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[16] 1766 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[13] 1793 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[18] 1766 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[1] 1580 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 418 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_6 1134 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1684 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[18] 1808 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[5] 832 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[7] 1625 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/dvalid_pipe_1/delayLine[2] 800 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1467 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[1] 1590 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wEn_P_r 1655 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/bflyMonitor 1699 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc_3_0_a2_1_RNIAGSQ 1592 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[24] 1726 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1144 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1894 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rx_en_RNO_0 1465 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_ns[0] 1649 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[8] 1224 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 968 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m137 1506 30
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[0] 1190 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[16] 1804 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 299 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][0] 1673 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_o2[0] 1326 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 967 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[5] 1679 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[1] 1705 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[15] 1720 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[13] 1722 37
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ENABLE 1210 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[28] 1824 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_5_inst 827 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 467 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1527 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 677 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[1] 1535 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[6] 1652 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[28] 1692 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[19] 1803 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[25] 1761 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/twid_wEn 1538 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1914 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[24] 1718 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[17] 1802 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_1 1534 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1672 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_21 1505 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_9 1599 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[7] 1731 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_13 1556 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 687 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[2] 1662 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[0] 1629 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0[6] 1489 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1911 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[7] 1700 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/rdCtl_reg 1621 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 1545 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 1841 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preInBuf_wEn_1_sqmuxa_0_a2 1628 39
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel_RNO[3] 1653 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[2] 1680 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1900 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wEn_r 1634 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[12] 1796 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[18] 1807 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1179 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 644 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2[0] 1132 55
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[5] 1182 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 268 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][0] 1643 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][3] 1775 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_rdy 1619 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][3] 1774 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[9] 1722 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_0_a2_0_1[2] 1347 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1274 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[31] 1776 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.CO0 1658 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1492 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[3] 1728 55
set_location reset_sync_0/reset_sync_0/dff_8 1157 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m146_2_0 1507 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1888 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m60 1522 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_4 1581 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1527 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 406 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[9] 1730 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1601 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[15] 1790 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1667 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[23] 1697 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_3/genblk1.delayLine[1]_3 1611 45
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_one 1723 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m59_2_0_1 1519 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[25] 1752 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[12] 1768 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 589 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_RNIK0141[10] 1729 60
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_RNI54T51[12] 1738 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2061 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[0] 1638 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1755 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[12] 1327 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1731 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 324 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[27] 1785 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[0] 1657 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1732 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2276 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1635 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[13] 1775 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[5] 1324 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[28] 1857 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[27] 1836 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_shift.rx_bit_cnt_4[1] 1461 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1716 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2059 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_233_i 1533 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[4] 1562 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][2] 1804 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1851 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[13] 1790 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[16] 1550 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1717 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][2] 1802 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1844 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 747 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[28] 1826 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[16] 1811 39
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[4] 1699 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[4] 1554 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[5] 1688 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1800 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2055 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_0_inst 816 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1814 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_7_RNO 1537 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 571 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[1] 1669 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[1] 1668 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[14] 1832 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[24] 1721 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[31] 1847 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1611 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WEN_RNO_1 1603 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[4] 1641 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 880 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[30] 1702 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[17] 1806 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[12] 1169 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 896 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1904 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[5] 1578 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 966 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m250 1530 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1706 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[7] 1668 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[21] 1771 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m173 1568 27
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_o2[2] 1448 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1958 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[21] 1789 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[16] 1790 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][13] 1699 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[15] 1788 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[27] 1895 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[7] 1223 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[1] 1675 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[1] 1668 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 1845 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[30] 1854 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[20] 1762 33
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1 582 93
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/dvalid_pipe_0/delayLine[0] 1828 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1708 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[6] 1704 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][3] 1644 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[28] 1692 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][14] 1587 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[20] 1825 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1555 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[1][1] 1798 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[3] 1631 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2272 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_RNO[0] 1205 78
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[12] 1686 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[2] 1233 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 624 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[8] 1672 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1093 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[3] 1591 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 807 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1526 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2258 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2145 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[30] 1775 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[12] 1537 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2020 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[6] 1193 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[16] 1794 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_2_sqmuxa_1_i_0 1616 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[1] 1573 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[9] 826 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][4] 1791 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 682 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[22] 1717 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1829 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][1] 1667 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[14] 1827 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[8] 1684 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][10] 1630 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[31] 1886 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 794 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/cvalid_pipe_0/delayLine[2] 943 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[3] 1589 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[2] 1752 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 696 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/async2sync_0/delayLine[1] 1260 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[26] 1898 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[3] 1727 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/valid_pipe_0/delayLine[0] 1786 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[6] 1732 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 423 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1754 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][5] 1714 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/txrdy_int_RNI81SD 1598 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[8] 1734 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[5] 1679 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[28] 1777 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[26] 1581 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[2] 1543 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1779 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m137 1507 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 842 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 2036 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 2046 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[30] 1778 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[13] 838 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m186_2 1533 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[5] 1685 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1534 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[25] 1849 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_4 1538 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CA2_1.SUM[2] 1138 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[3]_3 1616 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1292 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][2] 1653 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[30] 1587 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[4] 1650 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_cnst_i_a3[1] 1696 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick_RNI2I2R[6] 1549 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1865 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[20] 1800 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1246 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1607 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1792 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/pipe1 1772 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[27] 1710 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_0/genblk1.delayLine[2] 1623 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_7 1565 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[3] 1655 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[13] 1813 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m268_3 1507 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 1159 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2235 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[4] 1734 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][3] 1793 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[4] 1644 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 425 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[3] 1728 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[7] 1677 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[17] 1794 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1765 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[3] 1582 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2019 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 458 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1995 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m172 1542 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][12] 1707 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2130 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_23 1562 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1610 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[5] 1643 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_RNO[1] 1590 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m146 1504 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[1] 1697 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[8] 1647 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_4_RNI4IK81 236 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m100 1532 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/cvalid_pipe_0/delayLine[0] 1218 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[6] 1637 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[20] 1770 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[0] 829 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[27] 1704 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[22] 1572 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1736 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[9] 1132 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[22] 1873 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1621 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[9] 1633 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 1255 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/cvalid_pipe_0/delayLine[0] 1265 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 806 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wEn 1646 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2126 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1864 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[2] 1569 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2022 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 978 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1716 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[1] 1635 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[6] 1575 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[29] 1894 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 1544 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[19] 1784 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m70 1513 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[3] 799 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_10 1605 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 730 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_0_RNIVJK81 225 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m200 1531 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[7] 1729 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_1_RNO 232 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/cvalid_pipe_0/delayLine[1] 408 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1876 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[2] 1584 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 430 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[22] 1720 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][2] 1800 25
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[7] 1330 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/op_eq.un11_dc_0 828 54
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[2] 1568 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[12] 1730 61
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[0] 1551 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preInBuf_wEn 1628 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 1533 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 771 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[2] 1543 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[2] 1641 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1768 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[1] 1524 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[30] 1733 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1203 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 829 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_RNIN40J[2] 1663 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m14 1338 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_r_3_0_a2 1591 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_3_RNO 226 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[29] 1875 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1840 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_5_i 1590 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1491 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/coef_on_outp 1266 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[4] 1551 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_0/genblk1.delayLine[1] 1625 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 717 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][3] 1617 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 2018 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[20] 1800 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1266 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2305 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[0] 1123 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m60 1530 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1552 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[27] 1777 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_9 1573 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[9] 1691 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 559 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_tr4_0_a4_0_a2 1161 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/ldMonitor 1667 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[16] 1798 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[5] 1705 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 722 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 796 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[22] 1855 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m6 1508 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][7] 1695 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m206_2 1542 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[23] 1906 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1864 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[5] 1640 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m135_1_1 1506 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[15] 1697 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[24] 1844 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][11] 1593 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[2] 836 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1130 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smStartLoad_s 1639 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[1] 795 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 709 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r[2] 1579 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1792 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/CFG2_BLKZ0[1]\\ 792 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 557 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1805 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[5] 1643 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2275 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNILMKI1[4] 1360 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[2] 1601 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[8] 1662 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[26] 1739 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dvalid_pipe_3/delayLine[2] 1429 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[22] 1778 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[31] 1871 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[21] 1795 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[12] 1809 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[3] 1184 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 1142 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[11] 1685 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[5] 1653 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1313 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1345 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1551 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[0] 1679 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[10] 1627 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m246 1544 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/upScale_4 1701 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1994 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 538 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[31] 1762 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[23] 1902 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1214 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][0] 1669 25
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNI8H482[2] 1198 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 715 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[9] 1719 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[1] 1801 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_0_sqmuxa_3_0_2 1633 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[1] 1580 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[5] 1565 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[10] 1677 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m191_i 1497 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2058 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[3] 1234 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 573 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[26] 1779 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 770 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][7] 1713 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_RNO[3] 1648 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_2_RNO 223 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 857 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[23] 1906 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_ns[2] 1660 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[5] 1567 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsmce[11] 1304 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 895 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/dvalid_pipe_0/delayLine[2] 1844 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1109 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNIR6412[2] 1194 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[19] 1809 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WEN_RNO 1181 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1624 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/init_rear_0/inp_tick 1643 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/cvalid_pipe_0/delayLine[1] 1211 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[5] 802 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[10] 1682 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[22] 1778 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r_RNO[2] 1579 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_9_i 1596 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1887 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1765 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1825 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 1406 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1312 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1646 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[7] 1625 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_1 238 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[9] 1756 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[30] 1888 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_4 1128 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 891 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[4] 830 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 398 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 604 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 603 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[6] 1707 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 597 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[13] 1687 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[13] 1813 37
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m38_i_i_o2_4 1378 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[7] 1195 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[3] 1638 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[12] 1792 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[4] 1600 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/dvalid_pipe_0/delayLine[0] 961 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1072 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[2] 1568 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2307 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m236 1543 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1900 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/dvalid_pipe_0/delayLine[0] 1561 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[11] 1731 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1254 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_3_RNIM35G 1134 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 759 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 642 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[4] 1711 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/bflyMonitor_RNO 1703 36
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[3] 1367 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2262 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[20] 1800 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[5] 794 51
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[7] 1238 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1814 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_3 1555 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_0_a2[5] 1185 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[21] 1797 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[25] 1738 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[21] 1792 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[2] 1806 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[0][1] 1594 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[15] 1788 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 261 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[14] 1830 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][7] 1576 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 879 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 1543 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[25] 1851 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 1895 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[7] 1686 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[6] 1607 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m206_2_1_0 1541 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[9] 1733 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[22] 1716 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[1] 1760 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 456 52
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1 581 67
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[28] 1838 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_121_i 1505 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[18] 1818 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][11] 1756 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 556 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1396 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1730 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[29] 1787 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_bit0_r2 1579 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[17] 1794 43
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_I_VALID_RNO_0 1287 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_5 1503 30
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count_RNO[1] 1440 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1108 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2117 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1023 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 458 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1731 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[6] 1680 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_3 217 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2331 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[1] 1676 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1985 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m79 1529 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[31] 1700 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[26] 1831 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/valid_pipe_0/delayLine[1] 948 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[6] 1661 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[9] 1719 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[10] 1592 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[3] 1727 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[0] 1575 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1788 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[18] 1804 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[0][0] 1592 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1532 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1557 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2006 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2205 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/BLK_EN_inst 818 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 914 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[7] 1730 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[9] 1632 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[22] 1722 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[4] 1587 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[12] 1764 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[23] 1715 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/OEN 1464 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.N_199_i 1526 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1633 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[11] 1812 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 977 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m80 1540 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[4] 1581 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 483 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][4] 1653 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dvalid_pipe_3/delayLine[0] 1434 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1587 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_0 1133 43
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[0] 1364 43
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6 1163 162
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[1] 1712 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 1844 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 213 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1757 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 340 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[2] 1561 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[24] 1772 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 973 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[10] 1687 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[2] 1452 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m69 1521 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[1] 1632 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[26] 1828 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[13] 1201 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1897 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 258 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/rAmsb_r1 1674 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 965 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preSwCross_r 1583 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1143 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RD_ENABLE_1 1197 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/valid_pipe_0/delayLine[1] 632 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rx_en 1470 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[15] 1785 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[3] 1717 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1811 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[4] 794 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_180_i 1567 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1984 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1490 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[18] 1815 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[5] 1737 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel[2] 1644 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 194 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[12] 1738 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[1] 1705 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[11] 1301 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[5] 1605 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[9] 1735 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[5] 1611 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1525 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][5] 1664 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[28] 1824 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/dvalid_pipe_1/delayLine[0] 801 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[0] 1341 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_8 1538 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[7] 1625 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[20] 1825 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1699 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WEN 1344 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1787 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[23] 1712 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 976 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rLastStage_r 1609 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[0] 1579 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m135 1504 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1395 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 482 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1545 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1022 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 267 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1624 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[24] 1726 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[3] 1722 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/edge_detect_0/outp 1699 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 639 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[0] 1578 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1753 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m168_i 1520 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 488 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preInBuf_wEn_2_sqmuxa_i_0 1621 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[21] 1800 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[9]_3 1615 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/stop_strobe 1435 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 715 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[17] 1830 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[4] 1634 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2116 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2006 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[26] 1709 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 869 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m170_2_1 1532 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_pad.dvalid_pipe_2/delayLine[1] 1263 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/rstAfterInit_3 1536 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[23] 1837 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[21] 1819 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m2_i 1519 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][1] 1650 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[10] 1708 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 627 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[5] 1583 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[5] 1588 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1647 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1707 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2174 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[8] 1739 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/end_of_ngrst_0/d_flop1 1269 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[26] 1785 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick_RNI1QDV[5] 1559 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 221 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[28] 1714 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_C2_1.SUM[2] 1136 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[12] 1730 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/valid_pipe_0/delayLine[0] 1569 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[24] 1776 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/valid_pipe_0/delayLine[2] 1532 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[1] 1634 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1791 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[5] 1732 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1695 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[10] 1685 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][9] 1644 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 279 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1775 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m170_1 1531 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[27] 1782 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[6] 1711 36
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_tr4_0_a4_0_a2_4 1162 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1803 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count[0] 1449 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][3] 1558 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[2] 1665 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/genblk1.RXRDY 1468 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 868 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[5]\\ 802 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 241 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_cntr[1] 1662 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1131 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0[1] 1498 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1213 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1757 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/dvalid_pipe_0/delayLine[2] 962 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[29] 1717 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[0] 1706 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[4] 1679 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 303 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[2] 1550 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 805 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1432 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[26] 1695 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 474 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1843 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][10] 1648 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[12] 1828 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[11] 1826 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preInBuf_wEn_2_sqmuxa_i_a2_0 1625 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m81 1502 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[4] 1634 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_14_i 1527 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1643 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_4/genblk1.delayLine[1]_3 1620 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a3[8] 1495 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/dvalid_pipe_0/delayLine[2] 1557 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[3] 1649 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1394 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/hold_zero 835 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[10] 1734 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[16] 1790 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[3] 1603 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 421 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[6] 1723 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][7] 1706 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2330 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[7] 1631 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_clock_int 1703 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1082 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_a3_0_3_0_3[6] 1240 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[31] 1779 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 2044 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 973 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[29] 1777 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1579 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_RNO 1651 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m128 1496 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[6] 1760 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[16] 1809 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[25] 1897 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[5] 1738 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1853 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[0] 1727 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m186_2_1_0 1535 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 410 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state[0] 1431 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[1] 1339 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 975 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1848 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/OEN_RNO_0 1474 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count[2] 1443 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m128_i 1520 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[2] 1192 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1646 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 1302 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1542 46
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0 1152 162
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[0] 795 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1334 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1839 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[3] 1754 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[28] 1887 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 472 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2213 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2197 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[12] 1798 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m13 1519 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[0] 1609 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2162 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[2] 1345 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1915 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m247 1529 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 1830 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[24] 1863 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1528 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1431 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[3] 1631 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[10] 1526 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_1_inst 786 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 438 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[3] 1651 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2042 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[10] 1734 60
set_location reset_sync_0/reset_sync_0/un1_D 1163 3
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 509 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 608 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][3] 1646 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 263 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[8] 1657 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/RAM_REN_0_sqmuxa_0_a2_0_a2 1356 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1600 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1767 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBuf_wEn_frEdge 1631 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][6] 1617 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1834 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 588 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][0] 1658 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1805 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/dvalid_pipe_0/delayLine[1] 1374 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[0] 1638 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[5] 1703 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[19] 1807 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1719 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[4] 1680 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 208 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[22] 1884 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[30] 1791 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 255 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][15] 1697 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 323 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_clock 1664 43
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_tr4_0_a4_0_a2_3 1160 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[26] 1732 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[5] 1580 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[29] 1718 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[3] 1724 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[15] 1805 39
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0[14] 1321 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[10] 1623 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[28] 1893 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 746 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_2_4[0] 1570 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1530 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_223_i 1495 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[2] 1558 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1909 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 278 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 531 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[4] 1586 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/MAIN_FSM.DATA_WEN_6_f0_i_o2 1205 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m130 1494 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 272 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[1] 1700 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1635 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1627 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1107 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 769 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][15] 1805 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1442 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[4] 1652 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1753 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 390 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 508 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 493 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[10] 1659 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/dvalid_pipe_0/delayLine[2] 2064 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[0] 1671 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][2] 1676 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][3] 1650 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1580 25
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_sm.rx_state19_NE_i 1459 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[2] 1632 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1766 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 2034 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1552 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_5_inst 796 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1702 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][2] 1550 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[0][2] 1589 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state[1] 1433 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[15] 1808 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[6] 1645 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[27] 1713 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 566 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[6] 797 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[1] 1640 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[30] 1698 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[12] 1777 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[20] 1594 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[8] 798 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[3]\\ 798 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2053 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[6] 1648 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r_RNO[0] 1597 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[1] 1701 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[18] 1803 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1832 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[9] 1553 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1766 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1810 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_6 1590 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[11] 1804 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[29] 1716 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[7] 1628 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_DATA_OUT_0_sqmuxa_i_a3_0 1597 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[0] 1326 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1092 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_10 1578 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[12] 1774 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1706 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[14] 825 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_bit0_r2 1600 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/RAM_REN 1549 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[4] 1714 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/FFT_IM_REN 1548 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1245 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[11] 1628 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m248_2 1505 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][2] 1649 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[23] 1784 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1530 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[16] 1834 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_1_i_a2 1473 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1817 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[4] 1551 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt_1_sqmuxa_0_a4_0 1429 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[7] 1672 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 384 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[23] 1724 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[1] 1731 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[6] 1644 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 853 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[7]_3 1614 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1915 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[30] 1885 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 1529 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[4] 794 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_2/genblk1.delayLine[1]_3 1613 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/un1_ldRiskOV 1780 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[0] 1620 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 952 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][12] 1771 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[30] 1791 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m283 1554 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1230 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 372 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[6] 1733 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/tc_7 1635 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m59_2_0 1512 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[2] 1637 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1607 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[5] 1614 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1644 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 286 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[7] 1648 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 795 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1551 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1654 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 207 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/startFFT_dly_0/genblk1.delayLine[1] 1615 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[4] 1714 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_1_i_tz 1468 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[6] 838 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[0] 1622 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[4] 1653 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 239 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 424 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[7] 1737 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1466 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[5] 1601 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[6] 1649 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1765 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1765 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[7] 1494 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 219 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[2] 1675 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[4][1] 1703 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 437 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[10] 1626 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_12 1566 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1828 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[14] 1671 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[1] 1672 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 346 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[14] 1787 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[4] 1560 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1091 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[6] 1720 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 964 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1604 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[13] 1806 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m256_2_1_1 1503 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1705 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1725 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[2] 1639 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[3] 1632 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[23] 1724 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1854 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[6] 1753 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2188 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[4] 1634 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1645 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/startFFT_dly_0/genblk1.delayLine[1]_3 1615 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[17] 1654 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2152 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dvalid_pipe_3/delayLine[3] 1076 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[20] 1806 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[4] 1692 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[19] 1803 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_RNO 1612 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1489 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 963 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[1] 1591 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[1] 1666 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[6] 1716 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[23] 1856 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_2_0_o3_RNIVIPF 1555 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1909 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 1300 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[5] 1552 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[3] 1323 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1622 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a2_7[5] 1186 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[5] 1708 43
set_location reset_sync_0/reset_sync_0/dff_2 1156 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2_RNI5V1I1[1] 218 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[6] 1636 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m10 1444 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 663 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1863 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 1842 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[5] 1236 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 974 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2257 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[0] 1599 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m167_2 1541 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[0] 1607 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[9] 1642 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[2] 1724 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[8] 1659 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 297 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1088 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/dvalid_pipe_0/delayLine[0] 1249 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1021 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[2][0] 1651 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[5] 1681 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1231 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[7] 1736 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[0] 1541 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m23 1507 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m146_2_1 1501 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc 1590 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[4]\\ 808 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1236 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 424 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 555 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 821 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2_RNIPRM6[1] 1131 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[0] 1670 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 758 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 650 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 953 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[14] 1321 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][5] 1635 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1344 52
set_location reset_sync_0/reset_sync_0/dff_9 1162 4
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_RNIMANU[3] 1193 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[20] 1760 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/bflyMonitor_RNO_0 1696 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m85 1497 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[2] 1758 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2005 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rw_1/genblk1.delayLine[0] 1622 40
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i[0] 1285 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulsei 1206 78
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[5] 1369 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1418 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 519 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[30] 1786 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][1] 1546 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[1] 1597 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 678 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 659 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[0] 1578 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 626 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WEN_RNO_0 1604 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/un1_din_valid 834 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_addrP_w[6] 1604 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/CFG2_BLKX0[0] 1559 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[4] 1655 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[1] 1701 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 287 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[13] 1775 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2338 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[3] 1729 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[3] 1575 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[4] 1712 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[3] 1724 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m148 1579 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 972 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx 1652 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 1158 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[16] 1796 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[5] 1712 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 674 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1359 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 565 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick_RNI2O222[6] 1548 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m41_1 1506 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 820 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2187 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[6] 1594 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[20] 1804 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[11] 1759 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[5] 1704 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[3] 1567 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2151 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[26] 1776 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[19] 1807 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 240 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[6] 1760 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 656 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2219 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1841 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[4] 1585 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8[2] 1201 78
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m260 1506 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[6] 1578 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1868 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[30] 1798 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[14] 1834 33
set_location reset_sync_0/reset_sync_0/dff_14 955 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m229_3 1496 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_4_inst 1683 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[0] 1673 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1527 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state_ns_a3[1] 1647 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[20] 1790 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m15 1540 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1969 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1178 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_1_RNO 238 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[1] 1669 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick[2] 1593 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[24] 1782 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[13] 1819 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[30] 1773 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/valid_pipe_0/delayLine[2] 1244 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_4/genblk1.delayLine[0]_3 1627 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1852 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[6] 1723 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][6] 1649 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smBuf_full_2_sqmuxa_i 1636 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1823 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[13] 1672 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1075 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_30 1574 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_1_i_a2_1_0_RNI87B81 1177 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1586 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[22] 1778 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[25] 1775 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 732 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[23] 1773 28
set_location reset_sync_0/reset_sync_0/dff_15 1205 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[5] 1605 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1838 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[4] 1735 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 228 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/op_eq.un11_dc_4 837 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc_3_0_a2_2 1585 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][3] 1645 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[9] 1718 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[3] 1679 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 757 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][4] 1789 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][15] 1784 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1840 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[16] 1752 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m109 1542 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[19] 1811 27
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_I_VALID 1247 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/valid_pipe_0/delayLine[0] 1270 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNIN84C1[13] 1206 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][4] 1788 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[4] 1581 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[5] 1729 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[2] 1667 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1645 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[7] 1677 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[3] 1733 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count[1] 1440 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 285 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1311 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m154 1565 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][6] 1571 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1852 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[29] 1717 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[7] 1646 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[13] 1806 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[16] 1814 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[1] 1596 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m45 1496 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[9] 1225 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][12] 1764 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[1] 1610 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m177 1529 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1851 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[5] 1645 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[20] 1805 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_0_inst 821 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_0_sqmuxa_0_a4 1441 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1713 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2_RNI3GS12[2] 1130 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[0] 1584 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_22 1495 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m60_i 1502 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[3] 1701 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1212 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1252 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][14] 1771 22
set_location PF_ccc_0_0/PF_ccc_0_0/pll_inst_0_DELAY 2467 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 544 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][2] 1658 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1225 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_0_sqmuxa_1_0_a2_0_a2_RNI4H0G 1352 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][14] 1770 22
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[1] 1713 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][11] 1759 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1917 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[6] 1602 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][13] 1783 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 962 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1540 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[3] 839 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 530 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1347 46
set_location PF_init_monitor_0_0/PF_init_monitor_0_0/I_BEN_6 1750 1
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[18] 1809 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2054 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[5] 1182 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_n0_i_a2 1584 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1106 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[0] 1633 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1202 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m264_2_1 1518 21
set_location PF_ccc_0_0/PF_ccc_0_0/pll_inst_0 2460 5
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[14] 1789 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preOutBuf_wEn_1_sqmuxa_0_a2 1631 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1630 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/dvalid_pipe_1/delayLine[0] 1266 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[0] 1638 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[3] 1645 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[1] 1565 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2294 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[9] 1717 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_23_i 1566 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 1405 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[12] 1809 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_s0_0_a2 1438 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1557 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Gate1_15 1583 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1_0[0] 1710 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[4] 1597 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2115 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1764 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[30] 1786 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2233 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_clock5 1664 42
set_location reset_sync_0/reset_sync_0/dff_5 1155 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 543 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_1_0[0] 1490 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[3] 1591 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1903 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[1] 1629 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[25] 1899 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1829 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m51_i 1517 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][4] 1652 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 451 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[13] 1821 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[5] 1714 45
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_shift.rx_shift_11_fast[7] 1332 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1310 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[28] 1788 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 998 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[26] 1879 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_a3_0_3_0_4[6] 1239 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[4] 1564 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1035 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1704 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[2] 1569 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 616 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1886 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 759 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/valid_pipe_0/delayLine[0] 1248 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[6] 1598 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/dvalid_pipe_0/delayLine[2] 1239 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[4] 1532 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[9] 1637 28
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm[4] 1294 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1375 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1524 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1839 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/valid_pipe_0/delayLine[2] 630 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_8_RNO_0 1543 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1062 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 694 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1722 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2121 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_RNILUGN[3] 812 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_run_2_sqmuxa_i 1626 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[18] 1808 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][15] 1802 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_0_RNO 1133 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rStage_r_RNO[0] 1577 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[10] 1738 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m126 1493 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/cvalid_pipe_0/delayLine[1] 1262 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1957 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1752 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[7] 1659 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[1] 1716 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[3] 1556 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/un1_samples7_1_0 1437 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[6] 1604 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1070 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1983 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_2/genblk1.delayLine[0]_3 1629 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1541 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[25] 1779 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[0] 1671 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1621 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[3] 1768 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 277 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_7 1554 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smBuf_full 1616 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1639 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1891 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rAwA_w_0_a2_1 1557 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][4] 1797 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1251 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[3] 1537 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r_5[1] 1584 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[4] 1594 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1634 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick_RNI06071[4] 1550 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1417 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1593 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2306 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1059 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/last_bit[0] 1462 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[20] 1801 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][2] 1627 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[4] 1711 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/cvalid_pipe_0/delayLine[2] 1782 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a3_0_5[10] 1564 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[7] 1623 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[30] 1876 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[4] 1752 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1615 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2334 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldValid 1634 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][8] 1601 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[2] 1598 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 315 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[30] 1888 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[4] 1568 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[31] 1781 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[13] 1816 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[18] 1821 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1267 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 961 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1369 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[6] 1655 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m16_2 1431 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1034 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[14] 1826 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[2] 1678 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[6] 1647 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[12] 1772 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine[2] 1202 79
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm[2] 1194 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_2_sqmuxa_1_i_a2_2 1566 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 804 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[7] 1737 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/valid_pipe_0/delayLine[1] 1787 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[27] 1708 33
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[3] 1126 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[9] 1590 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1789 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 2033 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[1] 1602 40
set_location reset_sync_0/reset_sync_0/dff_10 1161 4
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[6] 1558 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1643 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1430 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 202 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state[2] 1660 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/valid_pipe_0/delayLine[0] 720 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[6] 1714 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1651 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r_2_sqmuxa_i 1593 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1670 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 2017 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 420 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[27] 1710 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[31] 1890 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_1[2] 1693 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[2] 1533 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m152 1564 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[30] 1701 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 529 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[2] 1609 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][4] 1618 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[1] 1542 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1982 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[2] 1593 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[2] 800 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_5 1558 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1083 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 901 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][15] 1693 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[3] 1550 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[7]\\ 781 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[10] 1761 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][3] 1545 40
set_location reset_sync_0/reset_sync_0/dff_12 835 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[18] 1807 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_14 1573 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/dvalid_pipe_0/delayLine[1] 612 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_6_RNO 1133 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][15] 1808 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_r2[0] 1605 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2120 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[1] 1640 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[14] 1812 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2114 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[3] 1715 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA[0] 1572 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[7] 1728 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1671 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 450 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1827 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[13] 1807 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 919 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[9] 1752 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/dvalid_pipe_0/delayLine[0] 1859 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/stop_strobe_1_sqmuxa_0_a4 1435 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1546 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m264_2_1_0 1516 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1910 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[1] 1551 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][13] 1766 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[6] 1690 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 292 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 328 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc_3_0_a2 1587 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][0] 1621 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1033 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 295 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[5] 1643 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[21] 1816 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[28] 1714 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 745 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smPong_2_sqmuxa_i_i 1616 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][13] 1804 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[2] 1734 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[4] 1560 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[18] 1795 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2_RNI7QIT[1] 1135 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[5] 1549 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[0] 1604 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[3] 1692 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[26] 1779 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1773 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[30] 1780 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[11]\\ 835 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2[2] 237 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[5] 1583 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[11] 1796 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/un1_startFFT 1702 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][11] 1763 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 436 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[5] 794 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1696 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[10] 836 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[6] 1683 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_8 1552 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1816 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_r2[4] 1560 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.N_220_i 1505 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[15] 1696 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2223 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[2] 1678 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m12_i 1520 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[0] 1646 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m32 1565 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[6] 1222 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rx_en_RNO_2 1467 42
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RD_ENABLE_0_i_0_0 1196 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 471 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1669 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[0] 1668 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r[2] 1585 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1826 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[25] 1758 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_0_sqmuxa_i_a2 1610 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 768 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 392 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m206_2_1 1539 21
set_location reset_sync_0/reset_sync_0/dff_6 1154 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/preRdValid_2_sqmuxa_1_i_a2_2_0 1579 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[7] 1671 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[19] 1769 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[27] 1715 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_0_o2[5] 1413 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[14] 1810 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1441 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1346 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_addrP_w[6] 1579 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 631 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[6] 1698 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[11] 1813 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1618 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[1] 1198 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2196 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 866 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1528 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1190 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/tc 1587 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_cntr[3] 1657 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[0] 1598 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[5] 1694 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[12] 1773 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[10] 1628 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2122 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 675 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[4] 1368 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_C2_1.SUM[2] 237 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1408 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1861 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/CFG2_BLKX0[0]\\ 806 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[1]\\ 789 54
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel[1] 1645 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[3] 1650 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1712 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1730 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][3] 1657 40
set_location reset_sync_0/reset_sync_0/dff_13 836 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2093 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count[3] 1442 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_RNO[2] 1204 78
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1825 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 1296 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][0] 1572 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m229 1494 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[30] 1703 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_bflyRiskOV_w_3 1720 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[16] 1803 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1856 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[29] 1766 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1837 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[3] 1669 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a2_6[5] 1209 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[8] 1656 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1916 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1282 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2241 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1580 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[11] 1685 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[22] 1757 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 1831 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1767 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1851 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 507 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1613 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2271 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1838 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][6] 1760 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2274 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 266 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[1][0] 1653 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1286 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m8 1432 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1549 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2295 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1905 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine[0] 1203 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2[0] 228 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[12] 1793 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[14] 1826 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 254 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[31] 1716 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[25] 1738 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m175 1539 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[23] 1772 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[29] 1870 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[14] 1787 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2095 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[2] 1676 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][12] 1770 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[4] 1652 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1412 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 470 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m274 1563 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 310 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_0_sqmuxa_4_0_a2_0_a2 1208 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_RNIB4LR3[0] 1724 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r2[3] 1582 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[0] 1638 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1622 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2222 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[12] 1810 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[21] 1795 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1837 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_1 1564 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[21] 1817 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[4] 1707 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[22] 1870 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[10] 1706 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][12] 1806 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m102 1541 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_bflyRiskOV_w 1693 36
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_0_a2_0[2] 1349 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/N_256_i_i_o2 1384 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m7 1538 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1701 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_pulse 1661 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/cvalid_pipe_0/delayLine[2] 1122 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[0] 1622 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[29] 1767 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[2] 1702 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[6] 1682 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1625 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1729 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_3_inst 814 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 720 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_sm.rx_state19_NE_0 1455 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[0] 1715 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 327 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[4] 1665 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[18] 1785 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[9] 1634 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/cvalid_pipe_0/delayLine[2] 1511 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 758 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[29] 1786 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[7] 1531 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[9] 1726 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_RNIJFJM2[1] 1670 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1562 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[5] 1596 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[12]\\ 839 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_6 1493 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[4] 1760 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m18 1433 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[4] 1654 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/valid_pipe_0/delayLine[0] 1785 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1194 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[17] 1647 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_2[0] 1561 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1729 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m146_2_0_1 1492 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[3] 798 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][8] 1753 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1323 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_24 1560 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a3[7] 1491 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 938 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[4] 1678 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[16] 1792 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1426 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2_RNO[0] 1132 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2060 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_C2_1.SUM[1] 1134 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 457 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 506 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[2] 1629 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1830 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1651 39
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_cntr[2] 1665 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dvalid_pipe_3/delayLine[1] 1438 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[29] 1765 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[19] 1826 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[17] 1730 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_DATA_OUT_0_sqmuxa_i_a3 1600 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 878 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1887 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[5] 1641 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m272_1 1518 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 1298 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0_a2_0_4[14] 1320 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_2_0_o3 1550 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1756 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1309 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[12] 1798 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/loadOver_w 1635 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2041 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 554 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[27] 1706 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1609 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/txrdy_int_1_sqmuxa_i 1666 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2299 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count[1] 831 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 719 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 253 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 528 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[24] 1780 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[8] 1496 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[2] 1566 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 1306 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[27] 1723 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[23] 1784 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/valid_pipe_0/delayLine[1] 1536 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1814 55
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_cnt.xmit_bit_sel_3_a3_0_a2[0] 1654 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_1_i_a2_1 1179 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 890 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[1] 1640 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1455 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[12] 1810 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_6 1603 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/tA[0] 1555 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2186 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1020 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[30] 1882 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1478 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[7] 1563 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1599 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2150 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[15] 1791 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[30] 1701 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[3] 1710 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[16] 1822 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[17] 1823 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 691 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[1] 1560 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 653 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[2] 1718 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1540 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[28] 1826 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[1] 1705 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smStartFFT 1617 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[17] 1786 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a2[5] 1202 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 206 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[24] 1723 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[6] 1644 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count_RNO[3] 1442 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r[0] 1591 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 225 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 841 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 250 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[4] 1737 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q[3] 1588 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2085 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[26] 1736 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[5] 1546 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[14] 1784 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[8] 1709 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine[0]_3 1628 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 290 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[27] 1716 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m160_1 1553 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1037 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[19] 1804 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[12] 1651 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/valid_pipe_0/delayLine[1] 728 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_0_inst 1803 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1533 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1886 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m51 1531 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[5] 1762 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1828 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/xmit_cntr[0] 1656 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rw_1/genblk1.delayLine[1] 1620 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[11] 1814 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[18] 1794 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1358 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 709 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1739 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[14] 1810 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_19 1552 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2256 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1189 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m227 1505 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[18] 1800 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m264_2 1515 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 435 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 951 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 377 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1241 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_7_RNO 1137 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[8] 1734 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2300 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1917 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[14] 1827 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 939 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1530 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1533 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[19] 1809 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[2] 1730 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1598 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[14] 1823 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_a2[3] 1445 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[5] 1685 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1539 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wEn_P_r 1645 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1177 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/tc_7_1_0 1641 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[25] 1735 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1069 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[4] 1541 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[20] 1806 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[4] 1235 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_0 1544 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1658 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[0] 1338 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[22] 1717 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_5 236 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][10] 1695 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[17] 1802 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_2 1495 24
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[5] 1732 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[4] 1619 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2052 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[1] 1662 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[6] 1683 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[6] 1735 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1981 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_2_inst 802 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m75 1491 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[27] 1711 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[5] 1720 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1488 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 819 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[25] 1873 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[15] 1797 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1644 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2137 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[6] 1489 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1142 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[9] 1683 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1916 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][15] 1780 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][14] 1696 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[15] 1786 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1710 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1693 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBuf_wEn 1633 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1801 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 422 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1515 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 1155 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[16] 1792 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[26] 1690 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_0_o2_3[14] 1322 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_5_i 1566 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][4] 1712 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1114 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[14] 1788 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_5 1576 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1465 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 217 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[7] 1733 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1726 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1885 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m63 1537 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][5] 1582 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[7] 1153 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[3] 1549 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1368 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 912 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[0] 1574 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 805 52
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_0[10] 1566 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_0_inst 1813 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 338 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[15]\\ 837 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/tc 1675 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[2] 1611 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[7] 1668 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[9] 1698 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 781 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_a4[3] 1337 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1443 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 2319 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[2] 1695 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 840 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][10] 1758 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[3] 1718 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[26] 1829 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[21] 1807 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/R_ADDR_5_inst 813 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 690 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1046 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1755 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[3] 1739 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[17] 1799 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1559 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[4] 1695 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][11] 1762 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[2] 1561 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[23] 1753 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[14] 1779 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2185 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[21] 1796 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][4] 1705 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/tA_r[0] 1548 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m242_1_2 1540 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1325 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[0] 1726 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 2035 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_run_1_sqmuxa 1629 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2149 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[15] 1732 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count[1] 795 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_2 1516 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[14] 1791 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[30] 1702 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2318 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_r[2] 1563 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1575 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_a2_1_0[0] 1428 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1850 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 409 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt[3] 1453 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[6] 838 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[17] 1794 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1311 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2327 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1045 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m119 1528 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[22] 1781 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 865 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[18] 1793 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 818 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m65_2_1 1515 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1653 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_3_inst 831 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[9] 1685 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[6] 1733 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m96 1492 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m119_1_0 1527 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 648 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1682 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[1] 1560 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[27] 1775 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][10] 1761 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2288 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[30] 1730 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1782 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 997 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m245 1504 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[1][12] 1803 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[25] 1729 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[0] 1674 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine[0] 1628 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[3] 1729 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m186_2_1 1563 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[24] 1904 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[1] 1608 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick[1] 1544 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[0][1] 1789 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[9] 1699 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[1] 1709 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1130 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1138 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[3] 1335 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[12] 1803 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[5] 1639 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[0] 1676 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 889 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1616 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1846 28
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m38_i_i_o2 1377 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smStartLoad 1639 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[3] 1654 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_9_RNO 1542 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[17] 1802 54
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_2_5[0] 1571 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[18] 1805 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m229_2 1506 33
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[4] 1127 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_4_inst 803 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2325 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/dvalid_pipe_1/delayLine[1] 1271 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[0] 1668 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[2]_3 1612 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[10] 1737 57
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[5] 1336 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1310 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 681 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[4] 1669 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[22] 1770 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsmce[1] 1493 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 867 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/un1_offsetPQ_w_5 1602 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1634 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[24] 1880 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 542 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1956 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1582 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[21] 1786 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m24 1559 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/dvalid_pipe_0/delayLine[1] 714 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[22] 1880 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 950 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[25] 1896 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1681 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][6] 1640 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[17] 1803 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1827 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[4] 1320 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[14] 1541 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1759 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[13] 1739 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[31] 1714 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 469 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[15] 1782 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[16] 1812 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1783 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/samples[2] 1333 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/init_rear_0/outp 1642 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 1550 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m77 1504 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[10] 1622 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[28] 1857 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1754 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1321 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/cvalid_pipe_0/delayLine[0] 930 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_29 1551 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[18] 1800 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1166 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smPong 1627 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[0] 1607 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1904 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1849 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1668 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[12] 1799 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1633 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 436 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[20] 1801 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[3] 1648 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[7] 1623 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[13] 1820 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1663 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 674 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[24] 1780 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[2] 537 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[24] 1723 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[5] 1647 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 434 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/ldMonitor_RNO 1667 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2203 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[17] 1758 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[4] 1613 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 1549 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[19] 1829 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[3] 1674 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m237_i 1517 27
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE_1[0] 1293 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[5] 1658 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[20] 1804 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[7] 1675 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 532 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_3/genblk1.delayLine[1] 1611 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[11] 1814 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/timer_r[3] 1589 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1237 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 378 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 713 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[2] 1328 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[3] 1546 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1790 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[1] 1232 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[23] 1877 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[11] 1817 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[14] 1771 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[1][1] 1587 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_0_RNO 216 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][1] 1801 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[31] 1813 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1993 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/txrdy_int 1659 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[1] 1650 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_1_RNI2IK81 231 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[18] 1808 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/tc 1635 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/valid_pipe_0/delayLine[2] 447 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1320 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1058 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[7] 1563 45
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR_RNIB1S52[1] 1286 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 505 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1477 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[25] 1849 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CA2_1.SUM[2] 229 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[10] 1707 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[6] 1718 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/valid_pipe_0/delayLine[1] 551 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 541 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/CFG2_BLKX0[0] 1664 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[24] 1577 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[1] 1603 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m196_2_1 1494 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[2] 1698 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[19] 1805 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[11] 1813 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][5] 1556 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2048 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1727 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[19] 1826 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 987 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[2] 1566 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2335 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[8] 1131 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[8] 1769 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 492 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1239 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WEN 1181 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[9] 1644 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_8 1561 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2040 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][4] 1626 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[1] 1727 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 676 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 252 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[4] 1574 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[19] 1817 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[13] 1687 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[1][0] 1588 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m245_1_1 1500 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1764 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 2017 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1599 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 1836 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1333 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[23] 1907 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[7] 1683 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[14] 1697 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[10] 1682 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[25] 1758 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1947 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[24] 1722 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1617 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[17] 1649 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[25] 1759 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[11] 1816 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_2_inst 820 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 986 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 937 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_bit_cnt_0_sqmuxa_0_a4 1436 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 265 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1795 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[10] 1648 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[14] 1690 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[2] 1648 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/BLK_EN_inst 1846 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_26_i 1562 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_rdy_0_sqmuxa 1618 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 235 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2323 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[13] 1770 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1992 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/cvalid_pipe_0/delayLine[1] 929 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1885 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_shft_stage_10_i 1598 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[0] 1656 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1611 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[0] 1696 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[6] 1725 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[9] 1733 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 877 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1057 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][9] 1756 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[21] 1790 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/load_done 1635 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[15] 1754 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wEn_Q 1650 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 655 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 337 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimerTC_tick 1621 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1085 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[21] 1801 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1549 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 942 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un5_outQ_axb_0_i_0 1668 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m111_1_2 1539 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1946 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 828 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_2/genblk1.delayLine[0] 1614 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_0_inst 1859 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_0/genblk1.delayLine[0] 1630 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 431 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[13] 1797 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[5] 1731 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 2263 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1920 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_4/genblk1.delayLine[0] 1627 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[23] 1696 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][1] 1620 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][7] 1646 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_0_inst 1535 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/rA_r[2] 1608 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_3_0_a2_1_1 1594 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/cvalid_pipe_0/delayLine[2] 1201 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[12] 1774 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_18 1493 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2221 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1808 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/un1_rst_3 1622 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[21] 1776 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wEn_P 1645 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2_RNIVBD9[1] 235 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[0] 1638 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0[11] 1301 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 375 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[16] 1788 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 224 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/startFFT_dly_0/genblk1.delayLine[0] 1618 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1902 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1129 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1548 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_ns_1_0_.m16_1 1430 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1 1740 66
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[1] 1602 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1610 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[4] 1678 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[6] 1574 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 1512 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[18] 1768 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][4] 1706 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1597 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][9] 1596 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[0] 1595 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 1161 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state[0] 1649 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[1] 1610 37
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_ON_RNO 1229 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[2] 1639 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2_RNI5AHD3[2] 234 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[28] 1878 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 481 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[17] 1822 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[8] 1671 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[9] 1593 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[16] 1802 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[0] 1704 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[2] 836 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_1_inst 1670 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 388 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_2/genblk1.delayLine[0] 1629 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2329 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1285 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1623 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[0] 1657 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[9] 1553 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[21] 1790 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1799 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[6] 1547 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[11] 1796 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_10 1500 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[0] 1621 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 876 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[25] 1694 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/pre2_sync_rw_0/genblk1.delayLine[0] 1604 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[14] 1785 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[19] 1807 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[24] 1724 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1765 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[3] 1684 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1238 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 602 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1044 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m268_1_0 1506 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[11] 1815 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2113 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[21] 1778 42
set_location reset_sync_0/reset_sync_0/dff_7 1153 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[2] 1633 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[13] 1817 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[4] 1708 45
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[4] 1607 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_2/genblk1.delayLine[0]_3_0_a2 1614 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 227 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[22] 1797 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[19] 1767 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 2320 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1464 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/R_ADDR_4_inst 823 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m93 1526 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/valid_pipe_0/delayLine[0] 693 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1778 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1762 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[0] 1231 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1826 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[29] 1855 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[15] 1812 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r[1] 1584 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 2304 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 386 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2339 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[15] 1819 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1723 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 518 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 1481 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[5] 1567 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1070 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1628 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1411 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 711 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[6] 1564 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 205 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_3_0_a2 1590 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1968 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1854 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 936 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_cnst_a2[5] 1602 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[25] 1899 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/dvalid_pipe_0/delayLine[2] 214 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[8] 1683 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_byte[1] 1322 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[6] 1680 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 2269 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 480 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1738 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1559 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 301 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[2] 1714 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[1] 1620 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1261 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr[2] 1718 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_63_i 1517 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/offsetPQ_r1[0] 1581 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1476 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/make_xmit_clock.xmit_cntr_3_1.SUM[3] 1657 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 193 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1878 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[4] 1586 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1632 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 817 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1105 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1721 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[4][0] 1652 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[6] 1642 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un1_offsetPQ_w_8 1574 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WEN 1598 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1308 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1068 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[13] 1765 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2312 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m14 1538 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 276 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1393 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[0] 1665 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_i_RNO[0] 1499 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/twid_wEn_0_sqmuxa 1537 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/BLK_EN_inst 1669 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[2] 1639 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1885 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2278 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[8] 1660 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[12] 1824 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m233 1491 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[3] 1616 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 433 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[2] 1678 37
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel_RNO[1] 1645 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[26] 1780 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][2] 1557 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m59_2_1 1514 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 672 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[5] 1578 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[10] 1662 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick2[2] 1559 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[3] 1673 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 380 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FILTER_COMPLETE_RNO_0 1288 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 383 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[8] 1609 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 855 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[4] 1342 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/sync_rAwA_w_0_a2 1604 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[1] 1672 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][8] 1577 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_wA[4] 1684 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/ctrl_dly_0/genblk1.delayLine[3][1] 1728 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_valid 1622 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[28] 1887 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_2_inst 1832 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[5] 1678 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][15] 1785 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 354 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 685 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][3] 1645 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[4] 1681 43
set_location reset_sync_0/reset_sync_0/dff_11 831 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_0_inst 1680 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_RNIARO71[1] 1722 51
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_full_int_1_sqmuxa_i 1456 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[1] 1700 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2220 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[10] 1627 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[6] 797 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1273 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[26] 1808 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[15] 1797 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 199 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1753 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[6] 1649 18
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 996 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[7] 1736 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[14] 1141 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 517 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][14] 1688 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1141 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 500 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[27] 1889 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wEn_Q_r 1654 40
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[5] 1733 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[14] 1812 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1414 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2173 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[13] 1820 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1776 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 638 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m196_1 1504 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/BLK_EN_inst 828 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[9] 1615 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[17] 1803 51
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[3] 1562 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_28 1570 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1912 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rStage_dly2/genblk1.delayLine[1][2] 1595 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][2] 1540 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_5_inst 1726 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 669 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/dvalid_pipe_0/delayLine[0] 1360 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[11] 1806 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][10] 1769 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 2041 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/sync_ngrst_0/genblk1.delayLine[1] 1209 79
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_state_s1_0_a4 1434 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1848 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 379 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[22] 1873 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1442 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m124 1525 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[6] 1646 27
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rx_shift[2] 1334 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][11] 1768 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/un4_swCross_w[0] 1582 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1454 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/CFG2_BLKZ0[0]\\ 799 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[5] 1680 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1538 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[10] 1736 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[29] 1787 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[20] 1820 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[16] 1787 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[27] 1883 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1272 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[5] 1599 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][11] 1645 19
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[26] 1901 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[8] 1667 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2268 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[12] 1823 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[31] 1591 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1825 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1345 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[9] 1593 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[0] 1621 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1598 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[5] 1647 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/ngrst2rst_0/pulse 1371 61
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[0] 1673 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 625 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[26] 1774 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 710 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_8_i 1562 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_count_RNO[2] 1443 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[1] 1708 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 888 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 2040 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[8] 1692 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[2] 1670 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][5] 1762 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[5] 1713 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_5_inst 1815 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rst_rA_0 835 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/dvalid_pipe_0/delayLine[0] 680 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[6] 1648 27
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[13] 1172 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[29] 1720 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1710 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_c/genblk1.delayLine[0][13] 1672 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m43 1492 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[31] 1850 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_20 1545 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][11] 1767 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2292 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[18] 1798 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][0] 1550 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/OEN_RNO_1 1472 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[14] 1811 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][10] 1734 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_10_i 1575 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 421 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[0][4] 1567 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[16] 1796 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1585 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[12] 1688 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 540 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[4] 1626 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[6] 1650 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[3] 1571 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[25] 1728 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2[7] 1732 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/RAM_REN_RNO 1549 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 236 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[6] 1159 43
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/DATA_I_VALID 1358 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[31] 1700 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1249 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/startFFT_g4_dly_0/genblk1.delayLine[0] 1625 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1980 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 1260 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[23] 1753 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[13] 1770 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 564 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_5_inst 1809 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[15] 1140 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_RNIHDED[6] 811 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[9] 1758 55
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA_0_RNIQH5D 1186 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_0_a3_0_3_0[6] 1242 42
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[0] 1727 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[26] 1905 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 1537 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[15] 1811 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 697 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 222 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[7] 1644 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[13] 1817 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1653 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[7] 1614 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[12] 1806 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0_RNO 233 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/CFG2_BLKZ0[0] 1632 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[1] 1639 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_4_inst 1804 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[3] 1599 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][6] 1754 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1140 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1188 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_nss_i[0] 1285 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][6] 1753 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2202 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 444 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[15] 1807 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1704 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[7] 1631 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1453 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 302 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[5] 1196 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[7] 1728 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 300 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[3] 1657 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wStage_r_5[2] 1585 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[3] 1026 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WADDR[6] 1237 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1392 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 289 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[31] 1776 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[19] 1800 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[8] 1689 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[3] 1219 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[2][12] 1733 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[8] 1739 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1640 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1597 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_2 1119 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_rx_en_2_sqmuxa_i_a2 1517 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1884 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1694 28
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[9] 1733 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[1] 1735 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1804 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[10] 1556 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/cvalid_pipe_0/delayLine[0] 1120 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNI1OL01[10] 1606 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 2030 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1789 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 667 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[25] 1728 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/preOutBuf_wEn_1_sqmuxa_1_0_a2 1611 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[9] 1147 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1526 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsmce[6] 1492 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[12] 1809 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[20] 1821 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_1_inst 1811 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[2] 1730 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2140 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[14] 1815 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1056 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[5] 686 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m157_1_0 1550 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[6] 1618 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[23] 1872 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[15] 1689 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[1] 1728 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1694 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 854 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1621 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[28] 1782 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[12] 1820 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 326 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1584 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1728 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 445 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[16] 1783 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[2] 1653 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][10] 1766 22
set_location PF_COREUART_0_0/PF_COREUART_0_0/tx_hold_reg[0] 1666 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[1] 1217 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_lm_0[8] 1588 45
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FIR_WR_ADDR[7] 1130 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1416 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 350 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[7] 1648 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/CFG2_BLKZ0[1] 1550 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[18] 1811 54
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_lm_0[8] 1736 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[18] 1821 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[20] 1768 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_1_inst 1903 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[2] 1345 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 408 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][8] 1752 28
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_nss_i_0_i_a2_3[0] 1488 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 864 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[1] 1633 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/valid_pipe_0/delayLine[1] 1998 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][8] 1758 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1778 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 705 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[9] 1698 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m268 1505 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[1][4] 1656 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_w[7] 1705 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP[29] 1779 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1357 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[15] 1796 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[9] 1637 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_C2_1.SUM[1] 230 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][6] 1711 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r1[2] 1603 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/genblk1.dly_d/genblk1.delayLine[0][10] 1581 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 673 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2] 1204 79
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[11] 1840 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_4_inst 1636 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][13] 1768 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit 1537 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_3_inst 1657 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 192 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[4] 1669 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[15] 1819 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1836 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[1] 1635 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[5] 1714 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m32 1490 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[20] 1800 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[2] 1709 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rTimer_dly2/genblk1.delayLine[1][1] 1539 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][0] 1652 25
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_2_0[5] 1730 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR[8] 1559 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1356 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[19] 1801 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/symm_data_pad.symm_data_pipe_0/delayLine_0[4] 1153 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[10] 1226 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_state[1] 1647 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[27] 1715 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 288 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 381 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/datai_re_r[11] 1814 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1441 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outQ[26] 1736 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 801 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[20] 1807 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 728 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/COEF_WEN_RNO 1355 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1849 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1874 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[0]_3 1574 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[24] 1831 33
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNO[13] 1201 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQi_w[15] 1693 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[2] 1218 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/latency_0/async2sync_0/delayLine[0] 1263 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 259 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 516 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[15] 1777 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[26] 1879 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1129 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1788 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 468 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_0_sqmuxa_1_0_a2_0_a2 1344 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[4] 1735 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask2_r[2] 1590 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/BLK_EN_inst 1525 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wEn_Q 1654 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_dly_2/genblk1.delayLine[0][2] 1614 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 863 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_1_inst 1812 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 2208 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11[0] 1711 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q[4] 1545 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_40_i 1491 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/genblk1.dly_c/genblk1.delayLine[0][6] 1642 25
set_location reset_sync_0/reset_sync_0/un1_PLL_POWERDOWN_B_i 1152 3
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1656 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[28] 1843 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/cvalid_pipe_0/delayLine[2] 1955 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1525 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 395 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_5_inst 1646 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/dvalid_pipe_0/delayLine[1] 1343 43
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/receive_full_int 1454 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[6] 1601 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[25] 1731 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][6] 1752 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1010 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_2_inst 1720 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_rA_r[1] 1710 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/FFT_RE_REN_0_a2 1552 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1284 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_3_inst 1719 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wEn_P 1655 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[0][8] 1692 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1176 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_CF2[1] 1138 55
set_location CFG0_GND_INST 1462 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1309 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1296 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m170_2 1526 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[29] 1790 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[4] 1560 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/cvalid_pipe_0/delayLine[1] 1118 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_lm_0[2] 800 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_RNI31N6[3] 814 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[28] 1776 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp[9] 1683 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 1128 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[21] 1797 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 553 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1908 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[2]_3 1580 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/dvalid_pipe_1/delayLine[1] 796 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[21] 1799 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask1_shft_stage_5 1573 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2184 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/un1_last_readout 1621 42
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[5] 1158 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[22] 1725 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1165 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/BLK_EN_inst 1752 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outQ[15] 1808 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[11] 1822 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 2148 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.wA_r[6] 1652 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_3_inst 815 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 504 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/timer_r[0] 1576 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/fftRd_done_r 1613 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2322 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_2_inst 1833 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1839 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 397 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rLastStage_r_3 1609 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 281 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1777 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT[2] 1695 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[25] 1833 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_lm_0[3] 839 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[8] 1588 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1873 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/OEN_RNO 1464 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[5]_3 1610 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[10] 1621 36
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[1] 1656 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1548 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/OEN_RNO_2 1475 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/dvalid_pipe_0/delayLine[0] 679 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/OR2_rD[31] 1873 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[23] 1703 27
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_clock_int_17_0_a2 1720 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][11] 1765 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outp_ready_r 1574 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inQr_w[5] 1635 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 679 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m103 1561 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[21] 1788 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_bflyRiskOV_w_1 1697 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1332 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[8] 960 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[0] 1705 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][8] 1762 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 325 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m76 1503 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m59_2_0 1536 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 900 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1764 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_5_inst 1918 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[11] 1737 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_2_RNO 1118 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/un1_RAM_REN_0_sqmuxa_1_i_a2_1_0 1180 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_twid_wEn 1630 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][10] 1773 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[23] 1698 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 718 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[17] 1654 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a3_0_4[10] 1565 42
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FILTER_COMPLETE 1291 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_2 225 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][12] 1774 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m283_1_2 1549 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_srsts_i_a2_0[5] 1203 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp[14] 1752 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 2016 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_WADDR[7] 1371 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[25] 1737 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 396 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r_RNO[0] 1572 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m256_2_1 1524 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1692 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1308 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[29] 1787 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 2132 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 2124 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1248 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/dvalid_pipe_0/delayLine[0] 1349 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_1_RNO 1129 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1069 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_4_inst 1882 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][10] 1761 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_3_RNO 1117 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/un1_bflyRiskOV_w_0 1696 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/BLK_EN_inst 780 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/valid_pipe_0/delayLine[0] 960 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[19] 1804 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 552 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1413 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_5 1137 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[17] 1810 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/bit_dly_0/genblk1.delayLine[1]_3 1572 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m41 1502 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_1_inst 1608 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_6 231 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smFft_run 1629 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m96_1_2 1490 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m137_i 1514 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[19] 1765 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 422 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[24] 1776 36
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RD_ENABLE 1197 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[15] 1543 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1164 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[28] 1832 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[8] 1664 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[12] 1811 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[12] 1799 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wP_w[4] 1710 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/autoScale_0/upScale 1701 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_WADDR[0] 1216 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1224 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q[3] 1612 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[26] 1757 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_4/genblk1.delayLine[1] 1620 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/smPong_RNIL8S3 1818 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 2119 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/addrP_w[5] 1606 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wP_w[31] 1869 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[12] 839 58
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[13] 708 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_4_RNICTRM 1128 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 621 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/stage_timer/Q_n3_i_o2 1589 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m97_1 1514 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 793 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[0] 1665 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/outBuf_wA_r[6] 1638 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/stage_tick[0] 1538 40
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_one_RNO 1723 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[15] 1801 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 803 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wQ_w[10] 1704 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1882 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[7] 1729 58
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[14] 1203 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA[0] 1596 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_lm_0[2] 1639 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/BLK_EN_inst 1584 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 1838 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 985 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q[0] 1595 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxQ_w[23] 1698 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 420 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_1[2] 1676 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 909 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR[0] 1153 43
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNIAU351[13] 1212 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[0] 1611 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/R_ADDR_1_inst 805 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_w[8] 1753 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxQ_w[13] 1790 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1837 46
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_ns_4_0_.m38_i_i 1294 42
set_location reset_sync_0/reset_sync_0/dff_4 1152 4
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 756 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/mask1_r[2] 1592 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm[8] 1496 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 355 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 1596 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q[3] 1669 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[14] 1724 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/left_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 661 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 2004 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 1009 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 1028 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[17] 1813 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[6] 1690 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1080 52
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.make_baud_cntr.baud_clock_int36 1719 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[9] 1068 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/leftQ_r[20] 1790 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[0] 1484 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 1783 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1945 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[15] 647 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/wA_w[6] 1649 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_2_inst 1524 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[6] 1632 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[7] 1714 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[13] 1793 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[8]_3 1609 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/twid_rA_0.tA_w_9_RNO_0 1536 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[25] 1592 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/BLK_EN_inst 1828 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m59_2_1 1548 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1440 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FFT_I_VALID_RNO 1290 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[8] 1689 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/R_ADDR_3_inst 1824 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.wA_r[1] 1646 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_7 1135 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/un1_rst 1638 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1344 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_5/genblk1.delayLine[1]_3 1626 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[1] 1670 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/valid_pipe_0/delayLine[2] 1824 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[31] 1702 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[4] 1661 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/OR2_rD[22] 1906 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/muxP_w[30] 1773 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshiftrff_1_RNIATRM 1134 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_4_inst 1823 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/FILTER_COMPLETE_RNO 1291 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2005 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[2] 1636 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[3] 1609 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outP[19] 1805 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[2] 1452 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[2] 1632 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 637 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 562 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/OR2_rD[31] 1764 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/preRstAfterInit_2 1539 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/R_ADDR_2_inst 804 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[6] 1536 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[13] 1542 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/mask2_r[0] 1572 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_rA_0/timer_tick_RNITLDV[3] 1541 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1761 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/tx_byte[0] 1664 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/valid_pipe_0/delayLine[2] 2087 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[13] 1889 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[1][14] 1764 22
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/loadOver_w_i_0 1641 39
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rw_dly_lastStage/genblk1.delayLine[1]_3 1608 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[9] 1731 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 274 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 1089 46
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/WDATA[8] 1186 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 984 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inQ_r[25] 1760 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[10] 672 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/rightP_r[31] 1781 34
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/DATA_OUT_11_0_1[2] 1697 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[0][7] 1754 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 852 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1008 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 756 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/R_ADDR_3_inst 1859 34
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/un1_rx_bit_cnt_1.CO0_m2_0_a2_1 1450 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_0_Or2_31 1576 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m277 1561 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[9] 1640 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/bit_dly_3/genblk1.delayLine[0]_3_0_a2 1608 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[19] 1811 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[3] 1647 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_1_inst 1853 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m272_1_0 1514 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[11] 1539 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 358 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[31] 1694 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[30] 1703 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[7] 1776 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_CF2_RNITU1I1[0] 220 54
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1596 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q[1] 1640 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 600 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/outQ[16] 1798 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1819 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[1] 2004 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshiftrff_0 226 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[11] 1816 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/outP[0] 1630 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/tc_3_0_a2_1_RNI366L 1586 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.N_37_i 1490 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/addrP_w[1] 1581 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m188 1502 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1715 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wA_w[2] 1633 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/dvalid_pipe_0/delayLine[2] 595 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1944 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m36 1503 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_3_inst 1548 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 329 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[2] 1638 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outPQ[20] 1801 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 204 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_3_inst 1620 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/dvalid_pipe_0/delayLine[1] 657 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/R_ADDR_2_inst 1787 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.6.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1440 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/R_ADDR_0_inst 1764 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.1.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 641 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 282 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[2][1] 1810 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/wA_r[5] 1723 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1668 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[10] 1707 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_4_inst 1718 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[9] 1836 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 1884 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][1] 1811 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/R_ADDR_5_inst 1531 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/muxP_w[6] 1650 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[4] 816 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPr_dly_0/genblk1.delayLine[3][11] 1721 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/symm_data_pad.symm_data_pipe_0/delayLine_0[12] 432 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[4] 808 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/inP_r[10] 1756 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[6] 1104 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1204 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[0] 2112 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.4.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 792 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outD[16] 1809 52
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_ON 1230 43
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[22] 1723 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[0] 1671 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/OR2_rD[23] 1576 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 308 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.5.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.3.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[5] 1608 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[3] 1647 37
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_lm_0[1] 1569 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/right_tap_0/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 336 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[11] 1429 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.outp_pipe_0/delayLine_0[1] 789 55
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/right_nibble.right_nibble_0/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 2180 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/postBflySw_0/outP[13] 1813 40
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/offsetPQ_r2[2] 1600 37
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/wQ_w[6] 1699 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_RX/rcv_cnt.receive_count_3_i_a4[0] 1447 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.3.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[12] 1128 52
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/rightP_r[26] 1734 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/inPi_dly_0/genblk1.delayLine[3][14] 1783 25
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m196_2 1502 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/R_ADDR_2_inst 1835 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/symm_data_pad.symm_data_pipe_0/delayLine_0[1] 893 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m154 1560 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/rA_r[6] 1548 34
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/OR2_rD[5] 1587 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.6.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.1.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[10] 1872 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/preBflySw_0/leftQ_r[17] 1730 28
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.4.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.5.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[8] 1428 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_lm_0[5] 1688 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/mid_nibbles.2.a_nibble/many_tap_nibble.many_tap_nibble_0/taps.2.atap/reload_shift_reg.shiftreg_section_0/delayLine_0[14] 744 46
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_bit_sel[3] 1653 46
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/OR2_R_DATA[10]\\ 836 57
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1848 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1596 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1752 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1752 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1512 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1704 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1788 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1896 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1716 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1608 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_1/mx_0/g5_macc.macc_0/MACC_PHYS_INST 1632 23
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1632 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1908 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_IN_BUF/PF_TPSRAM_1_0/PF_TPSRAM_1_PF_TPSRAM_1_0_PF_TPSRAM_R0C0 540 41
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/rows.1.a_row/left_nibble_0/many_tap_nibble.many_tap_nibble_0/left_tap_0/MACC_PA_BC_ROM_wrap_0/MACC_PA_BC_ROM_0/MACC_PHYS_0 72 50
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1764 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1812 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1884 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1656 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1584 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1824 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1776 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1800 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0 1128 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1920 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/genblk1.cmplx18_0/half_0/mx_0/g5_macc.macc_0/MACC_PHYS_INST 1560 23
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1812 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1692 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1728 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C0/RAM64x12_PHYS_0 780 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_FIR_OUT_BUF/PF_TPSRAM_2_0/PF_TPSRAM_2_PF_TPSRAM_2_0_PF_TPSRAM_R0C0 1752 41
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1872 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_RE_BUF/PF_TPSRAM_4_0/PF_TPSRAM_4_PF_TPSRAM_4_0_PF_TPSRAM_R0C0 1668 41
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C0/RAM64x12_PHYS_0 792 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COEF_BUF/PF_TPSRAM_0_0/PF_TPSRAM_0_PF_TPSRAM_0_0_PF_TPSRAM_R0C0 1128 41
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1824 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1764 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1524 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_1/RAM64x12_PHYS_0 228 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1548 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C0/RAM64x12_PHYS_0 1644 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1704 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_FFT_IM_BUF/PF_TPSRAM_3_0/PF_TPSRAM_3_PF_TPSRAM_3_0_PF_TPSRAM_R0C0 1704 41
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1572 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R0C1/RAM64x12_PHYS_0 804 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_0/RAM64x12_PHYS_0 216 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/enum_pad_g5_0/reload_coef_pad.symm_data_pipe_0/delayLine_seqshift_delayLine_seqshift_0_1/RAM64x12_PHYS_0 1104 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1560 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1788 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1620 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1836 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/genblk1.outBuff_0/outBuf_1/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1716 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C0/RAM64x12_PHYS_0 1668 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C1/RAM64x12_PHYS_0 1800 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.poBuf/genblk1.memQ/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R1C2/RAM64x12_PHYS_0 1680 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/twidLUT_1/twidLUT_0/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C1/RAM64x12_PHYS_0 1536 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/uram_wrap_0/uram_18x128.g5_uram18x128_0/g5_uram_18x128_R1C1/RAM64x12_PHYS_0 816 59
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/inBuf_0/genblk1.piBuf/genblk1.memP/PolarFire_uram.uram_0/PF_COREFFT_PF_COREFFT_0_uram_g5_R0C2/RAM64x12_PHYS_0 1860 32
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP_1_cry_0 1766 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp_int_s_1_467 1725 24
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR_cry_cy[0] 1152 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un3_outP_cry_0 1676 36
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE_0[0] 1122 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA_w_cry_0_0 1572 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_s_4 780 51
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp_int_s_1_466 1673 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA_w_cry_0_0 1596 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_s_463 1672 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q_cry_cy[0] 1540 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q_cry_cy[0] 1608 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_2_cry_0 1764 24
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP_0[8] 1215 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_s_462 1572 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un5_outQ_cry_0 1674 33
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_cry[0] 1716 60
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_s_464 1644 42
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP[8] 1230 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_s_465 1568 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_s_3 817 54
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE[0] 1363 42
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m146_1_0_wmux 1500 36
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m259_1_0_wmux 1521 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m59_1_0_wmux 1515 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m272_2_1_1_0_wmux 1512 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m196_1_0_0_wmux 1488 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m75_1_0_wmux 1510 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m95_1_0_wmux 1536 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m70_1_0_wmux 1518 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m29_1_0_wmux 1524 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m17_1_0_wmux 1512 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m105_1_0_wmux 1503 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m34_1_0_wmux 1560 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m47_1_0_wmux 1488 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m186_1_0_0_wmux 1572 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m253_1_0_wmux 1515 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m41_2_1_1_0_wmux 1500 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m236_1_0_wmux 1500 27
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m65_1_0_wmux 1512 33
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_0_31_0_.m97_2_1_1_1_wmux 1527 21
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_TX/xmit_sel.tx_2_u_i_m2_2_1_0_wmux 1656 45
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m19_1_0_wmux 1536 24
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m59_1_0_wmux 1524 21
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m229_1_0_wmux 1488 30
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/lut_0/T_1_00_31_0_.m84_1_0_wmux 1500 24
set_location reset_sync_0/reset_sync_0/dff_15_rep_GB_DEMOTE 1152 82
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB0 576 66
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB1 582 66
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB10 1747 12
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB2 1741 66
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB3 1747 66
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB4 576 39
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB5 582 39
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB6 1741 39
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB7 1747 39
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB8 582 12
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_RGB1_RGB9 1741 12
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider_inferred_clock_RNISVF8_0[2]/U0_RGB1_RGB0 1740 39
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB0 587 67
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB1 1745 67
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB2 581 40
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB3 587 40
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB4 1745 40
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_RGB1_RGB5 1751 40
set_location PF_ccc_0_0/PF_ccc_0_0/clkint_0/U0_GB0 1164 163
set_location reset_sync_0/reset_sync_0/dff_15_rep_RNIJHQ6/U0_GB0 1175 162
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_cry[0]_CC_0 1716 62
set_location PF_COREUART_0_0/PF_COREUART_0_0/make_CLOCK_GEN/genblk1.baud_cntr_cry[0]_CC_1 1728 62
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/COEF_RADDR_cry_cy[0]_CC_0 1152 44
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE[0]_CC_0 1363 44
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE[0]_CC_1 1368 44
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE_0[0]_CC_0 1122 44
set_location PF_DSP_FLOW_DEMO_TOP_0/FILTERCONTROL_FSM_0/fsm_i_RNIM2OE_0[0]_CC_1 1128 44
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp_int_s_1_467_CC_0 1725 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp_int_s_1_467_CC_1 1728 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHi_0/outp_int_s_1_467_CC_2 1752 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp_int_s_1_466_CC_0 1673 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/cmplx_0/rndHr_0/outp_int_s_1_466_CC_1 1680 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP_1_cry_0_CC_0 1766 29
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outP_1_cry_0_CC_1 1776 29
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_2_cry_0_CC_0 1764 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/outQ_2_cry_0_CC_1 1776 26
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un3_outP_cry_0_CC_0 1676 38
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un3_outP_cry_0_CC_1 1680 38
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un5_outQ_cry_0_CC_0 1674 35
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/bfly_0/un5_outQ_cry_0_CC_1 1680 35
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_ldA_0/ldCount/Q_s_464_CC_0 1644 44
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_rA_0/bflyA_w_cry_0_0_CC_0 1572 38
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/inBuf_wA_0/bflyA_w_cry_0_0_CC_0 1596 35
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/outBufA_0/outBuf_rA_0/Q_s_463_CC_0 1672 44
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_s_465_CC_0 1568 47
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/rdFFTtimer_0/rA_timer/Q_s_465_CC_1 1572 47
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/twid_wA_0/slowTimer/Q_cry_cy[0]_CC_0 1540 38
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/sm_0/wTimer_0/Q_cry_cy[0]_CC_0 1608 38
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/rAddr_0/count_s_3_CC_0 817 56
set_location PF_DSP_FLOW_DEMO_TOP_0/PF_COREFIR_0/PF_COREFIR_0/enum_g5.enum_fir_g5/adv_enum.adv_enum_0/dly_link_33/uRAM_shift_reg.uram_dly_0/wAddr_0/count_s_4_CC_0 780 53
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP[8]_CC_0 1230 44
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP[8]_CC_1 1236 44
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP_0[8]_CC_0 1215 44
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/rfsm_RNITPEP_0[8]_CC_1 1224 44
set_location PF_DSP_FLOW_DEMO_TOP_0/UART_IF_0/R_ADDR_s_462_CC_0 1572 44
