"PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q",,"PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q","PF_DSP_FLOW_DEMO_TOP_0/PF_COREFFT_0/PF_COREFFT_0/genblk1.DUT_INPLACE/slowClock_0/divider[2]:Q"
"PF_ccc_0_0/PF_ccc_0_0/pll_inst_0/OUT0",5,"PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0","PF_ccc_0_0/PF_ccc_0_0/pll_inst_0:OUT0"
"REF_CLK_0",20,"REF_CLK_0","REF_CLK_0"
