@W: BN132 :"c:\pf_task_jan_2021\test\dg0762\dg0762_fir_rtl\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\fftsm.v":675:2:675:7|Removing sequential instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer1_r[6:0] because it is equivalent to instance PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1.DUT_INPLACE.sm_0.inBuf_wA_0.timer_r[6:0]. To keep the instance, apply constraint syn_preserve=1 on the instance.
@W: FX1183 :"c:\pf_task_jan_2021\test\dg0762\dg0762_fir_rtl\libero_project\component\work\reset_sync\reset_sync_0\core\corereset_pf.v":58:0:58:5|User-specified initial value set for instance reset_sync_0.reset_sync_0.dff cannot be supported due to limitations in architecture. Please remove the initial value set on the instance to avoid the warning. 
@W: MT530 :"c:\pf_task_jan_2021\test\dg0762\dg0762_fir_rtl\libero_project\component\actel\directcore\corefft\7.1.100\rtl\in_place\vlog\core\kit.v":203:6:203:11|Found inferred clock fft_inpl_slowClock|divider_inferred_clock[2] which controls 22 sequential elements including PF_DSP_FLOW_DEMO_TOP_0.PF_COREFFT_0.PF_COREFFT_0.genblk1\.DUT_INPLACE.sm_0.twid_wA_0.ngrst2rst_0.sync_ngrst_0.genblk1\.delayLine\[3\]. This clock has no specified timing constraint which may adversely impact design performance. 
